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review.evervolv.com / android_kernel_oneplus_msm8996 / df14e4747aa58126a508ae26661c73d83127c831 / . / arch / arm / mach-omap2 / sram34xx.S
blob: 16eb4efa8b74bb4c2ecface214a97ddce1a33817 [file] [log] [blame]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]1/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]6 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]8 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]9 * Rajendra Nayak <rnayak@ti.com>
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]10 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]11 * Paul Walmsley
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#include <linux/linkage.h>
29#include <asm/assembler.h>
30#include <mach/hardware.h>
31
32#include <mach/io.h>
33
34#include "sdrc.h"
35#include "cm.h"
36
37 .text
38
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]39/* r4 parameters */
40#define SDRC_NO_UNLOCK_DLL 0x0
41#define SDRC_UNLOCK_DLL 0x1
42
43/* SDRC_DLLA_CTRL bit settings */
44#define DLLIDLE_MASK 0x4
45
46/* SDRC_DLLA_STATUS bit settings */
47#define LOCKSTATUS_MASK 0x4
48
49/* SDRC_POWER bit settings */
50#define SRFRONIDLEREQ_MASK 0x40
51#define PWDENA_MASK 0x4
52
53/* CM_IDLEST1_CORE bit settings */
54#define ST_SDRC_MASK 0x2
55
56/* CM_ICLKEN1_CORE bit settings */
57#define EN_SDRC_MASK 0x2
58
59/* CM_CLKSEL1_PLL bit settings */
60#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
61
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]62/*
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]63 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
64 * r0 = new SDRC_RFR_CTRL register contents
65 * r1 = new SDRC_ACTIM_CTRLA register contents
66 * r2 = new SDRC_ACTIM_CTRLB register contents
67 * r3 = new M2 divider setting (only 1 and 2 supported right now)
68 * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600[diff] [blame]69 * SDRC rates < 83MHz
Paul Walmsleyc9812d02009-06-19 19:08:26 -0600[diff] [blame]70 * r5 = number of MPU cycles to wait for SDRC to stabilize after
71 * reprogramming the SDRC when switching to a slower MPU speed
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]72 * r6 = new SDRC_MR_0 register value
Paul Walmsleyc9812d02009-06-19 19:08:26 -0600[diff] [blame]73 *
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]74 */
75ENTRY(omap3_sram_configure_core_dpll)
76 stmfd sp!, {r1-r12, lr} @ store regs to stack
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600[diff] [blame]77 ldr r4, [sp, #52] @ pull extra args off the stack
Paul Walmsleyc9812d02009-06-19 19:08:26 -0600[diff] [blame]78 ldr r5, [sp, #56] @ load extra args from the stack
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600[diff] [blame]79 ldr r6, [sp, #60] @ load extra args from the stack
Paul Walmsley69d42552009-05-12 17:27:09 -0600[diff] [blame]80 dsb @ flush buffered writes to interconnect
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]81 cmp r3, #0x2 @ if increasing SDRC clk rate,
82 blne configure_sdrc @ program the SDRC regs early (for RFR)
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]83 cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600[diff] [blame]84 bleq unlock_dll
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]85 blne lock_dll
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]86 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
87 bl configure_core_dpll @ change the DPLL3 M2 divider
88 bl enable_sdrc @ take SDRC out of idle
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]89 cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600[diff] [blame]90 bleq wait_dll_unlock
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]91 blne wait_dll_lock
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]92 cmp r3, #0x1 @ if increasing SDRC clk rate,
93 beq return_to_sdram @ return to SDRAM code, otherwise,
94 bl configure_sdrc @ reprogram SDRC regs now
95 mov r12, r5
96 bl wait_clk_stable @ wait for SDRC to stabilize
Paul Walmsleyc9812d02009-06-19 19:08:26 -0600[diff] [blame]97return_to_sdram:
Paul Walmsley69d42552009-05-12 17:27:09 -0600[diff] [blame]98 isb @ prevent speculative exec past here
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]99 mov r0, #0 @ return value
100 ldmfd sp!, {r1-r12, pc} @ restore regs and return
101unlock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]102 ldr r11, omap3_sdrc_dlla_ctrl
103 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]104 orr r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]105 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]106 bx lr
107lock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]108 ldr r11, omap3_sdrc_dlla_ctrl
109 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]110 bic r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]111 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]112 bx lr
113sdram_in_selfrefresh:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]114 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
115 ldr r12, [r11] @ read the contents of SDRC_POWER
116 mov r9, r12 @ keep a copy of SDRC_POWER bits
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]117 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
118 bic r12, r12, #PWDENA_MASK @ clear PWDENA
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]119 str r12, [r11] @ write back to SDRC_POWER register
120 ldr r12, [r11] @ posted-write barrier for SDRC
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600[diff] [blame]121idle_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]122 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
123 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]124 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]125 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]126wait_sdrc_idle:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]127 ldr r11, omap3_cm_idlest1_core
128 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]129 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
130 cmp r12, #ST_SDRC_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]131 bne wait_sdrc_idle
132 bx lr
133configure_core_dpll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]134 ldr r11, omap3_cm_clksel1_pll
135 ldr r12, [r11]
136 ldr r10, core_m2_mask_val @ modify m2 for core dpll
137 and r12, r12, r10
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]138 orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]139 str r12, [r11]
140 ldr r12, [r11] @ posted-write barrier for CM
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]141 bx lr
142wait_clk_stable:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]143 subs r12, r12, #1
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]144 bne wait_clk_stable
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]145 bx lr
146enable_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]147 ldr r11, omap3_cm_iclken1_core
148 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]149 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]150 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]151wait_sdrc_idle1:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]152 ldr r11, omap3_cm_idlest1_core
153 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]154 and r12, r12, #ST_SDRC_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]155 cmp r12, #0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]156 bne wait_sdrc_idle1
Paul Walmsleyfa0406a2009-05-12 17:27:09 -0600[diff] [blame]157restore_sdrc_power_val:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]158 ldr r11, omap3_sdrc_power
159 str r9, [r11] @ restore SDRC_POWER, no barrier needed
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]160 bx lr
161wait_dll_lock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]162 ldr r11, omap3_sdrc_dlla_status
163 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]164 and r12, r12, #LOCKSTATUS_MASK
165 cmp r12, #LOCKSTATUS_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]166 bne wait_dll_lock
167 bx lr
168wait_dll_unlock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]169 ldr r11, omap3_sdrc_dlla_status
170 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600[diff] [blame^]171 and r12, r12, #LOCKSTATUS_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]172 cmp r12, #0x0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]173 bne wait_dll_unlock
174 bx lr
175configure_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600[diff] [blame]176 ldr r11, omap3_sdrc_rfr_ctrl
177 str r0, [r11]
178 ldr r11, omap3_sdrc_actim_ctrla
179 str r1, [r11]
180 ldr r11, omap3_sdrc_actim_ctrlb
181 str r2, [r11]
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600[diff] [blame]182 ldr r11, omap3_sdrc_mr_0
183 str r6, [r11]
184 ldr r6, [r11] @ posted-write barrier for SDRC
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]185 bx lr
186
187omap3_sdrc_power:
188 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
189omap3_cm_clksel1_pll:
190 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
191omap3_cm_idlest1_core:
192 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
193omap3_cm_iclken1_core:
194 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
195omap3_sdrc_rfr_ctrl:
196 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
197omap3_sdrc_actim_ctrla:
198 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
199omap3_sdrc_actim_ctrlb:
200 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600[diff] [blame]201omap3_sdrc_mr_0:
202 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300[diff] [blame]203omap3_sdrc_dlla_status:
204 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
205omap3_sdrc_dlla_ctrl:
206 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
207core_m2_mask_val:
208 .word 0x07FFFFFF
209
210ENTRY(omap3_sram_configure_core_dpll_sz)
211 .word . - omap3_sram_configure_core_dpll