| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef _GT64111_H_ |
| 2 | #define _GT64111_H_ |
| 3 | |
| 4 | #define MASTER_INTERFACE 0x0 |
| 5 | #define RAS10_LO_DEC_ADR 0x8 |
| 6 | #define RAS10_HI_DEC_ADR 0x10 |
| 7 | #define RAS32_LO_DEC_ADR 0x18 |
| 8 | #define RAS32_HI_DEC_ADR 0x20 |
| 9 | #define CS20_LO_DEC_ADR 0x28 |
| 10 | #define CS20_HI_DEC_ADR 0x30 |
| 11 | #define CS3_LO_DEC_ADR 0x38 |
| 12 | #define CS3_HI_DEC_ADR 0x40 |
| 13 | #define PCI_IO_LO_DEC_ADR 0x48 |
| 14 | #define PCI_IO_HI_DEC_ADR 0x50 |
| 15 | #define PCI_MEM0_LO_DEC_ADR 0x58 |
| 16 | #define PCI_MEM0_HI_DEC_ADR 0x60 |
| 17 | #define INTERNAL_SPACE_DEC 0x68 |
| 18 | #define BUS_ERR_ADR_LO_CPU 0x70 |
| 19 | #define READONLY0 0x78 |
| 20 | #define PCI_MEM1_LO_DEC_ADR 0x80 |
| 21 | #define PCI_MEM1_HI_DEC_ADR 0x88 |
| 22 | #define RAS0_LO_DEC_ADR 0x400 |
| 23 | #define RAS0_HI_DEC_ADR 0x404 |
| 24 | #define RAS1_LO_DEC_ADR 0x408 |
| 25 | #define RAS1_HI_DEC_ADR 0x40c |
| 26 | #define RAS2_LO_DEC_ADR 0x410 |
| 27 | #define RAS2_HI_DEC_ADR 0x414 |
| 28 | #define RAS3_LO_DEC_ADR 0x418 |
| 29 | #define RAS3_HI_DEC_ADR 0x41c |
| 30 | #define DEV_CS0_LO_DEC_ADR 0x420 |
| 31 | #define DEV_CS0_HI_DEC_ADR 0x424 |
| 32 | #define DEV_CS1_LO_DEC_ADR 0x428 |
| 33 | #define DEV_CS1_HI_DEC_ADR 0x42c |
| 34 | #define DEV_CS2_LO_DEC_ADR 0x430 |
| 35 | #define DEV_CS2_HI_DEC_ADR 0x434 |
| 36 | #define DEV_CS3_LO_DEC_ADR 0x438 |
| 37 | #define DEV_CS3_HI_DEC_ADR 0x43c |
| 38 | #define DEV_BOOTCS_LO_DEC_ADR 0x440 |
| 39 | #define DEV_BOOTCS_HI_DEC_ADR 0x444 |
| 40 | #define DEV_ADR_DEC_ERR 0x470 |
| 41 | #define DRAM_CFG 0x448 |
| 42 | #define DRAM_BANK0_PARMS 0x44c |
| 43 | #define DRAM_BANK1_PARMS 0x450 |
| 44 | #define DRAM_BANK2_PARMS 0x454 |
| 45 | #define DRAM_BANK3_PARMS 0x458 |
| 46 | #define DEV_BANK0_PARMS 0x45c |
| 47 | #define DEV_BANK1_PARMS 0x460 |
| 48 | #define DEV_BANK2_PARMS 0x464 |
| 49 | #define DEV_BANK3_PARMS 0x468 |
| 50 | #define DEV_BOOT_BANK_PARMS 0x46c |
| 51 | #define CH0_DMA_BYTECOUNT 0x800 |
| 52 | #define CH1_DMA_BYTECOUNT 0x804 |
| 53 | #define CH2_DMA_BYTECOUNT 0x808 |
| 54 | #define CH3_DMA_BYTECOUNT 0x80c |
| 55 | #define CH0_DMA_SRC_ADR 0x810 |
| 56 | #define CH1_DMA_SRC_ADR 0x814 |
| 57 | #define CH2_DMA_SRC_ADR 0x818 |
| 58 | #define CH3_DMA_SRC_ADR 0x81c |
| 59 | #define CH0_DMA_DST_ADR 0x820 |
| 60 | #define CH1_DMA_DST_ADR 0x824 |
| 61 | #define CH2_DMA_DST_ADR 0x828 |
| 62 | #define CH3_DMA_DST_ADR 0x82c |
| 63 | #define CH0_NEXT_REC_PTR 0x830 |
| 64 | #define CH1_NEXT_REC_PTR 0x834 |
| 65 | #define CH2_NEXT_REC_PTR 0x838 |
| 66 | #define CH3_NEXT_REC_PTR 0x83c |
| 67 | #define CH0_CTRL 0x840 |
| 68 | #define CH1_CTRL 0x844 |
| 69 | #define CH2_CTRL 0x848 |
| 70 | #define CH3_CTRL 0x84c |
| 71 | #define DMA_ARBITER 0x860 |
| 72 | #define TIMER0 0x850 |
| 73 | #define TIMER1 0x854 |
| 74 | #define TIMER2 0x858 |
| 75 | #define TIMER3 0x85c |
| 76 | #define TIMER_CTRL 0x864 |
| 77 | #define PCI_CMD 0xc00 |
| 78 | #define PCI_TIMEOUT 0xc04 |
| 79 | #define PCI_RAS10_BANK_SIZE 0xc08 |
| 80 | #define PCI_RAS32_BANK_SIZE 0xc0c |
| 81 | #define PCI_CS20_BANK_SIZE 0xc10 |
| 82 | #define PCI_CS3_BANK_SIZE 0xc14 |
| 83 | #define PCI_SERRMASK 0xc28 |
| 84 | #define PCI_INTACK 0xc34 |
| 85 | #define PCI_BAR_EN 0xc3c |
| 86 | #define PCI_CFG_ADR 0xcf8 |
| 87 | #define PCI_CFG_DATA 0xcfc |
| 88 | #define PCI_INTCAUSE 0xc18 |
| 89 | #define PCI_MAST_MASK 0xc1c |
| 90 | #define PCI_PCIMASK 0xc24 |
| 91 | #define BAR_ENABLE_ADR 0xc3c |
| 92 | |
| 93 | /* These are config registers, accessible via PCI space */ |
| 94 | #define PCI_CONFIG_RAS10_BASE_ADR 0x010 |
| 95 | #define PCI_CONFIG_RAS32_BASE_ADR 0x014 |
| 96 | #define PCI_CONFIG_CS20_BASE_ADR 0x018 |
| 97 | #define PCI_CONFIG_CS3_BASE_ADR 0x01c |
| 98 | #define PCI_CONFIG_INT_REG_MM_ADR 0x020 |
| 99 | #define PCI_CONFIG_INT_REG_IO_ADR 0x024 |
| 100 | #define PCI_CONFIG_BOARD_VENDOR 0x02c |
| 101 | #define PCI_CONFIG_ROM_ADR 0x030 |
| 102 | #define PCI_CONFIG_INT_PIN_LINE 0x03c |
| 103 | |
| 104 | |
| 105 | |
| 106 | |
| 107 | |
| 108 | #endif |
| 109 | |