| Sri Deevi | e0d3baf | 2009-03-03 14:37:50 -0300 | [diff] [blame^] | 1 | /* |
| 2 | cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB |
| 3 | video capture devices |
| 4 | |
| 5 | Copyright (C) 2008 <srinivasa.deevi at conexant dot com> |
| 6 | |
| 7 | This program is free software; you can redistribute it and/or modify |
| 8 | it under the terms of the GNU General Public License as published by |
| 9 | the Free Software Foundation; either version 2 of the License, or |
| 10 | (at your option) any later version. |
| 11 | |
| 12 | This program is distributed in the hope that it will be useful, |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | GNU General Public License for more details. |
| 16 | |
| 17 | You should have received a copy of the GNU General Public License |
| 18 | along with this program; if not, write to the Free Software |
| 19 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 20 | */ |
| 21 | |
| 22 | |
| 23 | #ifndef _POLARIS_REG_H_ |
| 24 | #define _POLARIS_REG_H_ |
| 25 | |
| 26 | #define BOARD_CFG_STAT 0x0 |
| 27 | #define TS_MODE_REG 0x4 |
| 28 | #define TS1_CFG_REG 0x8 |
| 29 | #define TS1_LENGTH_REG 0xc |
| 30 | #define TS2_CFG_REG 0x10 |
| 31 | #define TS2_LENGTH_REG 0x14 |
| 32 | #define EP_MODE_SET 0x18 |
| 33 | #define CIR_PWR_PTN1 0x1c |
| 34 | #define CIR_PWR_PTN2 0x20 |
| 35 | #define CIR_PWR_PTN3 0x24 |
| 36 | #define CIR_PWR_MASK0 0x28 |
| 37 | #define CIR_PWR_MASK1 0x2c |
| 38 | #define CIR_PWR_MASK2 0x30 |
| 39 | #define CIR_GAIN 0x34 |
| 40 | #define CIR_CAR_REG 0x38 |
| 41 | #define CIR_OT_CFG1 0x40 |
| 42 | #define CIR_OT_CFG2 0x44 |
| 43 | #define PWR_CTL_EN 0x74 |
| 44 | |
| 45 | /* Polaris Endpoints capture mask for register EP_MODE_SET */ |
| 46 | #define ENABLE_EP1 0x01 /* Bit[0]=1 */ |
| 47 | #define ENABLE_EP2 0x02 /* Bit[1]=1 */ |
| 48 | #define ENABLE_EP3 0x04 /* Bit[2]=1 */ |
| 49 | #define ENABLE_EP4 0x08 /* Bit[3]=1 */ |
| 50 | #define ENABLE_EP5 0x10 /* Bit[4]=1 */ |
| 51 | #define ENABLE_EP6 0x20 /* Bit[5]=1 */ |
| 52 | |
| 53 | /* Bit definition for register PWR_CTL_EN */ |
| 54 | #define PWR_MODE_MASK 0x17f |
| 55 | #define PWR_AV_EN 0x08 /* bit3 */ |
| 56 | #define PWR_ISO_EN 0x40 /* bit6 */ |
| 57 | #define PWR_AV_MODE 0x30 /* bit4,5 */ |
| 58 | #define PWR_TUNER_EN 0x04 /* bit2 */ |
| 59 | #define PWR_DEMOD_EN 0x02 /* bit1 */ |
| 60 | #define I2C_DEMOD_EN 0x01 /* bit0 */ |
| 61 | #define PWR_RESETOUT_EN 0x100 /* bit8 */ |
| 62 | |
| 63 | typedef enum{ |
| 64 | POLARIS_AVMODE_DEFAULT = 0, |
| 65 | POLARIS_AVMODE_DIGITAL = 0x10, |
| 66 | POLARIS_AVMODE_ANALOGT_TV = 0x20, |
| 67 | POLARIS_AVMODE_ENXTERNAL_AV = 0x30, |
| 68 | |
| 69 | }AV_MODE; |
| 70 | |
| 71 | /* Colibri Registers */ |
| 72 | |
| 73 | #define SINGLE_ENDED 0x0 |
| 74 | #define LOW_IF 0x4 |
| 75 | #define EU_IF 0x9 |
| 76 | #define US_IF 0xa |
| 77 | |
| 78 | |
| 79 | |
| 80 | #define SUP_BLK_TUNE1 0x00 |
| 81 | #define SUP_BLK_TUNE2 0x01 |
| 82 | #define SUP_BLK_TUNE3 0x02 |
| 83 | #define SUP_BLK_XTAL 0x03 |
| 84 | #define SUP_BLK_PLL1 0x04 |
| 85 | #define SUP_BLK_PLL2 0x05 |
| 86 | #define SUP_BLK_PLL3 0x06 |
| 87 | #define SUP_BLK_REF 0x07 |
| 88 | #define SUP_BLK_PWRDN 0x08 |
| 89 | #define SUP_BLK_TESTPAD 0x09 |
| 90 | #define ADC_COM_INT5_STAB_REF 0x0a |
| 91 | #define ADC_COM_QUANT 0x0b |
| 92 | #define ADC_COM_BIAS1 0x0c |
| 93 | #define ADC_COM_BIAS2 0x0d |
| 94 | #define ADC_COM_BIAS3 0x0e |
| 95 | #define TESTBUS_CTRL 0x12 |
| 96 | |
| 97 | #define ADC_STATUS_CH1 0x20 |
| 98 | #define ADC_STATUS_CH2 0x40 |
| 99 | #define ADC_STATUS_CH3 0x60 |
| 100 | |
| 101 | #define ADC_STATUS2_CH1 0x21 |
| 102 | #define ADC_STATUS2_CH2 0x41 |
| 103 | #define ADC_STATUS2_CH3 0x61 |
| 104 | |
| 105 | #define ADC_CAL_ATEST_CH1 0x22 |
| 106 | #define ADC_CAL_ATEST_CH2 0x42 |
| 107 | #define ADC_CAL_ATEST_CH3 0x62 |
| 108 | |
| 109 | #define ADC_PWRDN_CLAMP_CH1 0x23 |
| 110 | #define ADC_PWRDN_CLAMP_CH2 0x43 |
| 111 | #define ADC_PWRDN_CLAMP_CH3 0x63 |
| 112 | |
| 113 | #define ADC_CTRL_DAC23_CH1 0x24 |
| 114 | #define ADC_CTRL_DAC23_CH2 0x44 |
| 115 | #define ADC_CTRL_DAC23_CH3 0x64 |
| 116 | |
| 117 | #define ADC_CTRL_DAC1_CH1 0x25 |
| 118 | #define ADC_CTRL_DAC1_CH2 0x45 |
| 119 | #define ADC_CTRL_DAC1_CH3 0x65 |
| 120 | |
| 121 | #define ADC_DCSERVO_DEM_CH1 0x26 |
| 122 | #define ADC_DCSERVO_DEM_CH2 0x46 |
| 123 | #define ADC_DCSERVO_DEM_CH3 0x66 |
| 124 | |
| 125 | #define ADC_FB_FRCRST_CH1 0x27 |
| 126 | #define ADC_FB_FRCRST_CH2 0x47 |
| 127 | #define ADC_FB_FRCRST_CH3 0x67 |
| 128 | |
| 129 | #define ADC_INPUT_CH1 0x28 |
| 130 | #define ADC_INPUT_CH2 0x48 |
| 131 | #define ADC_INPUT_CH3 0x68 |
| 132 | #define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ |
| 133 | |
| 134 | #define ADC_NTF_PRECLMP_EN_CH1 0x29 |
| 135 | #define ADC_NTF_PRECLMP_EN_CH2 0x49 |
| 136 | #define ADC_NTF_PRECLMP_EN_CH3 0x69 |
| 137 | |
| 138 | #define ADC_QGAIN_RES_TRM_CH1 0x2a |
| 139 | #define ADC_QGAIN_RES_TRM_CH2 0x4a |
| 140 | #define ADC_QGAIN_RES_TRM_CH3 0x6a |
| 141 | |
| 142 | #define ADC_SOC_PRECLMP_TERM_CH1 0x2b |
| 143 | #define ADC_SOC_PRECLMP_TERM_CH2 0x4b |
| 144 | #define ADC_SOC_PRECLMP_TERM_CH3 0x6b |
| 145 | |
| 146 | #define TESTBUS_CTRL_CH1 0x32 |
| 147 | #define TESTBUS_CTRL_CH2 0x52 |
| 148 | #define TESTBUS_CTRL_CH3 0x72 |
| 149 | |
| 150 | /****************************************************************************** |
| 151 | * DIF registers * |
| 152 | ******************************************************************************/ |
| 153 | #define DIRECT_IF_REVB_BASE 0x00300 |
| 154 | |
| 155 | /*****************************************************************************/ |
| 156 | #define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */ |
| 157 | /*****************************************************************************/ |
| 158 | #define FLD_DIF_PLL_LOCK 0x80000000 |
| 159 | /* Reserved [30:29] */ |
| 160 | #define FLD_DIF_PLL_FREE_RUN 0x10000000 |
| 161 | #define FLD_DIF_PLL_FREQ 0x0FFFFFFF |
| 162 | |
| 163 | /*****************************************************************************/ |
| 164 | #define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */ |
| 165 | /*****************************************************************************/ |
| 166 | #define FLD_DIF_KD_PD 0xFF000000 |
| 167 | /* Reserved [23:20] */ |
| 168 | #define FLD_DIF_KDS_PD 0x000F0000 |
| 169 | #define FLD_DIF_KI_PD 0x0000FF00 |
| 170 | /* Reserved [7:4] */ |
| 171 | #define FLD_DIF_KIS_PD 0x0000000F |
| 172 | |
| 173 | /*****************************************************************************/ |
| 174 | #define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */ |
| 175 | /*****************************************************************************/ |
| 176 | #define FLD_DIF_KD_FD 0xFF000000 |
| 177 | /* Reserved [23:20] */ |
| 178 | #define FLD_DIF_KDS_FD 0x000F0000 |
| 179 | #define FLD_DIF_KI_FD 0x0000FF00 |
| 180 | #define FLD_DIF_SIG_PROP_SZ 0x000000F0 |
| 181 | #define FLD_DIF_KIS_FD 0x0000000F |
| 182 | |
| 183 | /*****************************************************************************/ |
| 184 | #define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */ |
| 185 | /*****************************************************************************/ |
| 186 | #define FLD_DIF_PLL_AGC_REF 0xFFF00000 |
| 187 | #define FLD_DIF_PLL_AGC_KI 0x000F0000 |
| 188 | /* Reserved [15] */ |
| 189 | #define FLD_DIF_FREQ_LIMIT 0x00007000 |
| 190 | #define FLD_DIF_K_FD 0x00000F00 |
| 191 | #define FLD_DIF_DOWNSMPL_FD 0x000000FF |
| 192 | |
| 193 | /*****************************************************************************/ |
| 194 | #define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */ |
| 195 | /*****************************************************************************/ |
| 196 | /* Reserved [31:16] */ |
| 197 | #define FLD_DIF_PLL_AGC_EN 0x00008000 |
| 198 | /* Reserved [14:12] */ |
| 199 | #define FLD_DIF_PLL_MAN_GAIN 0x00000FFF |
| 200 | |
| 201 | /*****************************************************************************/ |
| 202 | #define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */ |
| 203 | /*****************************************************************************/ |
| 204 | #define FLD_DIF_K_AGC_RF 0xF0000000 |
| 205 | #define FLD_DIF_K_AGC_IF 0x0F000000 |
| 206 | #define FLD_DIF_K_AGC_INT 0x00F00000 |
| 207 | /* Reserved [19:12] */ |
| 208 | #define FLD_DIF_IF_REF 0x00000FFF |
| 209 | |
| 210 | /*****************************************************************************/ |
| 211 | #define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */ |
| 212 | /*****************************************************************************/ |
| 213 | #define FLD_DIF_IF_MAX 0xFF000000 |
| 214 | #define FLD_DIF_IF_MIN 0x00FF0000 |
| 215 | #define FLD_DIF_IF_AGC 0x0000FFFF |
| 216 | |
| 217 | /*****************************************************************************/ |
| 218 | #define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */ |
| 219 | /*****************************************************************************/ |
| 220 | #define FLD_DIF_INT_MAX 0xFF000000 |
| 221 | #define FLD_DIF_INT_MIN 0x00FF0000 |
| 222 | #define FLD_DIF_INT_AGC 0x0000FFFF |
| 223 | |
| 224 | /*****************************************************************************/ |
| 225 | #define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */ |
| 226 | /*****************************************************************************/ |
| 227 | #define FLD_DIF_RF_MAX 0xFF000000 |
| 228 | #define FLD_DIF_RF_MIN 0x00FF0000 |
| 229 | #define FLD_DIF_RF_AGC 0x0000FFFF |
| 230 | |
| 231 | /*****************************************************************************/ |
| 232 | #define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */ |
| 233 | /*****************************************************************************/ |
| 234 | #define FLD_DIF_IF_AGC_IN 0xFFFF0000 |
| 235 | #define FLD_DIF_INT_AGC_IN 0x0000FFFF |
| 236 | |
| 237 | /*****************************************************************************/ |
| 238 | #define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */ |
| 239 | /*****************************************************************************/ |
| 240 | /* Reserved [31:16] */ |
| 241 | #define FLD_DIF_RF_AGC_IN 0x0000FFFF |
| 242 | |
| 243 | /*****************************************************************************/ |
| 244 | #define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */ |
| 245 | /*****************************************************************************/ |
| 246 | #define FLD_DIF_AFD 0xC0000000 |
| 247 | #define FLD_DIF_K_VID_AGC 0x30000000 |
| 248 | #define FLD_DIF_LINE_LENGTH 0x0FFF0000 |
| 249 | #define FLD_DIF_AGC_GAIN 0x0000FFFF |
| 250 | |
| 251 | /*****************************************************************************/ |
| 252 | #define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */ |
| 253 | /*****************************************************************************/ |
| 254 | #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 |
| 255 | /* Reserved [30:30] */ |
| 256 | #define FLD_DIF_AUDIO_MAN_GAIN 0x3F000000 |
| 257 | /* Reserved [23:17] */ |
| 258 | #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 |
| 259 | #define FLD_DIF_VID_MAN_GAIN 0x0000FFFF |
| 260 | |
| 261 | /*****************************************************************************/ |
| 262 | #define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */ |
| 263 | /*****************************************************************************/ |
| 264 | #define FLD_DIF_LPF_FREQ 0xC0000000 |
| 265 | #define FLD_DIF_AV_PHASE_INC 0x3F000000 |
| 266 | #define FLD_DIF_AUDIO_FREQ 0x00FFFFFF |
| 267 | |
| 268 | /*****************************************************************************/ |
| 269 | #define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */ |
| 270 | /*****************************************************************************/ |
| 271 | /* Reserved [31:24] */ |
| 272 | #define FLD_DIF_IIR23_R2 0x00FF0000 |
| 273 | #define FLD_DIF_IIR23_R1 0x0000FF00 |
| 274 | #define FLD_DIF_IIR1_R1 0x000000FF |
| 275 | |
| 276 | /*****************************************************************************/ |
| 277 | #define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */ |
| 278 | /*****************************************************************************/ |
| 279 | #define FLD_DIF_DIF_BYPASS 0x80000000 |
| 280 | #define FLD_DIF_FM_NYQ_GAIN 0x40000000 |
| 281 | #define FLD_DIF_RF_AGC_ENA 0x20000000 |
| 282 | #define FLD_DIF_INT_AGC_ENA 0x10000000 |
| 283 | #define FLD_DIF_IF_AGC_ENA 0x08000000 |
| 284 | #define FLD_DIF_FORCE_RF_IF_LOCK 0x04000000 |
| 285 | #define FLD_DIF_VIDEO_AGC_ENA 0x02000000 |
| 286 | #define FLD_DIF_RF_AGC_INV 0x01000000 |
| 287 | #define FLD_DIF_INT_AGC_INV 0x00800000 |
| 288 | #define FLD_DIF_IF_AGC_INV 0x00400000 |
| 289 | #define FLD_DIF_SPEC_INV 0x00200000 |
| 290 | #define FLD_DIF_AUD_FULL_BW 0x00100000 |
| 291 | #define FLD_DIF_AUD_SRC_SEL 0x00080000 |
| 292 | /* Reserved [18] */ |
| 293 | #define FLD_DIF_IF_FREQ 0x00030000 |
| 294 | /* Reserved [15:14] */ |
| 295 | #define FLD_DIF_TIP_OFFSET 0x00003F00 |
| 296 | /* Reserved [7:5] */ |
| 297 | #define FLD_DIF_DITHER_ENA 0x00000010 |
| 298 | /* Reserved [3:1] */ |
| 299 | #define FLD_DIF_RF_IF_LOCK 0x00000001 |
| 300 | |
| 301 | /*****************************************************************************/ |
| 302 | #define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */ |
| 303 | /*****************************************************************************/ |
| 304 | /* Reserved [31:29] */ |
| 305 | #define FLD_DIF_PHASE_INC 0x1FFFFFFF |
| 306 | |
| 307 | /*****************************************************************************/ |
| 308 | #define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */ |
| 309 | /*****************************************************************************/ |
| 310 | /* Reserved [31:16] */ |
| 311 | #define FLD_DIF_SRC_KI 0x0000FF00 |
| 312 | #define FLD_DIF_SRC_KD 0x000000FF |
| 313 | |
| 314 | /*****************************************************************************/ |
| 315 | #define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */ |
| 316 | /*****************************************************************************/ |
| 317 | /* Reserved [31:19] */ |
| 318 | #define FLD_DIF_BPF_COEFF_0 0x00070000 |
| 319 | /* Reserved [15:4] */ |
| 320 | #define FLD_DIF_BPF_COEFF_1 0x0000000F |
| 321 | |
| 322 | /*****************************************************************************/ |
| 323 | #define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */ |
| 324 | /*****************************************************************************/ |
| 325 | /* Reserved [31:22] */ |
| 326 | #define FLD_DIF_BPF_COEFF_2 0x003F0000 |
| 327 | /* Reserved [15:7] */ |
| 328 | #define FLD_DIF_BPF_COEFF_3 0x0000007F |
| 329 | |
| 330 | /*****************************************************************************/ |
| 331 | #define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */ |
| 332 | /*****************************************************************************/ |
| 333 | /* Reserved [31:24] */ |
| 334 | #define FLD_DIF_BPF_COEFF_4 0x00FF0000 |
| 335 | /* Reserved [15:8] */ |
| 336 | #define FLD_DIF_BPF_COEFF_5 0x000000FF |
| 337 | |
| 338 | /*****************************************************************************/ |
| 339 | #define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */ |
| 340 | /*****************************************************************************/ |
| 341 | /* Reserved [31:25] */ |
| 342 | #define FLD_DIF_BPF_COEFF_6 0x01FF0000 |
| 343 | /* Reserved [15:9] */ |
| 344 | #define FLD_DIF_BPF_COEFF_7 0x000001FF |
| 345 | |
| 346 | /*****************************************************************************/ |
| 347 | #define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */ |
| 348 | /*****************************************************************************/ |
| 349 | /* Reserved [31:26] */ |
| 350 | #define FLD_DIF_BPF_COEFF_8 0x03FF0000 |
| 351 | /* Reserved [15:10] */ |
| 352 | #define FLD_DIF_BPF_COEFF_9 0x000003FF |
| 353 | |
| 354 | /*****************************************************************************/ |
| 355 | #define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */ |
| 356 | /*****************************************************************************/ |
| 357 | /* Reserved [31:27] */ |
| 358 | #define FLD_DIF_BPF_COEFF_10 0x07FF0000 |
| 359 | /* Reserved [15:11] */ |
| 360 | #define FLD_DIF_BPF_COEFF_11 0x000007FF |
| 361 | |
| 362 | /*****************************************************************************/ |
| 363 | #define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */ |
| 364 | /*****************************************************************************/ |
| 365 | /* Reserved [31:27] */ |
| 366 | #define FLD_DIF_BPF_COEFF_12 0x07FF0000 |
| 367 | /* Reserved [15:12] */ |
| 368 | #define FLD_DIF_BPF_COEFF_13 0x00000FFF |
| 369 | |
| 370 | /*****************************************************************************/ |
| 371 | #define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */ |
| 372 | /*****************************************************************************/ |
| 373 | /* Reserved [31:28] */ |
| 374 | #define FLD_DIF_BPF_COEFF_14 0x0FFF0000 |
| 375 | /* Reserved [15:12] */ |
| 376 | #define FLD_DIF_BPF_COEFF_15 0x00000FFF |
| 377 | |
| 378 | /*****************************************************************************/ |
| 379 | #define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */ |
| 380 | /*****************************************************************************/ |
| 381 | /* Reserved [31:29] */ |
| 382 | #define FLD_DIF_BPF_COEFF_16 0x1FFF0000 |
| 383 | /* Reserved [15:13] */ |
| 384 | #define FLD_DIF_BPF_COEFF_17 0x00001FFF |
| 385 | |
| 386 | /*****************************************************************************/ |
| 387 | #define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */ |
| 388 | /*****************************************************************************/ |
| 389 | /* Reserved [31:29] */ |
| 390 | #define FLD_DIF_BPF_COEFF_18 0x1FFF0000 |
| 391 | /* Reserved [15:13] */ |
| 392 | #define FLD_DIF_BPF_COEFF_19 0x00001FFF |
| 393 | |
| 394 | /*****************************************************************************/ |
| 395 | #define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */ |
| 396 | /*****************************************************************************/ |
| 397 | /* Reserved [31:29] */ |
| 398 | #define FLD_DIF_BPF_COEFF_20 0x1FFF0000 |
| 399 | /* Reserved [15:14] */ |
| 400 | #define FLD_DIF_BPF_COEFF_21 0x00003FFF |
| 401 | |
| 402 | /*****************************************************************************/ |
| 403 | #define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */ |
| 404 | /*****************************************************************************/ |
| 405 | /* Reserved [31:30] */ |
| 406 | #define FLD_DIF_BPF_COEFF_22 0x3FFF0000 |
| 407 | /* Reserved [15:14] */ |
| 408 | #define FLD_DIF_BPF_COEFF_23 0x00003FFF |
| 409 | |
| 410 | /*****************************************************************************/ |
| 411 | #define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */ |
| 412 | /*****************************************************************************/ |
| 413 | /* Reserved [31:30] */ |
| 414 | #define FLD_DIF_BPF_COEFF_24 0x3FFF0000 |
| 415 | /* Reserved [15:14] */ |
| 416 | #define FLD_DIF_BPF_COEFF_25 0x00003FFF |
| 417 | |
| 418 | /*****************************************************************************/ |
| 419 | #define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */ |
| 420 | /*****************************************************************************/ |
| 421 | /* Reserved [31:30] */ |
| 422 | #define FLD_DIF_BPF_COEFF_26 0x3FFF0000 |
| 423 | /* Reserved [15:14] */ |
| 424 | #define FLD_DIF_BPF_COEFF_27 0x00003FFF |
| 425 | |
| 426 | /*****************************************************************************/ |
| 427 | #define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */ |
| 428 | /*****************************************************************************/ |
| 429 | /* Reserved [31:30] */ |
| 430 | #define FLD_DIF_BPF_COEFF_28 0x3FFF0000 |
| 431 | /* Reserved [15:14] */ |
| 432 | #define FLD_DIF_BPF_COEFF_29 0x00003FFF |
| 433 | |
| 434 | /*****************************************************************************/ |
| 435 | #define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */ |
| 436 | /*****************************************************************************/ |
| 437 | /* Reserved [31:30] */ |
| 438 | #define FLD_DIF_BPF_COEFF_30 0x3FFF0000 |
| 439 | /* Reserved [15:14] */ |
| 440 | #define FLD_DIF_BPF_COEFF_31 0x00003FFF |
| 441 | |
| 442 | /*****************************************************************************/ |
| 443 | #define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */ |
| 444 | /*****************************************************************************/ |
| 445 | /* Reserved [31:30] */ |
| 446 | #define FLD_DIF_BPF_COEFF_32 0x3FFF0000 |
| 447 | /* Reserved [15:14] */ |
| 448 | #define FLD_DIF_BPF_COEFF_33 0x00003FFF |
| 449 | |
| 450 | /*****************************************************************************/ |
| 451 | #define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */ |
| 452 | /*****************************************************************************/ |
| 453 | /* Reserved [31:30] */ |
| 454 | #define FLD_DIF_BPF_COEFF_34 0x3FFF0000 |
| 455 | /* Reserved [15:14] */ |
| 456 | #define FLD_DIF_BPF_COEFF_35 0x00003FFF |
| 457 | |
| 458 | /*****************************************************************************/ |
| 459 | #define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */ |
| 460 | /*****************************************************************************/ |
| 461 | /* Reserved [31:30] */ |
| 462 | #define FLD_DIF_BPF_COEFF_36 0x3FFF0000 |
| 463 | /* Reserved [15:0] */ |
| 464 | |
| 465 | /*****************************************************************************/ |
| 466 | #define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */ |
| 467 | /*****************************************************************************/ |
| 468 | /* Reserved [31:20] */ |
| 469 | #define FLD_DIF_RPT_VARIANCE 0x000FFFFF |
| 470 | |
| 471 | /*****************************************************************************/ |
| 472 | #define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */ |
| 473 | /*****************************************************************************/ |
| 474 | /* Reserved [31:8] */ |
| 475 | #define FLD_DIF_DIF_SOFT_RST 0x00000080 |
| 476 | #define FLD_DIF_DIF_REG_RST_MSK 0x00000040 |
| 477 | #define FLD_DIF_AGC_RST_MSK 0x00000020 |
| 478 | #define FLD_DIF_CMP_RST_MSK 0x00000010 |
| 479 | #define FLD_DIF_AVS_RST_MSK 0x00000008 |
| 480 | #define FLD_DIF_NYQ_RST_MSK 0x00000004 |
| 481 | #define FLD_DIF_DIF_SRC_RST_MSK 0x00000002 |
| 482 | #define FLD_DIF_PLL_RST_MSK 0x00000001 |
| 483 | |
| 484 | /*****************************************************************************/ |
| 485 | #define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */ |
| 486 | /*****************************************************************************/ |
| 487 | /* Reserved [31:25] */ |
| 488 | #define FLD_DIF_CTL_IP 0x01FFFFFF |
| 489 | |
| 490 | |
| 491 | #endif |