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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
Ralf Baechle27f76812006-10-09 00:03:05 +01006 *
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com
9 *
10 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/sched.h>
16#include <linux/kernel_stat.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/msc01_ic.h>
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +090020#include <asm/traps.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22static unsigned long _icctrl_msc;
23#define MSC01_IC_REG_BASE _icctrl_msc
24
25#define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0)
26#define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0)
27
28static unsigned int irq_base;
29
30/* mask off an interrupt */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000031static inline void mask_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070032{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000033 unsigned int irq = d->irq;
34
Linus Torvalds1da177e2005-04-16 15:20:36 -070035 if (irq < (irq_base + 32))
36 MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
37 else
38 MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
39}
40
41/* unmask an interrupt */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000042static inline void unmask_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070043{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000044 unsigned int irq = d->irq;
45
Linus Torvalds1da177e2005-04-16 15:20:36 -070046 if (irq < (irq_base + 32))
47 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
48 else
49 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
50}
51
52/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070053 * Masks and ACKs an IRQ
54 */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000055static void level_mask_and_ack_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070056{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000057 unsigned int irq = d->irq;
58
59 mask_msc_irq(d);
Ralf Baechlee01402b2005-07-14 15:57:16 +000060 if (!cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 MSCIC_WRITE(MSC01_IC_EOI, 0);
Ralf Baechle41c594a2006-04-05 09:45:45 +010062 /* This actually needs to be a call into platform code */
Ralf Baechle1146fe32007-09-21 17:13:55 +010063 smtc_im_ack_irq(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070064}
65
66/*
67 * Masks and ACKs an IRQ
68 */
Thomas Gleixnere15883d2011-03-23 21:08:59 +000069static void edge_mask_and_ack_msc_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070070{
Thomas Gleixnere15883d2011-03-23 21:08:59 +000071 unsigned int irq = d->irq;
72
73 mask_msc_irq(d);
Ralf Baechlee01402b2005-07-14 15:57:16 +000074 if (!cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070075 MSCIC_WRITE(MSC01_IC_EOI, 0);
76 else {
77 u32 r;
78 MSCIC_READ(MSC01_IC_SUP+irq*8, r);
79 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
80 MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
81 }
Ralf Baechle1146fe32007-09-21 17:13:55 +010082 smtc_im_ack_irq(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070083}
84
85/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 * Interrupt handler for interrupts coming from SOC-it.
87 */
Ralf Baechle937a8012006-10-07 19:44:33 +010088void ll_msc_irq(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070089{
90 unsigned int irq;
91
92 /* read the interrupt vector register */
93 MSCIC_READ(MSC01_IC_VEC, irq);
94 if (irq < 64)
Ralf Baechle937a8012006-10-07 19:44:33 +010095 do_IRQ(irq + irq_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 else {
97 /* Ignore spurious interrupt */
98 }
99}
100
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +0900101static void msc_bind_eic_interrupt(int irq, int set)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102{
103 MSCIC_WRITE(MSC01_IC_RAMW,
104 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
105}
106
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +0900107static struct irq_chip msc_levelirq_type = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900108 .name = "SOC-it-Level",
Thomas Gleixnere15883d2011-03-23 21:08:59 +0000109 .irq_ack = level_mask_and_ack_msc_irq,
110 .irq_mask = mask_msc_irq,
111 .irq_mask_ack = level_mask_and_ack_msc_irq,
112 .irq_unmask = unmask_msc_irq,
113 .irq_eoi = unmask_msc_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114};
115
Atsushi Nemoto411ba7f2008-04-26 01:55:30 +0900116static struct irq_chip msc_edgeirq_type = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900117 .name = "SOC-it-Edge",
Thomas Gleixnere15883d2011-03-23 21:08:59 +0000118 .irq_ack = edge_mask_and_ack_msc_irq,
119 .irq_mask = mask_msc_irq,
120 .irq_mask_ack = edge_mask_and_ack_msc_irq,
121 .irq_unmask = unmask_msc_irq,
122 .irq_eoi = unmask_msc_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123};
124
125
Chris Dearmand725cf32007-05-08 14:05:39 +0100126void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127{
Ralf Baechle49a89ef2007-10-11 23:46:15 +0100128 _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129
130 /* Reset interrupt controller - initialises all registers to 0 */
131 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
132
133 board_bind_eic_interrupt = &msc_bind_eic_interrupt;
134
135 for (; nirq >= 0; nirq--, imp++) {
136 int n = imp->im_irq;
137
138 switch (imp->im_type) {
139 case MSC01_IRQ_EDGE:
Ralf Baechlec87e0902009-03-30 14:49:44 +0200140 set_irq_chip_and_handler_name(irqbase + n,
141 &msc_edgeirq_type, handle_edge_irq, "edge");
Ralf Baechlee01402b2005-07-14 15:57:16 +0000142 if (cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
144 else
145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
146 break;
147 case MSC01_IRQ_LEVEL:
Ralf Baechlec87e0902009-03-30 14:49:44 +0200148 set_irq_chip_and_handler_name(irqbase+n,
149 &msc_levelirq_type, handle_level_irq, "level");
Ralf Baechlee01402b2005-07-14 15:57:16 +0000150 if (cpu_has_veic)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
152 else
153 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
154 }
155 }
156
Chris Dearmand725cf32007-05-08 14:05:39 +0100157 irq_base = irqbase;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
159 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
160
161}