Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 1 | /* |
| 2 | * OmniVision OV9740 Camera Driver |
| 3 | * |
| 4 | * Copyright (C) 2011 NVIDIA Corporation |
| 5 | * |
| 6 | * Based on ov9640 camera driver. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/i2c.h> |
| 16 | #include <linux/slab.h> |
| 17 | #include <media/v4l2-chip-ident.h> |
| 18 | #include <media/soc_camera.h> |
| 19 | |
| 20 | #define to_ov9740(sd) container_of(sd, struct ov9740_priv, subdev) |
| 21 | |
| 22 | /* General Status Registers */ |
| 23 | #define OV9740_MODEL_ID_HI 0x0000 |
| 24 | #define OV9740_MODEL_ID_LO 0x0001 |
| 25 | #define OV9740_REVISION_NUMBER 0x0002 |
| 26 | #define OV9740_MANUFACTURER_ID 0x0003 |
| 27 | #define OV9740_SMIA_VERSION 0x0004 |
| 28 | |
| 29 | /* General Setup Registers */ |
| 30 | #define OV9740_MODE_SELECT 0x0100 |
| 31 | #define OV9740_IMAGE_ORT 0x0101 |
| 32 | #define OV9740_SOFTWARE_RESET 0x0103 |
| 33 | #define OV9740_GRP_PARAM_HOLD 0x0104 |
| 34 | #define OV9740_MSK_CORRUP_FM 0x0105 |
| 35 | |
| 36 | /* Timing Setting */ |
| 37 | #define OV9740_FRM_LENGTH_LN_HI 0x0340 /* VTS */ |
| 38 | #define OV9740_FRM_LENGTH_LN_LO 0x0341 /* VTS */ |
| 39 | #define OV9740_LN_LENGTH_PCK_HI 0x0342 /* HTS */ |
| 40 | #define OV9740_LN_LENGTH_PCK_LO 0x0343 /* HTS */ |
| 41 | #define OV9740_X_ADDR_START_HI 0x0344 |
| 42 | #define OV9740_X_ADDR_START_LO 0x0345 |
| 43 | #define OV9740_Y_ADDR_START_HI 0x0346 |
| 44 | #define OV9740_Y_ADDR_START_LO 0x0347 |
| 45 | #define OV9740_X_ADDR_END_HI 0x0348 |
| 46 | #define OV9740_X_ADDR_END_LO 0x0349 |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 47 | #define OV9740_Y_ADDR_END_HI 0x034a |
| 48 | #define OV9740_Y_ADDR_END_LO 0x034b |
| 49 | #define OV9740_X_OUTPUT_SIZE_HI 0x034c |
| 50 | #define OV9740_X_OUTPUT_SIZE_LO 0x034d |
| 51 | #define OV9740_Y_OUTPUT_SIZE_HI 0x034e |
| 52 | #define OV9740_Y_OUTPUT_SIZE_LO 0x034f |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 53 | |
| 54 | /* IO Control Registers */ |
| 55 | #define OV9740_IO_CREL00 0x3002 |
| 56 | #define OV9740_IO_CREL01 0x3004 |
| 57 | #define OV9740_IO_CREL02 0x3005 |
| 58 | #define OV9740_IO_OUTPUT_SEL01 0x3026 |
| 59 | #define OV9740_IO_OUTPUT_SEL02 0x3027 |
| 60 | |
| 61 | /* AWB Registers */ |
| 62 | #define OV9740_AWB_MANUAL_CTRL 0x3406 |
| 63 | |
| 64 | /* Analog Control Registers */ |
| 65 | #define OV9740_ANALOG_CTRL01 0x3601 |
| 66 | #define OV9740_ANALOG_CTRL02 0x3602 |
| 67 | #define OV9740_ANALOG_CTRL03 0x3603 |
| 68 | #define OV9740_ANALOG_CTRL04 0x3604 |
| 69 | #define OV9740_ANALOG_CTRL10 0x3610 |
| 70 | #define OV9740_ANALOG_CTRL12 0x3612 |
Andrew Chew | c4fdce5 | 2011-06-23 20:19:41 -0300 | [diff] [blame] | 71 | #define OV9740_ANALOG_CTRL15 0x3615 |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 72 | #define OV9740_ANALOG_CTRL20 0x3620 |
| 73 | #define OV9740_ANALOG_CTRL21 0x3621 |
| 74 | #define OV9740_ANALOG_CTRL22 0x3622 |
| 75 | #define OV9740_ANALOG_CTRL30 0x3630 |
| 76 | #define OV9740_ANALOG_CTRL31 0x3631 |
| 77 | #define OV9740_ANALOG_CTRL32 0x3632 |
| 78 | #define OV9740_ANALOG_CTRL33 0x3633 |
| 79 | |
| 80 | /* Sensor Control */ |
| 81 | #define OV9740_SENSOR_CTRL03 0x3703 |
| 82 | #define OV9740_SENSOR_CTRL04 0x3704 |
| 83 | #define OV9740_SENSOR_CTRL05 0x3705 |
| 84 | #define OV9740_SENSOR_CTRL07 0x3707 |
| 85 | |
| 86 | /* Timing Control */ |
| 87 | #define OV9740_TIMING_CTRL17 0x3817 |
| 88 | #define OV9740_TIMING_CTRL19 0x3819 |
| 89 | #define OV9740_TIMING_CTRL33 0x3833 |
| 90 | #define OV9740_TIMING_CTRL35 0x3835 |
| 91 | |
| 92 | /* Banding Filter */ |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 93 | #define OV9740_AEC_MAXEXPO_60_H 0x3a02 |
| 94 | #define OV9740_AEC_MAXEXPO_60_L 0x3a03 |
| 95 | #define OV9740_AEC_B50_STEP_HI 0x3a08 |
| 96 | #define OV9740_AEC_B50_STEP_LO 0x3a09 |
| 97 | #define OV9740_AEC_B60_STEP_HI 0x3a0a |
| 98 | #define OV9740_AEC_B60_STEP_LO 0x3a0b |
| 99 | #define OV9740_AEC_CTRL0D 0x3a0d |
| 100 | #define OV9740_AEC_CTRL0E 0x3a0e |
| 101 | #define OV9740_AEC_MAXEXPO_50_H 0x3a14 |
| 102 | #define OV9740_AEC_MAXEXPO_50_L 0x3a15 |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 103 | |
| 104 | /* AEC/AGC Control */ |
| 105 | #define OV9740_AEC_ENABLE 0x3503 |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 106 | #define OV9740_GAIN_CEILING_01 0x3a18 |
| 107 | #define OV9740_GAIN_CEILING_02 0x3a19 |
| 108 | #define OV9740_AEC_HI_THRESHOLD 0x3a11 |
| 109 | #define OV9740_AEC_3A1A 0x3a1a |
| 110 | #define OV9740_AEC_CTRL1B_WPT2 0x3a1b |
| 111 | #define OV9740_AEC_CTRL0F_WPT 0x3a0f |
| 112 | #define OV9740_AEC_CTRL10_BPT 0x3a10 |
| 113 | #define OV9740_AEC_CTRL1E_BPT2 0x3a1e |
| 114 | #define OV9740_AEC_LO_THRESHOLD 0x3a1f |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 115 | |
| 116 | /* BLC Control */ |
| 117 | #define OV9740_BLC_AUTO_ENABLE 0x4002 |
| 118 | #define OV9740_BLC_MODE 0x4005 |
| 119 | |
| 120 | /* VFIFO */ |
| 121 | #define OV9740_VFIFO_READ_START_HI 0x4608 |
| 122 | #define OV9740_VFIFO_READ_START_LO 0x4609 |
| 123 | |
| 124 | /* DVP Control */ |
| 125 | #define OV9740_DVP_VSYNC_CTRL02 0x4702 |
| 126 | #define OV9740_DVP_VSYNC_MODE 0x4704 |
| 127 | #define OV9740_DVP_VSYNC_CTRL06 0x4706 |
| 128 | |
| 129 | /* PLL Setting */ |
| 130 | #define OV9740_PLL_MODE_CTRL01 0x3104 |
| 131 | #define OV9740_PRE_PLL_CLK_DIV 0x0305 |
| 132 | #define OV9740_PLL_MULTIPLIER 0x0307 |
| 133 | #define OV9740_VT_SYS_CLK_DIV 0x0303 |
| 134 | #define OV9740_VT_PIX_CLK_DIV 0x0301 |
| 135 | #define OV9740_PLL_CTRL3010 0x3010 |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 136 | #define OV9740_VFIFO_CTRL00 0x460e |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 137 | |
| 138 | /* ISP Control */ |
| 139 | #define OV9740_ISP_CTRL00 0x5000 |
| 140 | #define OV9740_ISP_CTRL01 0x5001 |
| 141 | #define OV9740_ISP_CTRL03 0x5003 |
| 142 | #define OV9740_ISP_CTRL05 0x5005 |
| 143 | #define OV9740_ISP_CTRL12 0x5012 |
| 144 | #define OV9740_ISP_CTRL19 0x5019 |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 145 | #define OV9740_ISP_CTRL1A 0x501a |
| 146 | #define OV9740_ISP_CTRL1E 0x501e |
| 147 | #define OV9740_ISP_CTRL1F 0x501f |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 148 | #define OV9740_ISP_CTRL20 0x5020 |
| 149 | #define OV9740_ISP_CTRL21 0x5021 |
| 150 | |
| 151 | /* AWB */ |
| 152 | #define OV9740_AWB_CTRL00 0x5180 |
| 153 | #define OV9740_AWB_CTRL01 0x5181 |
| 154 | #define OV9740_AWB_CTRL02 0x5182 |
| 155 | #define OV9740_AWB_CTRL03 0x5183 |
| 156 | #define OV9740_AWB_ADV_CTRL01 0x5184 |
| 157 | #define OV9740_AWB_ADV_CTRL02 0x5185 |
| 158 | #define OV9740_AWB_ADV_CTRL03 0x5186 |
| 159 | #define OV9740_AWB_ADV_CTRL04 0x5187 |
| 160 | #define OV9740_AWB_ADV_CTRL05 0x5188 |
| 161 | #define OV9740_AWB_ADV_CTRL06 0x5189 |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 162 | #define OV9740_AWB_ADV_CTRL07 0x518a |
| 163 | #define OV9740_AWB_ADV_CTRL08 0x518b |
| 164 | #define OV9740_AWB_ADV_CTRL09 0x518c |
| 165 | #define OV9740_AWB_ADV_CTRL10 0x518d |
| 166 | #define OV9740_AWB_ADV_CTRL11 0x518e |
| 167 | #define OV9740_AWB_CTRL0F 0x518f |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 168 | #define OV9740_AWB_CTRL10 0x5190 |
| 169 | #define OV9740_AWB_CTRL11 0x5191 |
| 170 | #define OV9740_AWB_CTRL12 0x5192 |
| 171 | #define OV9740_AWB_CTRL13 0x5193 |
| 172 | #define OV9740_AWB_CTRL14 0x5194 |
| 173 | |
| 174 | /* MIPI Control */ |
| 175 | #define OV9740_MIPI_CTRL00 0x4800 |
| 176 | #define OV9740_MIPI_3837 0x3837 |
| 177 | #define OV9740_MIPI_CTRL01 0x4801 |
| 178 | #define OV9740_MIPI_CTRL03 0x4803 |
| 179 | #define OV9740_MIPI_CTRL05 0x4805 |
| 180 | #define OV9740_VFIFO_RD_CTRL 0x4601 |
| 181 | #define OV9740_MIPI_CTRL_3012 0x3012 |
| 182 | #define OV9740_SC_CMMM_MIPI_CTR 0x3014 |
| 183 | |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 184 | #define OV9740_MAX_WIDTH 1280 |
| 185 | #define OV9740_MAX_HEIGHT 720 |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 186 | |
| 187 | /* Misc. structures */ |
| 188 | struct ov9740_reg { |
| 189 | u16 reg; |
| 190 | u8 val; |
| 191 | }; |
| 192 | |
| 193 | struct ov9740_priv { |
| 194 | struct v4l2_subdev subdev; |
| 195 | |
| 196 | int ident; |
| 197 | u16 model; |
| 198 | u8 revision; |
| 199 | u8 manid; |
| 200 | u8 smiaver; |
| 201 | |
| 202 | bool flag_vflip; |
| 203 | bool flag_hflip; |
| 204 | }; |
| 205 | |
| 206 | static const struct ov9740_reg ov9740_defaults[] = { |
Andrew Chew | c4fdce5 | 2011-06-23 20:19:41 -0300 | [diff] [blame] | 207 | /* Software Reset */ |
| 208 | { OV9740_SOFTWARE_RESET, 0x01 }, |
| 209 | |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 210 | /* Banding Filter */ |
| 211 | { OV9740_AEC_B50_STEP_HI, 0x00 }, |
| 212 | { OV9740_AEC_B50_STEP_LO, 0xe8 }, |
| 213 | { OV9740_AEC_CTRL0E, 0x03 }, |
| 214 | { OV9740_AEC_MAXEXPO_50_H, 0x15 }, |
| 215 | { OV9740_AEC_MAXEXPO_50_L, 0xc6 }, |
| 216 | { OV9740_AEC_B60_STEP_HI, 0x00 }, |
| 217 | { OV9740_AEC_B60_STEP_LO, 0xc0 }, |
| 218 | { OV9740_AEC_CTRL0D, 0x04 }, |
| 219 | { OV9740_AEC_MAXEXPO_60_H, 0x18 }, |
| 220 | { OV9740_AEC_MAXEXPO_60_L, 0x20 }, |
| 221 | |
| 222 | /* LC */ |
| 223 | { 0x5842, 0x02 }, { 0x5843, 0x5e }, { 0x5844, 0x04 }, { 0x5845, 0x32 }, |
| 224 | { 0x5846, 0x03 }, { 0x5847, 0x29 }, { 0x5848, 0x02 }, { 0x5849, 0xcc }, |
| 225 | |
| 226 | /* Un-documented OV9740 registers */ |
| 227 | { 0x5800, 0x29 }, { 0x5801, 0x25 }, { 0x5802, 0x20 }, { 0x5803, 0x21 }, |
| 228 | { 0x5804, 0x26 }, { 0x5805, 0x2e }, { 0x5806, 0x11 }, { 0x5807, 0x0c }, |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 229 | { 0x5808, 0x09 }, { 0x5809, 0x0a }, { 0x580a, 0x0e }, { 0x580b, 0x16 }, |
| 230 | { 0x580c, 0x06 }, { 0x580d, 0x02 }, { 0x580e, 0x00 }, { 0x580f, 0x00 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 231 | { 0x5810, 0x04 }, { 0x5811, 0x0a }, { 0x5812, 0x05 }, { 0x5813, 0x02 }, |
| 232 | { 0x5814, 0x00 }, { 0x5815, 0x00 }, { 0x5816, 0x03 }, { 0x5817, 0x09 }, |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 233 | { 0x5818, 0x0f }, { 0x5819, 0x0a }, { 0x581a, 0x07 }, { 0x581b, 0x08 }, |
| 234 | { 0x581c, 0x0b }, { 0x581d, 0x14 }, { 0x581e, 0x28 }, { 0x581f, 0x23 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 235 | { 0x5820, 0x1d }, { 0x5821, 0x1e }, { 0x5822, 0x24 }, { 0x5823, 0x2a }, |
| 236 | { 0x5824, 0x4f }, { 0x5825, 0x6f }, { 0x5826, 0x5f }, { 0x5827, 0x7f }, |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 237 | { 0x5828, 0x9f }, { 0x5829, 0x5f }, { 0x582a, 0x8f }, { 0x582b, 0x9e }, |
| 238 | { 0x582c, 0x8f }, { 0x582d, 0x9f }, { 0x582e, 0x4f }, { 0x582f, 0x87 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 239 | { 0x5830, 0x86 }, { 0x5831, 0x97 }, { 0x5832, 0xae }, { 0x5833, 0x3f }, |
| 240 | { 0x5834, 0x8e }, { 0x5835, 0x7c }, { 0x5836, 0x7e }, { 0x5837, 0xaf }, |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 241 | { 0x5838, 0x8f }, { 0x5839, 0x8f }, { 0x583a, 0x9f }, { 0x583b, 0x7f }, |
| 242 | { 0x583c, 0x5f }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 243 | |
| 244 | /* Y Gamma */ |
| 245 | { 0x5480, 0x07 }, { 0x5481, 0x18 }, { 0x5482, 0x2c }, { 0x5483, 0x4e }, |
| 246 | { 0x5484, 0x5e }, { 0x5485, 0x6b }, { 0x5486, 0x77 }, { 0x5487, 0x82 }, |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 247 | { 0x5488, 0x8c }, { 0x5489, 0x95 }, { 0x548a, 0xa4 }, { 0x548b, 0xb1 }, |
| 248 | { 0x548c, 0xc6 }, { 0x548d, 0xd8 }, { 0x548e, 0xe9 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 249 | |
| 250 | /* UV Gamma */ |
| 251 | { 0x5490, 0x0f }, { 0x5491, 0xff }, { 0x5492, 0x0d }, { 0x5493, 0x05 }, |
| 252 | { 0x5494, 0x07 }, { 0x5495, 0x1a }, { 0x5496, 0x04 }, { 0x5497, 0x01 }, |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 253 | { 0x5498, 0x03 }, { 0x5499, 0x53 }, { 0x549a, 0x02 }, { 0x549b, 0xeb }, |
| 254 | { 0x549c, 0x02 }, { 0x549d, 0xa0 }, { 0x549e, 0x02 }, { 0x549f, 0x67 }, |
| 255 | { 0x54a0, 0x02 }, { 0x54a1, 0x3b }, { 0x54a2, 0x02 }, { 0x54a3, 0x18 }, |
| 256 | { 0x54a4, 0x01 }, { 0x54a5, 0xe7 }, { 0x54a6, 0x01 }, { 0x54a7, 0xc3 }, |
| 257 | { 0x54a8, 0x01 }, { 0x54a9, 0x94 }, { 0x54aa, 0x01 }, { 0x54ab, 0x72 }, |
| 258 | { 0x54ac, 0x01 }, { 0x54ad, 0x57 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 259 | |
| 260 | /* AWB */ |
| 261 | { OV9740_AWB_CTRL00, 0xf0 }, |
| 262 | { OV9740_AWB_CTRL01, 0x00 }, |
| 263 | { OV9740_AWB_CTRL02, 0x41 }, |
| 264 | { OV9740_AWB_CTRL03, 0x42 }, |
| 265 | { OV9740_AWB_ADV_CTRL01, 0x8a }, |
| 266 | { OV9740_AWB_ADV_CTRL02, 0x61 }, |
| 267 | { OV9740_AWB_ADV_CTRL03, 0xce }, |
| 268 | { OV9740_AWB_ADV_CTRL04, 0xa8 }, |
| 269 | { OV9740_AWB_ADV_CTRL05, 0x17 }, |
| 270 | { OV9740_AWB_ADV_CTRL06, 0x1f }, |
| 271 | { OV9740_AWB_ADV_CTRL07, 0x27 }, |
| 272 | { OV9740_AWB_ADV_CTRL08, 0x41 }, |
| 273 | { OV9740_AWB_ADV_CTRL09, 0x34 }, |
| 274 | { OV9740_AWB_ADV_CTRL10, 0xf0 }, |
| 275 | { OV9740_AWB_ADV_CTRL11, 0x10 }, |
| 276 | { OV9740_AWB_CTRL0F, 0xff }, |
| 277 | { OV9740_AWB_CTRL10, 0x00 }, |
| 278 | { OV9740_AWB_CTRL11, 0xff }, |
| 279 | { OV9740_AWB_CTRL12, 0x00 }, |
| 280 | { OV9740_AWB_CTRL13, 0xff }, |
| 281 | { OV9740_AWB_CTRL14, 0x00 }, |
| 282 | |
| 283 | /* CIP */ |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 284 | { 0x530d, 0x12 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 285 | |
| 286 | /* CMX */ |
| 287 | { 0x5380, 0x01 }, { 0x5381, 0x00 }, { 0x5382, 0x00 }, { 0x5383, 0x17 }, |
| 288 | { 0x5384, 0x00 }, { 0x5385, 0x01 }, { 0x5386, 0x00 }, { 0x5387, 0x00 }, |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 289 | { 0x5388, 0x00 }, { 0x5389, 0xe0 }, { 0x538a, 0x00 }, { 0x538b, 0x20 }, |
| 290 | { 0x538c, 0x00 }, { 0x538d, 0x00 }, { 0x538e, 0x00 }, { 0x538f, 0x16 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 291 | { 0x5390, 0x00 }, { 0x5391, 0x9c }, { 0x5392, 0x00 }, { 0x5393, 0xa0 }, |
| 292 | { 0x5394, 0x18 }, |
| 293 | |
| 294 | /* 50/60 Detection */ |
Andrew Chew | c6aac9f | 2011-06-23 20:19:39 -0300 | [diff] [blame] | 295 | { 0x3c0a, 0x9c }, { 0x3c0b, 0x3f }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 296 | |
| 297 | /* Output Select */ |
| 298 | { OV9740_IO_OUTPUT_SEL01, 0x00 }, |
| 299 | { OV9740_IO_OUTPUT_SEL02, 0x00 }, |
| 300 | { OV9740_IO_CREL00, 0x00 }, |
| 301 | { OV9740_IO_CREL01, 0x00 }, |
| 302 | { OV9740_IO_CREL02, 0x00 }, |
| 303 | |
| 304 | /* AWB Control */ |
| 305 | { OV9740_AWB_MANUAL_CTRL, 0x00 }, |
| 306 | |
| 307 | /* Analog Control */ |
| 308 | { OV9740_ANALOG_CTRL03, 0xaa }, |
| 309 | { OV9740_ANALOG_CTRL32, 0x2f }, |
| 310 | { OV9740_ANALOG_CTRL20, 0x66 }, |
| 311 | { OV9740_ANALOG_CTRL21, 0xc0 }, |
| 312 | { OV9740_ANALOG_CTRL31, 0x52 }, |
| 313 | { OV9740_ANALOG_CTRL33, 0x50 }, |
| 314 | { OV9740_ANALOG_CTRL30, 0xca }, |
| 315 | { OV9740_ANALOG_CTRL04, 0x0c }, |
| 316 | { OV9740_ANALOG_CTRL01, 0x40 }, |
| 317 | { OV9740_ANALOG_CTRL02, 0x16 }, |
| 318 | { OV9740_ANALOG_CTRL10, 0xa1 }, |
| 319 | { OV9740_ANALOG_CTRL12, 0x24 }, |
| 320 | { OV9740_ANALOG_CTRL22, 0x9f }, |
Andrew Chew | c4fdce5 | 2011-06-23 20:19:41 -0300 | [diff] [blame] | 321 | { OV9740_ANALOG_CTRL15, 0xf0 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 322 | |
| 323 | /* Sensor Control */ |
| 324 | { OV9740_SENSOR_CTRL03, 0x42 }, |
| 325 | { OV9740_SENSOR_CTRL04, 0x10 }, |
| 326 | { OV9740_SENSOR_CTRL05, 0x45 }, |
| 327 | { OV9740_SENSOR_CTRL07, 0x14 }, |
| 328 | |
| 329 | /* Timing Control */ |
| 330 | { OV9740_TIMING_CTRL33, 0x04 }, |
| 331 | { OV9740_TIMING_CTRL35, 0x02 }, |
| 332 | { OV9740_TIMING_CTRL19, 0x6e }, |
| 333 | { OV9740_TIMING_CTRL17, 0x94 }, |
| 334 | |
| 335 | /* AEC/AGC Control */ |
| 336 | { OV9740_AEC_ENABLE, 0x10 }, |
| 337 | { OV9740_GAIN_CEILING_01, 0x00 }, |
| 338 | { OV9740_GAIN_CEILING_02, 0x7f }, |
| 339 | { OV9740_AEC_HI_THRESHOLD, 0xa0 }, |
| 340 | { OV9740_AEC_3A1A, 0x05 }, |
| 341 | { OV9740_AEC_CTRL1B_WPT2, 0x50 }, |
| 342 | { OV9740_AEC_CTRL0F_WPT, 0x50 }, |
| 343 | { OV9740_AEC_CTRL10_BPT, 0x4c }, |
| 344 | { OV9740_AEC_CTRL1E_BPT2, 0x4c }, |
| 345 | { OV9740_AEC_LO_THRESHOLD, 0x26 }, |
| 346 | |
| 347 | /* BLC Control */ |
| 348 | { OV9740_BLC_AUTO_ENABLE, 0x45 }, |
| 349 | { OV9740_BLC_MODE, 0x18 }, |
| 350 | |
| 351 | /* DVP Control */ |
| 352 | { OV9740_DVP_VSYNC_CTRL02, 0x04 }, |
| 353 | { OV9740_DVP_VSYNC_MODE, 0x00 }, |
| 354 | { OV9740_DVP_VSYNC_CTRL06, 0x08 }, |
| 355 | |
| 356 | /* PLL Setting */ |
| 357 | { OV9740_PLL_MODE_CTRL01, 0x20 }, |
| 358 | { OV9740_PRE_PLL_CLK_DIV, 0x03 }, |
| 359 | { OV9740_PLL_MULTIPLIER, 0x4c }, |
| 360 | { OV9740_VT_SYS_CLK_DIV, 0x01 }, |
| 361 | { OV9740_VT_PIX_CLK_DIV, 0x08 }, |
| 362 | { OV9740_PLL_CTRL3010, 0x01 }, |
| 363 | { OV9740_VFIFO_CTRL00, 0x82 }, |
| 364 | |
| 365 | /* Timing Setting */ |
| 366 | /* VTS */ |
| 367 | { OV9740_FRM_LENGTH_LN_HI, 0x03 }, |
| 368 | { OV9740_FRM_LENGTH_LN_LO, 0x07 }, |
| 369 | /* HTS */ |
| 370 | { OV9740_LN_LENGTH_PCK_HI, 0x06 }, |
| 371 | { OV9740_LN_LENGTH_PCK_LO, 0x62 }, |
| 372 | |
| 373 | /* MIPI Control */ |
Andrew Chew | c4fdce5 | 2011-06-23 20:19:41 -0300 | [diff] [blame] | 374 | { OV9740_MIPI_CTRL00, 0x44 }, /* 0x64 for discontinuous clk */ |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 375 | { OV9740_MIPI_3837, 0x01 }, |
| 376 | { OV9740_MIPI_CTRL01, 0x0f }, |
| 377 | { OV9740_MIPI_CTRL03, 0x05 }, |
| 378 | { OV9740_MIPI_CTRL05, 0x10 }, |
| 379 | { OV9740_VFIFO_RD_CTRL, 0x16 }, |
| 380 | { OV9740_MIPI_CTRL_3012, 0x70 }, |
| 381 | { OV9740_SC_CMMM_MIPI_CTR, 0x01 }, |
Andrew Chew | c4fdce5 | 2011-06-23 20:19:41 -0300 | [diff] [blame] | 382 | |
| 383 | /* YUYV order */ |
| 384 | { OV9740_ISP_CTRL19, 0x02 }, |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 385 | }; |
| 386 | |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 387 | static enum v4l2_mbus_pixelcode ov9740_codes[] = { |
| 388 | V4L2_MBUS_FMT_YUYV8_2X8, |
| 389 | }; |
| 390 | |
| 391 | static const struct v4l2_queryctrl ov9740_controls[] = { |
| 392 | { |
| 393 | .id = V4L2_CID_VFLIP, |
| 394 | .type = V4L2_CTRL_TYPE_BOOLEAN, |
| 395 | .name = "Flip Vertically", |
| 396 | .minimum = 0, |
| 397 | .maximum = 1, |
| 398 | .step = 1, |
| 399 | .default_value = 0, |
| 400 | }, |
| 401 | { |
| 402 | .id = V4L2_CID_HFLIP, |
| 403 | .type = V4L2_CTRL_TYPE_BOOLEAN, |
| 404 | .name = "Flip Horizontally", |
| 405 | .minimum = 0, |
| 406 | .maximum = 1, |
| 407 | .step = 1, |
| 408 | .default_value = 0, |
| 409 | }, |
| 410 | }; |
| 411 | |
| 412 | /* read a register */ |
| 413 | static int ov9740_reg_read(struct i2c_client *client, u16 reg, u8 *val) |
| 414 | { |
| 415 | int ret; |
| 416 | struct i2c_msg msg[] = { |
| 417 | { |
| 418 | .addr = client->addr, |
| 419 | .flags = 0, |
| 420 | .len = 2, |
| 421 | .buf = (u8 *)®, |
| 422 | }, |
| 423 | { |
| 424 | .addr = client->addr, |
| 425 | .flags = I2C_M_RD, |
| 426 | .len = 1, |
| 427 | .buf = val, |
| 428 | }, |
| 429 | }; |
| 430 | |
| 431 | reg = swab16(reg); |
| 432 | |
| 433 | ret = i2c_transfer(client->adapter, msg, 2); |
| 434 | if (ret < 0) { |
| 435 | dev_err(&client->dev, "Failed reading register 0x%04x!\n", reg); |
| 436 | return ret; |
| 437 | } |
| 438 | |
| 439 | return 0; |
| 440 | } |
| 441 | |
| 442 | /* write a register */ |
| 443 | static int ov9740_reg_write(struct i2c_client *client, u16 reg, u8 val) |
| 444 | { |
| 445 | struct i2c_msg msg; |
| 446 | struct { |
| 447 | u16 reg; |
| 448 | u8 val; |
| 449 | } __packed buf; |
| 450 | int ret; |
| 451 | |
| 452 | reg = swab16(reg); |
| 453 | |
| 454 | buf.reg = reg; |
| 455 | buf.val = val; |
| 456 | |
| 457 | msg.addr = client->addr; |
| 458 | msg.flags = 0; |
| 459 | msg.len = 3; |
| 460 | msg.buf = (u8 *)&buf; |
| 461 | |
| 462 | ret = i2c_transfer(client->adapter, &msg, 1); |
| 463 | if (ret < 0) { |
| 464 | dev_err(&client->dev, "Failed writing register 0x%04x!\n", reg); |
| 465 | return ret; |
| 466 | } |
| 467 | |
| 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | |
| 472 | /* Read a register, alter its bits, write it back */ |
| 473 | static int ov9740_reg_rmw(struct i2c_client *client, u16 reg, u8 set, u8 unset) |
| 474 | { |
| 475 | u8 val; |
| 476 | int ret; |
| 477 | |
| 478 | ret = ov9740_reg_read(client, reg, &val); |
| 479 | if (ret < 0) { |
| 480 | dev_err(&client->dev, |
Andrew Chew | 5fec8b9 | 2011-06-23 20:19:40 -0300 | [diff] [blame] | 481 | "[Read]-Modify-Write of register 0x%04x failed!\n", |
| 482 | reg); |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 483 | return ret; |
| 484 | } |
| 485 | |
| 486 | val |= set; |
| 487 | val &= ~unset; |
| 488 | |
| 489 | ret = ov9740_reg_write(client, reg, val); |
| 490 | if (ret < 0) { |
| 491 | dev_err(&client->dev, |
Andrew Chew | 5fec8b9 | 2011-06-23 20:19:40 -0300 | [diff] [blame] | 492 | "Read-Modify-[Write] of register 0x%04x failed!\n", |
| 493 | reg); |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 494 | return ret; |
| 495 | } |
| 496 | |
| 497 | return 0; |
| 498 | } |
| 499 | |
| 500 | static int ov9740_reg_write_array(struct i2c_client *client, |
| 501 | const struct ov9740_reg *regarray, |
| 502 | int regarraylen) |
| 503 | { |
| 504 | int i; |
| 505 | int ret; |
| 506 | |
| 507 | for (i = 0; i < regarraylen; i++) { |
| 508 | ret = ov9740_reg_write(client, |
| 509 | regarray[i].reg, regarray[i].val); |
| 510 | if (ret < 0) |
| 511 | return ret; |
| 512 | } |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
| 517 | /* Start/Stop streaming from the device */ |
| 518 | static int ov9740_s_stream(struct v4l2_subdev *sd, int enable) |
| 519 | { |
| 520 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 521 | struct ov9740_priv *priv = to_ov9740(sd); |
| 522 | int ret; |
| 523 | |
| 524 | /* Program orientation register. */ |
| 525 | if (priv->flag_vflip) |
| 526 | ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x2, 0); |
| 527 | else |
| 528 | ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x2); |
| 529 | if (ret < 0) |
| 530 | return ret; |
| 531 | |
| 532 | if (priv->flag_hflip) |
| 533 | ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x1, 0); |
| 534 | else |
| 535 | ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x1); |
| 536 | if (ret < 0) |
| 537 | return ret; |
| 538 | |
| 539 | if (enable) { |
| 540 | dev_dbg(&client->dev, "Enabling Streaming\n"); |
| 541 | /* Start Streaming */ |
| 542 | ret = ov9740_reg_write(client, OV9740_MODE_SELECT, 0x01); |
| 543 | |
| 544 | } else { |
| 545 | dev_dbg(&client->dev, "Disabling Streaming\n"); |
| 546 | /* Software Reset */ |
| 547 | ret = ov9740_reg_write(client, OV9740_SOFTWARE_RESET, 0x01); |
| 548 | if (!ret) |
| 549 | /* Setting Streaming to Standby */ |
| 550 | ret = ov9740_reg_write(client, OV9740_MODE_SELECT, |
| 551 | 0x00); |
| 552 | } |
| 553 | |
| 554 | return ret; |
| 555 | } |
| 556 | |
| 557 | /* Alter bus settings on camera side */ |
| 558 | static int ov9740_set_bus_param(struct soc_camera_device *icd, |
| 559 | unsigned long flags) |
| 560 | { |
| 561 | return 0; |
| 562 | } |
| 563 | |
| 564 | /* Request bus settings on camera side */ |
| 565 | static unsigned long ov9740_query_bus_param(struct soc_camera_device *icd) |
| 566 | { |
| 567 | struct soc_camera_link *icl = to_soc_camera_link(icd); |
| 568 | |
| 569 | unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER | |
| 570 | SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH | |
| 571 | SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATAWIDTH_8; |
| 572 | |
| 573 | return soc_camera_apply_sensor_flags(icl, flags); |
| 574 | } |
| 575 | |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 576 | /* select nearest higher resolution for capture */ |
| 577 | static void ov9740_res_roundup(u32 *width, u32 *height) |
| 578 | { |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 579 | /* Width must be a multiple of 4 pixels. */ |
| 580 | *width = ALIGN(*width, 4); |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 581 | |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 582 | /* Max resolution is 1280x720 (720p). */ |
| 583 | if (*width > OV9740_MAX_WIDTH) |
| 584 | *width = OV9740_MAX_WIDTH; |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 585 | |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 586 | if (*height > OV9740_MAX_HEIGHT) |
| 587 | *height = OV9740_MAX_HEIGHT; |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 588 | } |
| 589 | |
| 590 | /* Setup registers according to resolution and color encoding */ |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 591 | static int ov9740_set_res(struct i2c_client *client, u32 width, u32 height) |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 592 | { |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 593 | u32 x_start; |
| 594 | u32 y_start; |
| 595 | u32 x_end; |
| 596 | u32 y_end; |
| 597 | bool scaling = 0; |
| 598 | u32 scale_input_x; |
| 599 | u32 scale_input_y; |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 600 | int ret; |
| 601 | |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 602 | if ((width != OV9740_MAX_WIDTH) || (height != OV9740_MAX_HEIGHT)) |
| 603 | scaling = 1; |
| 604 | |
| 605 | /* |
| 606 | * Try to use as much of the sensor area as possible when supporting |
| 607 | * smaller resolutions. Depending on the aspect ratio of the |
| 608 | * chosen resolution, we can either use the full width of the sensor, |
| 609 | * or the full height of the sensor (or both if the aspect ratio is |
| 610 | * the same as 1280x720. |
| 611 | */ |
| 612 | if ((OV9740_MAX_WIDTH * height) > (OV9740_MAX_HEIGHT * width)) { |
| 613 | scale_input_x = (OV9740_MAX_HEIGHT * width) / height; |
| 614 | scale_input_y = OV9740_MAX_HEIGHT; |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 615 | } else { |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 616 | scale_input_x = OV9740_MAX_WIDTH; |
| 617 | scale_input_y = (OV9740_MAX_WIDTH * height) / width; |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 618 | } |
| 619 | |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 620 | /* These describe the area of the sensor to use. */ |
| 621 | x_start = (OV9740_MAX_WIDTH - scale_input_x) / 2; |
| 622 | y_start = (OV9740_MAX_HEIGHT - scale_input_y) / 2; |
| 623 | x_end = x_start + scale_input_x - 1; |
| 624 | y_end = y_start + scale_input_y - 1; |
| 625 | |
| 626 | ret = ov9740_reg_write(client, OV9740_X_ADDR_START_HI, x_start >> 8); |
| 627 | if (ret) |
| 628 | goto done; |
| 629 | ret = ov9740_reg_write(client, OV9740_X_ADDR_START_LO, x_start & 0xff); |
| 630 | if (ret) |
| 631 | goto done; |
| 632 | ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_HI, y_start >> 8); |
| 633 | if (ret) |
| 634 | goto done; |
| 635 | ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_LO, y_start & 0xff); |
| 636 | if (ret) |
| 637 | goto done; |
| 638 | |
| 639 | ret = ov9740_reg_write(client, OV9740_X_ADDR_END_HI, x_end >> 8); |
| 640 | if (ret) |
| 641 | goto done; |
| 642 | ret = ov9740_reg_write(client, OV9740_X_ADDR_END_LO, x_end & 0xff); |
| 643 | if (ret) |
| 644 | goto done; |
| 645 | ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_HI, y_end >> 8); |
| 646 | if (ret) |
| 647 | goto done; |
| 648 | ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_LO, y_end & 0xff); |
| 649 | if (ret) |
| 650 | goto done; |
| 651 | |
| 652 | ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_HI, width >> 8); |
| 653 | if (ret) |
| 654 | goto done; |
| 655 | ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_LO, width & 0xff); |
| 656 | if (ret) |
| 657 | goto done; |
| 658 | ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_HI, height >> 8); |
| 659 | if (ret) |
| 660 | goto done; |
| 661 | ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_LO, height & 0xff); |
| 662 | if (ret) |
| 663 | goto done; |
| 664 | |
| 665 | ret = ov9740_reg_write(client, OV9740_ISP_CTRL1E, scale_input_x >> 8); |
| 666 | if (ret) |
| 667 | goto done; |
| 668 | ret = ov9740_reg_write(client, OV9740_ISP_CTRL1F, scale_input_x & 0xff); |
| 669 | if (ret) |
| 670 | goto done; |
| 671 | ret = ov9740_reg_write(client, OV9740_ISP_CTRL20, scale_input_y >> 8); |
| 672 | if (ret) |
| 673 | goto done; |
| 674 | ret = ov9740_reg_write(client, OV9740_ISP_CTRL21, scale_input_y & 0xff); |
| 675 | if (ret) |
| 676 | goto done; |
| 677 | |
| 678 | ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_HI, |
| 679 | (scale_input_x - width) >> 8); |
| 680 | if (ret) |
| 681 | goto done; |
| 682 | ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_LO, |
| 683 | (scale_input_x - width) & 0xff); |
| 684 | if (ret) |
| 685 | goto done; |
| 686 | |
| 687 | ret = ov9740_reg_write(client, OV9740_ISP_CTRL00, 0xff); |
| 688 | if (ret) |
| 689 | goto done; |
| 690 | ret = ov9740_reg_write(client, OV9740_ISP_CTRL01, 0xef | |
| 691 | (scaling << 4)); |
| 692 | if (ret) |
| 693 | goto done; |
| 694 | ret = ov9740_reg_write(client, OV9740_ISP_CTRL03, 0xff); |
| 695 | |
| 696 | done: |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 697 | return ret; |
| 698 | } |
| 699 | |
| 700 | /* set the format we will capture in */ |
| 701 | static int ov9740_s_fmt(struct v4l2_subdev *sd, |
| 702 | struct v4l2_mbus_framefmt *mf) |
| 703 | { |
| 704 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 705 | enum v4l2_colorspace cspace; |
| 706 | enum v4l2_mbus_pixelcode code = mf->code; |
| 707 | int ret; |
| 708 | |
| 709 | ov9740_res_roundup(&mf->width, &mf->height); |
| 710 | |
| 711 | switch (code) { |
| 712 | case V4L2_MBUS_FMT_YUYV8_2X8: |
| 713 | cspace = V4L2_COLORSPACE_SRGB; |
| 714 | break; |
| 715 | default: |
| 716 | return -EINVAL; |
| 717 | } |
| 718 | |
| 719 | ret = ov9740_reg_write_array(client, ov9740_defaults, |
| 720 | ARRAY_SIZE(ov9740_defaults)); |
| 721 | if (ret < 0) |
| 722 | return ret; |
| 723 | |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 724 | ret = ov9740_set_res(client, mf->width, mf->height); |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 725 | if (ret < 0) |
| 726 | return ret; |
| 727 | |
| 728 | mf->code = code; |
| 729 | mf->colorspace = cspace; |
| 730 | |
| 731 | return ret; |
| 732 | } |
| 733 | |
| 734 | static int ov9740_try_fmt(struct v4l2_subdev *sd, |
| 735 | struct v4l2_mbus_framefmt *mf) |
| 736 | { |
| 737 | ov9740_res_roundup(&mf->width, &mf->height); |
| 738 | |
| 739 | mf->field = V4L2_FIELD_NONE; |
| 740 | mf->code = V4L2_MBUS_FMT_YUYV8_2X8; |
| 741 | mf->colorspace = V4L2_COLORSPACE_SRGB; |
| 742 | |
| 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | static int ov9740_enum_fmt(struct v4l2_subdev *sd, unsigned int index, |
| 747 | enum v4l2_mbus_pixelcode *code) |
| 748 | { |
| 749 | if (index >= ARRAY_SIZE(ov9740_codes)) |
| 750 | return -EINVAL; |
| 751 | |
| 752 | *code = ov9740_codes[index]; |
| 753 | |
| 754 | return 0; |
| 755 | } |
| 756 | |
| 757 | static int ov9740_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) |
| 758 | { |
| 759 | a->bounds.left = 0; |
| 760 | a->bounds.top = 0; |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 761 | a->bounds.width = OV9740_MAX_WIDTH; |
| 762 | a->bounds.height = OV9740_MAX_HEIGHT; |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 763 | a->defrect = a->bounds; |
| 764 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
| 765 | a->pixelaspect.numerator = 1; |
| 766 | a->pixelaspect.denominator = 1; |
| 767 | |
| 768 | return 0; |
| 769 | } |
| 770 | |
| 771 | static int ov9740_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) |
| 772 | { |
| 773 | a->c.left = 0; |
| 774 | a->c.top = 0; |
Andrew Chew | 970aa9e | 2011-06-23 20:19:42 -0300 | [diff] [blame] | 775 | a->c.width = OV9740_MAX_WIDTH; |
| 776 | a->c.height = OV9740_MAX_HEIGHT; |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 777 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
| 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | |
Andrew Chew | e29c9bf | 2011-06-23 20:19:43 -0300 | [diff] [blame^] | 782 | /* Get status of additional camera capabilities */ |
| 783 | static int ov9740_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
| 784 | { |
| 785 | struct ov9740_priv *priv = to_ov9740(sd); |
| 786 | |
| 787 | switch (ctrl->id) { |
| 788 | case V4L2_CID_VFLIP: |
| 789 | ctrl->value = priv->flag_vflip; |
| 790 | break; |
| 791 | case V4L2_CID_HFLIP: |
| 792 | ctrl->value = priv->flag_hflip; |
| 793 | break; |
| 794 | default: |
| 795 | return -EINVAL; |
| 796 | } |
| 797 | |
| 798 | return 0; |
| 799 | } |
| 800 | |
| 801 | /* Set status of additional camera capabilities */ |
| 802 | static int ov9740_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
| 803 | { |
| 804 | struct ov9740_priv *priv = to_ov9740(sd); |
| 805 | |
| 806 | switch (ctrl->id) { |
| 807 | case V4L2_CID_VFLIP: |
| 808 | priv->flag_vflip = ctrl->value; |
| 809 | break; |
| 810 | case V4L2_CID_HFLIP: |
| 811 | priv->flag_hflip = ctrl->value; |
| 812 | break; |
| 813 | default: |
| 814 | return -EINVAL; |
| 815 | } |
| 816 | |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | /* Get chip identification */ |
| 821 | static int ov9740_g_chip_ident(struct v4l2_subdev *sd, |
| 822 | struct v4l2_dbg_chip_ident *id) |
| 823 | { |
| 824 | struct ov9740_priv *priv = to_ov9740(sd); |
| 825 | |
| 826 | id->ident = priv->ident; |
| 827 | id->revision = priv->revision; |
| 828 | |
| 829 | return 0; |
| 830 | } |
| 831 | |
| 832 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 833 | static int ov9740_get_register(struct v4l2_subdev *sd, |
| 834 | struct v4l2_dbg_register *reg) |
| 835 | { |
| 836 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 837 | int ret; |
| 838 | u8 val; |
| 839 | |
| 840 | if (reg->reg & ~0xffff) |
| 841 | return -EINVAL; |
| 842 | |
| 843 | reg->size = 2; |
| 844 | |
| 845 | ret = ov9740_reg_read(client, reg->reg, &val); |
| 846 | if (ret) |
| 847 | return ret; |
| 848 | |
| 849 | reg->val = (__u64)val; |
| 850 | |
| 851 | return ret; |
| 852 | } |
| 853 | |
| 854 | static int ov9740_set_register(struct v4l2_subdev *sd, |
| 855 | struct v4l2_dbg_register *reg) |
| 856 | { |
| 857 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 858 | |
| 859 | if (reg->reg & ~0xffff || reg->val & ~0xff) |
| 860 | return -EINVAL; |
| 861 | |
| 862 | return ov9740_reg_write(client, reg->reg, reg->val); |
| 863 | } |
| 864 | #endif |
| 865 | |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 866 | static int ov9740_video_probe(struct soc_camera_device *icd, |
| 867 | struct i2c_client *client) |
| 868 | { |
| 869 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
| 870 | struct ov9740_priv *priv = to_ov9740(sd); |
| 871 | u8 modelhi, modello; |
| 872 | int ret; |
| 873 | |
| 874 | /* |
| 875 | * We must have a parent by now. And it cannot be a wrong one. |
| 876 | * So this entire test is completely redundant. |
| 877 | */ |
| 878 | if (!icd->dev.parent || |
| 879 | to_soc_camera_host(icd->dev.parent)->nr != icd->iface) { |
| 880 | dev_err(&client->dev, "Parent missing or invalid!\n"); |
| 881 | ret = -ENODEV; |
| 882 | goto err; |
| 883 | } |
| 884 | |
| 885 | /* |
| 886 | * check and show product ID and manufacturer ID |
| 887 | */ |
| 888 | ret = ov9740_reg_read(client, OV9740_MODEL_ID_HI, &modelhi); |
| 889 | if (ret < 0) |
| 890 | goto err; |
| 891 | |
| 892 | ret = ov9740_reg_read(client, OV9740_MODEL_ID_LO, &modello); |
| 893 | if (ret < 0) |
| 894 | goto err; |
| 895 | |
| 896 | priv->model = (modelhi << 8) | modello; |
| 897 | |
| 898 | ret = ov9740_reg_read(client, OV9740_REVISION_NUMBER, &priv->revision); |
| 899 | if (ret < 0) |
| 900 | goto err; |
| 901 | |
| 902 | ret = ov9740_reg_read(client, OV9740_MANUFACTURER_ID, &priv->manid); |
| 903 | if (ret < 0) |
| 904 | goto err; |
| 905 | |
| 906 | ret = ov9740_reg_read(client, OV9740_SMIA_VERSION, &priv->smiaver); |
| 907 | if (ret < 0) |
| 908 | goto err; |
| 909 | |
| 910 | if (priv->model != 0x9740) { |
| 911 | ret = -ENODEV; |
| 912 | goto err; |
| 913 | } |
| 914 | |
| 915 | priv->ident = V4L2_IDENT_OV9740; |
| 916 | |
| 917 | dev_info(&client->dev, "ov9740 Model ID 0x%04x, Revision 0x%02x, " |
| 918 | "Manufacturer 0x%02x, SMIA Version 0x%02x\n", |
| 919 | priv->model, priv->revision, priv->manid, priv->smiaver); |
| 920 | |
| 921 | err: |
| 922 | return ret; |
| 923 | } |
| 924 | |
| 925 | static struct soc_camera_ops ov9740_ops = { |
| 926 | .set_bus_param = ov9740_set_bus_param, |
| 927 | .query_bus_param = ov9740_query_bus_param, |
| 928 | .controls = ov9740_controls, |
| 929 | .num_controls = ARRAY_SIZE(ov9740_controls), |
| 930 | }; |
| 931 | |
Andrew Chew | e29c9bf | 2011-06-23 20:19:43 -0300 | [diff] [blame^] | 932 | static struct v4l2_subdev_video_ops ov9740_video_ops = { |
| 933 | .s_stream = ov9740_s_stream, |
| 934 | .s_mbus_fmt = ov9740_s_fmt, |
| 935 | .try_mbus_fmt = ov9740_try_fmt, |
| 936 | .enum_mbus_fmt = ov9740_enum_fmt, |
| 937 | .cropcap = ov9740_cropcap, |
| 938 | .g_crop = ov9740_g_crop, |
| 939 | }; |
| 940 | |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 941 | static struct v4l2_subdev_core_ops ov9740_core_ops = { |
| 942 | .g_ctrl = ov9740_g_ctrl, |
| 943 | .s_ctrl = ov9740_s_ctrl, |
| 944 | .g_chip_ident = ov9740_g_chip_ident, |
| 945 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 946 | .g_register = ov9740_get_register, |
| 947 | .s_register = ov9740_set_register, |
| 948 | #endif |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 949 | }; |
| 950 | |
Andrew Chew | 9bd060e | 2011-02-17 19:14:33 -0300 | [diff] [blame] | 951 | static struct v4l2_subdev_ops ov9740_subdev_ops = { |
| 952 | .core = &ov9740_core_ops, |
| 953 | .video = &ov9740_video_ops, |
| 954 | }; |
| 955 | |
| 956 | /* |
| 957 | * i2c_driver function |
| 958 | */ |
| 959 | static int ov9740_probe(struct i2c_client *client, |
| 960 | const struct i2c_device_id *did) |
| 961 | { |
| 962 | struct ov9740_priv *priv; |
| 963 | struct soc_camera_device *icd = client->dev.platform_data; |
| 964 | struct soc_camera_link *icl; |
| 965 | int ret; |
| 966 | |
| 967 | if (!icd) { |
| 968 | dev_err(&client->dev, "Missing soc-camera data!\n"); |
| 969 | return -EINVAL; |
| 970 | } |
| 971 | |
| 972 | icl = to_soc_camera_link(icd); |
| 973 | if (!icl) { |
| 974 | dev_err(&client->dev, "Missing platform_data for driver\n"); |
| 975 | return -EINVAL; |
| 976 | } |
| 977 | |
| 978 | priv = kzalloc(sizeof(struct ov9740_priv), GFP_KERNEL); |
| 979 | if (!priv) { |
| 980 | dev_err(&client->dev, "Failed to allocate private data!\n"); |
| 981 | return -ENOMEM; |
| 982 | } |
| 983 | |
| 984 | v4l2_i2c_subdev_init(&priv->subdev, client, &ov9740_subdev_ops); |
| 985 | |
| 986 | icd->ops = &ov9740_ops; |
| 987 | |
| 988 | ret = ov9740_video_probe(icd, client); |
| 989 | if (ret < 0) { |
| 990 | icd->ops = NULL; |
| 991 | kfree(priv); |
| 992 | } |
| 993 | |
| 994 | return ret; |
| 995 | } |
| 996 | |
| 997 | static int ov9740_remove(struct i2c_client *client) |
| 998 | { |
| 999 | struct ov9740_priv *priv = i2c_get_clientdata(client); |
| 1000 | |
| 1001 | kfree(priv); |
| 1002 | |
| 1003 | return 0; |
| 1004 | } |
| 1005 | |
| 1006 | static const struct i2c_device_id ov9740_id[] = { |
| 1007 | { "ov9740", 0 }, |
| 1008 | { } |
| 1009 | }; |
| 1010 | MODULE_DEVICE_TABLE(i2c, ov9740_id); |
| 1011 | |
| 1012 | static struct i2c_driver ov9740_i2c_driver = { |
| 1013 | .driver = { |
| 1014 | .name = "ov9740", |
| 1015 | }, |
| 1016 | .probe = ov9740_probe, |
| 1017 | .remove = ov9740_remove, |
| 1018 | .id_table = ov9740_id, |
| 1019 | }; |
| 1020 | |
| 1021 | static int __init ov9740_module_init(void) |
| 1022 | { |
| 1023 | return i2c_add_driver(&ov9740_i2c_driver); |
| 1024 | } |
| 1025 | |
| 1026 | static void __exit ov9740_module_exit(void) |
| 1027 | { |
| 1028 | i2c_del_driver(&ov9740_i2c_driver); |
| 1029 | } |
| 1030 | |
| 1031 | module_init(ov9740_module_init); |
| 1032 | module_exit(ov9740_module_exit); |
| 1033 | |
| 1034 | MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV9740"); |
| 1035 | MODULE_AUTHOR("Andrew Chew <achew@nvidia.com>"); |
| 1036 | MODULE_LICENSE("GPL v2"); |