| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * include/asm-sh/cpu-sh4/sq.h | 
|  | 3 | * | 
|  | 4 | * Copyright (C) 2001, 2002, 2003  Paul Mundt | 
|  | 5 | * Copyright (C) 2001, 2002  M. R. Brown | 
|  | 6 | * | 
|  | 7 | * This file is subject to the terms and conditions of the GNU General Public | 
|  | 8 | * License.  See the file "COPYING" in the main directory of this archive | 
|  | 9 | * for more details. | 
|  | 10 | */ | 
|  | 11 | #ifndef __ASM_CPU_SH4_SQ_H | 
|  | 12 | #define __ASM_CPU_SH4_SQ_H | 
|  | 13 |  | 
|  | 14 | #include <asm/addrspace.h> | 
|  | 15 |  | 
|  | 16 | /* | 
|  | 17 | * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be | 
|  | 18 | * mapped to any physical address space. Since data is written (and aligned) | 
|  | 19 | * to 32-byte boundaries, we need to be sure that all allocations are aligned. | 
| Paul Mundt | d7c30c6 | 2006-09-27 15:49:57 +0900 | [diff] [blame] | 20 | */ | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #define SQ_SIZE                 32 | 
|  | 22 | #define SQ_ALIGN_MASK           (~(SQ_SIZE - 1)) | 
|  | 23 | #define SQ_ALIGN(addr)          (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK) | 
|  | 24 |  | 
|  | 25 | #define SQ_QACR0		(P4SEG_REG_BASE  + 0x38) | 
|  | 26 | #define SQ_QACR1		(P4SEG_REG_BASE  + 0x3c) | 
|  | 27 | #define SQ_ADDRMAX              (P4SEG_STORE_QUE + 0x04000000) | 
|  | 28 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | /* arch/sh/kernel/cpu/sh4/sq.c */ | 
| Paul Mundt | d7c30c6 | 2006-09-27 15:49:57 +0900 | [diff] [blame] | 30 | unsigned long sq_remap(unsigned long phys, unsigned int size, | 
|  | 31 | const char *name, unsigned long flags); | 
|  | 32 | void sq_unmap(unsigned long vaddr); | 
|  | 33 | void sq_flush_range(unsigned long start, unsigned int len); | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 |  | 
|  | 35 | #endif /* __ASM_CPU_SH4_SQ_H */ |