| Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * Copyright © 2006, Intel Corporation. | 
|  | 3 | * | 
|  | 4 | * This program is free software; you can redistribute it and/or modify it | 
|  | 5 | * under the terms and conditions of the GNU General Public License, | 
|  | 6 | * version 2, as published by the Free Software Foundation. | 
|  | 7 | * | 
|  | 8 | * This program is distributed in the hope it will be useful, but WITHOUT | 
|  | 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 
|  | 10 | * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for | 
|  | 11 | * more details. | 
|  | 12 | * | 
|  | 13 | * You should have received a copy of the GNU General Public License along with | 
|  | 14 | * this program; if not, write to the Free Software Foundation, Inc., | 
|  | 15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | 
|  | 16 | * | 
|  | 17 | */ | 
|  | 18 | #ifndef _ASYNC_TX_H_ | 
|  | 19 | #define _ASYNC_TX_H_ | 
|  | 20 | #include <linux/dmaengine.h> | 
|  | 21 | #include <linux/spinlock.h> | 
|  | 22 | #include <linux/interrupt.h> | 
|  | 23 |  | 
|  | 24 | /** | 
|  | 25 | * dma_chan_ref - object used to manage dma channels received from the | 
|  | 26 | *   dmaengine core. | 
|  | 27 | * @chan - the channel being tracked | 
|  | 28 | * @node - node for the channel to be placed on async_tx_master_list | 
|  | 29 | * @rcu - for list_del_rcu | 
|  | 30 | * @count - number of times this channel is listed in the pool | 
|  | 31 | *	(for channels with multiple capabiities) | 
|  | 32 | */ | 
|  | 33 | struct dma_chan_ref { | 
|  | 34 | struct dma_chan *chan; | 
|  | 35 | struct list_head node; | 
|  | 36 | struct rcu_head rcu; | 
|  | 37 | atomic_t count; | 
|  | 38 | }; | 
|  | 39 |  | 
|  | 40 | /** | 
|  | 41 | * async_tx_flags - modifiers for the async_* calls | 
|  | 42 | * @ASYNC_TX_XOR_ZERO_DST: this flag must be used for xor operations where the | 
|  | 43 | * the destination address is not a source.  The asynchronous case handles this | 
|  | 44 | * implicitly, the synchronous case needs to zero the destination block. | 
|  | 45 | * @ASYNC_TX_XOR_DROP_DST: this flag must be used if the destination address is | 
|  | 46 | * also one of the source addresses.  In the synchronous case the destination | 
|  | 47 | * address is an implied source, whereas the asynchronous case it must be listed | 
|  | 48 | * as a source.  The destination address must be the first address in the source | 
|  | 49 | * array. | 
|  | 50 | * @ASYNC_TX_ASSUME_COHERENT: skip cache maintenance operations | 
|  | 51 | * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a | 
|  | 52 | * dependency chain | 
|  | 53 | * @ASYNC_TX_DEP_ACK: ack the dependency descriptor.  Useful for chaining. | 
| Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 54 | */ | 
|  | 55 | enum async_tx_flags { | 
|  | 56 | ASYNC_TX_XOR_ZERO_DST	 = (1 << 0), | 
|  | 57 | ASYNC_TX_XOR_DROP_DST	 = (1 << 1), | 
|  | 58 | ASYNC_TX_ASSUME_COHERENT = (1 << 2), | 
|  | 59 | ASYNC_TX_ACK		 = (1 << 3), | 
|  | 60 | ASYNC_TX_DEP_ACK	 = (1 << 4), | 
| Dan Williams | 9bc89cd | 2007-01-02 11:10:44 -0700 | [diff] [blame] | 61 | }; | 
|  | 62 |  | 
|  | 63 | #ifdef CONFIG_DMA_ENGINE | 
|  | 64 | void async_tx_issue_pending_all(void); | 
|  | 65 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | 
|  | 66 | void async_tx_run_dependencies(struct dma_async_tx_descriptor *tx); | 
|  | 67 | struct dma_chan * | 
|  | 68 | async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, | 
|  | 69 | enum dma_transaction_type tx_type); | 
|  | 70 | #else | 
|  | 71 | static inline void async_tx_issue_pending_all(void) | 
|  | 72 | { | 
|  | 73 | do { } while (0); | 
|  | 74 | } | 
|  | 75 |  | 
|  | 76 | static inline enum dma_status | 
|  | 77 | dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | 
|  | 78 | { | 
|  | 79 | return DMA_SUCCESS; | 
|  | 80 | } | 
|  | 81 |  | 
|  | 82 | static inline void | 
|  | 83 | async_tx_run_dependencies(struct dma_async_tx_descriptor *tx, | 
|  | 84 | struct dma_chan *host_chan) | 
|  | 85 | { | 
|  | 86 | do { } while (0); | 
|  | 87 | } | 
|  | 88 |  | 
|  | 89 | static inline struct dma_chan * | 
|  | 90 | async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, | 
|  | 91 | enum dma_transaction_type tx_type) | 
|  | 92 | { | 
|  | 93 | return NULL; | 
|  | 94 | } | 
|  | 95 | #endif | 
|  | 96 |  | 
|  | 97 | /** | 
|  | 98 | * async_tx_sync_epilog - actions to take if an operation is run synchronously | 
|  | 99 | * @flags: async_tx flags | 
|  | 100 | * @depend_tx: transaction depends on depend_tx | 
|  | 101 | * @cb_fn: function to call when the transaction completes | 
|  | 102 | * @cb_fn_param: parameter to pass to the callback routine | 
|  | 103 | */ | 
|  | 104 | static inline void | 
|  | 105 | async_tx_sync_epilog(unsigned long flags, | 
|  | 106 | struct dma_async_tx_descriptor *depend_tx, | 
|  | 107 | dma_async_tx_callback cb_fn, void *cb_fn_param) | 
|  | 108 | { | 
|  | 109 | if (cb_fn) | 
|  | 110 | cb_fn(cb_fn_param); | 
|  | 111 |  | 
|  | 112 | if (depend_tx && (flags & ASYNC_TX_DEP_ACK)) | 
|  | 113 | async_tx_ack(depend_tx); | 
|  | 114 | } | 
|  | 115 |  | 
|  | 116 | void | 
|  | 117 | async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx, | 
|  | 118 | enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx, | 
|  | 119 | dma_async_tx_callback cb_fn, void *cb_fn_param); | 
|  | 120 |  | 
|  | 121 | struct dma_async_tx_descriptor * | 
|  | 122 | async_xor(struct page *dest, struct page **src_list, unsigned int offset, | 
|  | 123 | int src_cnt, size_t len, enum async_tx_flags flags, | 
|  | 124 | struct dma_async_tx_descriptor *depend_tx, | 
|  | 125 | dma_async_tx_callback cb_fn, void *cb_fn_param); | 
|  | 126 |  | 
|  | 127 | struct dma_async_tx_descriptor * | 
|  | 128 | async_xor_zero_sum(struct page *dest, struct page **src_list, | 
|  | 129 | unsigned int offset, int src_cnt, size_t len, | 
|  | 130 | u32 *result, enum async_tx_flags flags, | 
|  | 131 | struct dma_async_tx_descriptor *depend_tx, | 
|  | 132 | dma_async_tx_callback cb_fn, void *cb_fn_param); | 
|  | 133 |  | 
|  | 134 | struct dma_async_tx_descriptor * | 
|  | 135 | async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset, | 
|  | 136 | unsigned int src_offset, size_t len, enum async_tx_flags flags, | 
|  | 137 | struct dma_async_tx_descriptor *depend_tx, | 
|  | 138 | dma_async_tx_callback cb_fn, void *cb_fn_param); | 
|  | 139 |  | 
|  | 140 | struct dma_async_tx_descriptor * | 
|  | 141 | async_memset(struct page *dest, int val, unsigned int offset, | 
|  | 142 | size_t len, enum async_tx_flags flags, | 
|  | 143 | struct dma_async_tx_descriptor *depend_tx, | 
|  | 144 | dma_async_tx_callback cb_fn, void *cb_fn_param); | 
|  | 145 |  | 
|  | 146 | struct dma_async_tx_descriptor * | 
|  | 147 | async_trigger_callback(enum async_tx_flags flags, | 
|  | 148 | struct dma_async_tx_descriptor *depend_tx, | 
|  | 149 | dma_async_tx_callback cb_fn, void *cb_fn_param); | 
|  | 150 | #endif /* _ASYNC_TX_H_ */ |