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review.evervolv.com / android_kernel_oneplus_msm8996 / e4e8536f65b51ce91c30588b0925872bdfc60d03 / . / Documentation / devicetree / bindings / clock / imx27-clock.txt
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Fabio Estevamc20736f2012-11-28 15:55:30 -0200[diff] [blame]1* Clock bindings for Freescale i.MX27
2
3Required properties:
4- compatible: Should be "fsl,imx27-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX27
11clocks and IDs.
12
13 Clock ID
14 -----------------------
15 dummy 0
16 ckih 1
17 ckil 2
18 mpll 3
19 spll 4
20 mpll_main2 5
21 ahb 6
22 ipg 7
23 nfc_div 8
24 per1_div 9
25 per2_div 10
26 per3_div 11
27 per4_div 12
28 vpu_sel 13
29 vpu_div 14
30 usb_div 15
31 cpu_sel 16
32 clko_sel 17
33 cpu_div 18
34 clko_div 19
35 ssi1_sel 20
36 ssi2_sel 21
37 ssi1_div 22
38 ssi2_div 23
39 clko_en 24
40 ssi2_ipg_gate 25
41 ssi1_ipg_gate 26
42 slcdc_ipg_gate 27
43 sdhc3_ipg_gate 28
44 sdhc2_ipg_gate 29
45 sdhc1_ipg_gate 30
46 scc_ipg_gate 31
47 sahara_ipg_gate 32
48 rtc_ipg_gate 33
49 pwm_ipg_gate 34
50 owire_ipg_gate 35
51 lcdc_ipg_gate 36
52 kpp_ipg_gate 37
53 iim_ipg_gate 38
54 i2c2_ipg_gate 39
55 i2c1_ipg_gate 40
56 gpt6_ipg_gate 41
57 gpt5_ipg_gate 42
58 gpt4_ipg_gate 43
59 gpt3_ipg_gate 44
60 gpt2_ipg_gate 45
61 gpt1_ipg_gate 46
62 gpio_ipg_gate 47
63 fec_ipg_gate 48
64 emma_ipg_gate 49
65 dma_ipg_gate 50
66 cspi3_ipg_gate 51
67 cspi2_ipg_gate 52
68 cspi1_ipg_gate 53
69 nfc_baud_gate 54
70 ssi2_baud_gate 55
71 ssi1_baud_gate 56
72 vpu_baud_gate 57
73 per4_gate 58
74 per3_gate 59
75 per2_gate 60
76 per1_gate 61
77 usb_ahb_gate 62
78 slcdc_ahb_gate 63
79 sahara_ahb_gate 64
80 lcdc_ahb_gate 65
81 vpu_ahb_gate 66
82 fec_ahb_gate 67
83 emma_ahb_gate 68
84 emi_ahb_gate 69
85 dma_ahb_gate 70
86 csi_ahb_gate 71
87 brom_ahb_gate 72
88 ata_ahb_gate 73
89 wdog_ipg_gate 74
90 usb_ipg_gate 75
91 uart6_ipg_gate 76
92 uart5_ipg_gate 77
93 uart4_ipg_gate 78
94 uart3_ipg_gate 79
95 uart2_ipg_gate 80
96 uart1_ipg_gate 81
97 ckih_div1p5 82
98 fpm 83
99 mpll_osc_sel 84
100 mpll_sel 85
101
102Examples:
103
104clks: ccm@10027000{
105 compatible = "fsl,imx27-ccm";
106 reg = <0x10027000 0x1000>;
107 #clock-cells = <1>;
108};
109
110uart1: serial@1000a000 {
111 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
112 reg = <0x1000a000 0x1000>;
113 interrupts = <20>;
114 clocks = <&clks 81>, <&clks 61>;
115 clock-names = "ipg", "per";
116 status = "disabled";
117};