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Chris Leech0bbd5f42006-05-23 17:35:34 -07001/*
Shannon Nelson43d6e362007-10-16 01:27:39 -07002 * Intel I/OAT DMA Linux driver
Maciej Sosnowski211a22c2009-02-26 11:05:43 +01003 * Copyright(c) 2004 - 2009 Intel Corporation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07004 *
5 * This program is free software; you can redistribute it and/or modify it
Shannon Nelson43d6e362007-10-16 01:27:39 -07006 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07008 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
Shannon Nelson43d6e362007-10-16 01:27:39 -070015 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
Chris Leech0bbd5f42006-05-23 17:35:34 -070017 *
Shannon Nelson43d6e362007-10-16 01:27:39 -070018 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
Chris Leech0bbd5f42006-05-23 17:35:34 -070021 */
22
23/*
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
25 * copy operations.
26 */
27
28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
David S. Miller6b00c922006-05-23 17:37:58 -070034#include <linux/dma-mapping.h>
Maciej Sosnowski09177e82008-07-22 10:07:33 -070035#include <linux/workqueue.h>
Venki Pallipadi3ad0b022008-10-22 16:34:52 -070036#include <linux/i7300_idle.h>
Dan Williams584ec222009-07-28 14:32:12 -070037#include "dma.h"
38#include "registers.h"
39#include "hw.h"
Chris Leech0bbd5f42006-05-23 17:35:34 -070040
Shannon Nelson7bb67c12007-11-14 16:59:51 -080041static int ioat_pending_level = 4;
42module_param(ioat_pending_level, int, 0644);
43MODULE_PARM_DESC(ioat_pending_level,
44 "high-water mark for pushing ioat descriptors (default: 4)");
45
Maciej Sosnowski09177e82008-07-22 10:07:33 -070046static void ioat_dma_chan_reset_part2(struct work_struct *work);
47static void ioat_dma_chan_watchdog(struct work_struct *work);
48
Chris Leech0bbd5f42006-05-23 17:35:34 -070049/* internal functions */
Shannon Nelson43d6e362007-10-16 01:27:39 -070050static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
51static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -080052
Shannon Nelson7f2b2912007-10-18 03:07:14 -070053static struct ioat_desc_sw *
Shannon Nelson7bb67c12007-11-14 16:59:51 -080054ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
55static struct ioat_desc_sw *
56ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -070057
Shannon Nelson7f2b2912007-10-18 03:07:14 -070058static inline struct ioat_dma_chan *ioat_lookup_chan_by_index(
59 struct ioatdma_device *device,
60 int index)
Shannon Nelson3e037452007-10-16 01:27:40 -070061{
62 return device->idx[index];
63}
64
65/**
66 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
67 * @irq: interrupt id
68 * @data: interrupt data
69 */
70static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
71{
72 struct ioatdma_device *instance = data;
73 struct ioat_dma_chan *ioat_chan;
74 unsigned long attnstatus;
75 int bit;
76 u8 intrctrl;
77
78 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
79
80 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
81 return IRQ_NONE;
82
83 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
84 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
85 return IRQ_NONE;
86 }
87
88 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
89 for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
90 ioat_chan = ioat_lookup_chan_by_index(instance, bit);
91 tasklet_schedule(&ioat_chan->cleanup_task);
92 }
93
94 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
95 return IRQ_HANDLED;
96}
97
98/**
99 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
100 * @irq: interrupt id
101 * @data: interrupt data
102 */
103static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
104{
105 struct ioat_dma_chan *ioat_chan = data;
106
107 tasklet_schedule(&ioat_chan->cleanup_task);
108
109 return IRQ_HANDLED;
110}
111
112static void ioat_dma_cleanup_tasklet(unsigned long data);
113
114/**
115 * ioat_dma_enumerate_channels - find and initialize the device's channels
116 * @device: the device to be enumerated
117 */
Shannon Nelson8ab89562007-10-16 01:27:39 -0700118static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700119{
120 u8 xfercap_scale;
121 u32 xfercap;
122 int i;
123 struct ioat_dma_chan *ioat_chan;
Dan Williamse6c0b692009-09-08 17:29:44 -0700124 struct device *dev = &device->pdev->dev;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700125
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700126 /*
127 * IOAT ver.3 workarounds
128 */
129 if (device->version == IOAT_VER_3_0) {
130 u32 chan_err_mask;
131 u16 dev_id;
132 u32 dmauncerrsts;
133
134 /*
135 * Write CHANERRMSK_INT with 3E07h to mask out the errors
136 * that can cause stability issues for IOAT ver.3
137 */
138 chan_err_mask = 0x3E07;
139 pci_write_config_dword(device->pdev,
140 IOAT_PCI_CHANERRMASK_INT_OFFSET,
141 chan_err_mask);
142
143 /*
144 * Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
145 * (workaround for spurious config parity error after restart)
146 */
147 pci_read_config_word(device->pdev,
148 IOAT_PCI_DEVICE_ID_OFFSET,
149 &dev_id);
150 if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) {
151 dmauncerrsts = 0x10;
152 pci_write_config_dword(device->pdev,
153 IOAT_PCI_DMAUNCERRSTS_OFFSET,
154 dmauncerrsts);
155 }
156 }
157
Chris Leeche3828812007-03-08 09:57:35 -0800158 device->common.chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
159 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700160 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
161
Venki Pallipadif371be62008-10-23 15:39:06 -0700162#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
Len Brown2f102602009-05-27 23:59:58 -0400163 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) {
Venki Pallipadi3ad0b022008-10-22 16:34:52 -0700164 device->common.chancnt--;
165 }
Andy Henroid27471fd2008-10-09 11:45:22 -0700166#endif
Chris Leech0bbd5f42006-05-23 17:35:34 -0700167 for (i = 0; i < device->common.chancnt; i++) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700168 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700169 if (!ioat_chan) {
170 device->common.chancnt = i;
171 break;
172 }
173
174 ioat_chan->device = device;
175 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
176 ioat_chan->xfercap = xfercap;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800177 ioat_chan->desccount = 0;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700178 INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);
Maciej Sosnowskiea9c7172009-02-26 11:04:38 +0100179 if (ioat_chan->device->version == IOAT_VER_2_0)
180 writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE |
181 IOAT_DMA_DCA_ANY_CPU,
182 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
183 else if (ioat_chan->device->version == IOAT_VER_3_0)
184 writel(IOAT_DMA_DCA_ANY_CPU,
185 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700186 spin_lock_init(&ioat_chan->cleanup_lock);
187 spin_lock_init(&ioat_chan->desc_lock);
188 INIT_LIST_HEAD(&ioat_chan->free_desc);
189 INIT_LIST_HEAD(&ioat_chan->used_desc);
190 /* This should be made common somewhere in dmaengine.c */
191 ioat_chan->common.device = &device->common;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700192 list_add_tail(&ioat_chan->common.device_node,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700193 &device->common.channels);
Shannon Nelson3e037452007-10-16 01:27:40 -0700194 device->idx[i] = ioat_chan;
195 tasklet_init(&ioat_chan->cleanup_task,
196 ioat_dma_cleanup_tasklet,
197 (unsigned long) ioat_chan);
198 tasklet_disable(&ioat_chan->cleanup_task);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700199 }
200 return device->common.chancnt;
201}
202
Shannon Nelson711924b2007-12-17 16:20:08 -0800203/**
204 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
205 * descriptors to hw
206 * @chan: DMA channel handle
207 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800208static inline void __ioat1_dma_memcpy_issue_pending(
Shannon Nelson711924b2007-12-17 16:20:08 -0800209 struct ioat_dma_chan *ioat_chan)
210{
211 ioat_chan->pending = 0;
212 writeb(IOAT_CHANCMD_APPEND, ioat_chan->reg_base + IOAT1_CHANCMD_OFFSET);
213}
214
215static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
216{
217 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
218
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700219 if (ioat_chan->pending > 0) {
Shannon Nelson711924b2007-12-17 16:20:08 -0800220 spin_lock_bh(&ioat_chan->desc_lock);
221 __ioat1_dma_memcpy_issue_pending(ioat_chan);
222 spin_unlock_bh(&ioat_chan->desc_lock);
223 }
224}
225
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800226static inline void __ioat2_dma_memcpy_issue_pending(
Shannon Nelson711924b2007-12-17 16:20:08 -0800227 struct ioat_dma_chan *ioat_chan)
228{
229 ioat_chan->pending = 0;
230 writew(ioat_chan->dmacount,
231 ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
232}
233
234static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
235{
236 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
237
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700238 if (ioat_chan->pending > 0) {
Shannon Nelson711924b2007-12-17 16:20:08 -0800239 spin_lock_bh(&ioat_chan->desc_lock);
240 __ioat2_dma_memcpy_issue_pending(ioat_chan);
241 spin_unlock_bh(&ioat_chan->desc_lock);
242 }
243}
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800244
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700245
246/**
247 * ioat_dma_chan_reset_part2 - reinit the channel after a reset
248 */
249static void ioat_dma_chan_reset_part2(struct work_struct *work)
250{
251 struct ioat_dma_chan *ioat_chan =
252 container_of(work, struct ioat_dma_chan, work.work);
253 struct ioat_desc_sw *desc;
254
255 spin_lock_bh(&ioat_chan->cleanup_lock);
256 spin_lock_bh(&ioat_chan->desc_lock);
257
258 ioat_chan->completion_virt->low = 0;
259 ioat_chan->completion_virt->high = 0;
260 ioat_chan->pending = 0;
261
262 /*
263 * count the descriptors waiting, and be sure to do it
264 * right for both the CB1 line and the CB2 ring
265 */
266 ioat_chan->dmacount = 0;
267 if (ioat_chan->used_desc.prev) {
268 desc = to_ioat_desc(ioat_chan->used_desc.prev);
269 do {
270 ioat_chan->dmacount++;
271 desc = to_ioat_desc(desc->node.next);
272 } while (&desc->node != ioat_chan->used_desc.next);
273 }
274
275 /*
276 * write the new starting descriptor address
277 * this puts channel engine into ARMED state
278 */
279 desc = to_ioat_desc(ioat_chan->used_desc.prev);
280 switch (ioat_chan->device->version) {
281 case IOAT_VER_1_2:
282 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
283 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
284 writel(((u64) desc->async_tx.phys) >> 32,
285 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
286
287 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
288 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
289 break;
290 case IOAT_VER_2_0:
291 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
292 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
293 writel(((u64) desc->async_tx.phys) >> 32,
294 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
295
296 /* tell the engine to go with what's left to be done */
297 writew(ioat_chan->dmacount,
298 ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
299
300 break;
301 }
302 dev_err(&ioat_chan->device->pdev->dev,
303 "chan%d reset - %d descs waiting, %d total desc\n",
304 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
305
306 spin_unlock_bh(&ioat_chan->desc_lock);
307 spin_unlock_bh(&ioat_chan->cleanup_lock);
308}
309
310/**
311 * ioat_dma_reset_channel - restart a channel
312 * @ioat_chan: IOAT DMA channel handle
313 */
314static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
315{
316 u32 chansts, chanerr;
317
318 if (!ioat_chan->used_desc.prev)
319 return;
320
321 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
322 chansts = (ioat_chan->completion_virt->low
323 & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
324 if (chanerr) {
325 dev_err(&ioat_chan->device->pdev->dev,
326 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
327 chan_num(ioat_chan), chansts, chanerr);
328 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
329 }
330
331 /*
332 * whack it upside the head with a reset
333 * and wait for things to settle out.
334 * force the pending count to a really big negative
335 * to make sure no one forces an issue_pending
336 * while we're waiting.
337 */
338
339 spin_lock_bh(&ioat_chan->desc_lock);
340 ioat_chan->pending = INT_MIN;
341 writeb(IOAT_CHANCMD_RESET,
342 ioat_chan->reg_base
343 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
344 spin_unlock_bh(&ioat_chan->desc_lock);
345
346 /* schedule the 2nd half instead of sleeping a long time */
347 schedule_delayed_work(&ioat_chan->work, RESET_DELAY);
348}
349
350/**
351 * ioat_dma_chan_watchdog - watch for stuck channels
352 */
353static void ioat_dma_chan_watchdog(struct work_struct *work)
354{
355 struct ioatdma_device *device =
356 container_of(work, struct ioatdma_device, work.work);
357 struct ioat_dma_chan *ioat_chan;
358 int i;
359
360 union {
361 u64 full;
362 struct {
363 u32 low;
364 u32 high;
365 };
366 } completion_hw;
367 unsigned long compl_desc_addr_hw;
368
369 for (i = 0; i < device->common.chancnt; i++) {
370 ioat_chan = ioat_lookup_chan_by_index(device, i);
371
372 if (ioat_chan->device->version == IOAT_VER_1_2
373 /* have we started processing anything yet */
374 && ioat_chan->last_completion
375 /* have we completed any since last watchdog cycle? */
376 && (ioat_chan->last_completion ==
377 ioat_chan->watchdog_completion)
378 /* has TCP stuck on one cookie since last watchdog? */
379 && (ioat_chan->watchdog_tcp_cookie ==
380 ioat_chan->watchdog_last_tcp_cookie)
381 && (ioat_chan->watchdog_tcp_cookie !=
382 ioat_chan->completed_cookie)
383 /* is there something in the chain to be processed? */
384 /* CB1 chain always has at least the last one processed */
385 && (ioat_chan->used_desc.prev != ioat_chan->used_desc.next)
386 && ioat_chan->pending == 0) {
387
388 /*
389 * check CHANSTS register for completed
390 * descriptor address.
391 * if it is different than completion writeback,
392 * it is not zero
393 * and it has changed since the last watchdog
394 * we can assume that channel
395 * is still working correctly
396 * and the problem is in completion writeback.
397 * update completion writeback
398 * with actual CHANSTS value
399 * else
400 * try resetting the channel
401 */
402
403 completion_hw.low = readl(ioat_chan->reg_base +
404 IOAT_CHANSTS_OFFSET_LOW(ioat_chan->device->version));
405 completion_hw.high = readl(ioat_chan->reg_base +
406 IOAT_CHANSTS_OFFSET_HIGH(ioat_chan->device->version));
407#if (BITS_PER_LONG == 64)
408 compl_desc_addr_hw =
409 completion_hw.full
410 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
411#else
412 compl_desc_addr_hw =
413 completion_hw.low & IOAT_LOW_COMPLETION_MASK;
414#endif
415
416 if ((compl_desc_addr_hw != 0)
417 && (compl_desc_addr_hw != ioat_chan->watchdog_completion)
418 && (compl_desc_addr_hw != ioat_chan->last_compl_desc_addr_hw)) {
419 ioat_chan->last_compl_desc_addr_hw = compl_desc_addr_hw;
420 ioat_chan->completion_virt->low = completion_hw.low;
421 ioat_chan->completion_virt->high = completion_hw.high;
422 } else {
423 ioat_dma_reset_channel(ioat_chan);
424 ioat_chan->watchdog_completion = 0;
425 ioat_chan->last_compl_desc_addr_hw = 0;
426 }
427
428 /*
429 * for version 2.0 if there are descriptors yet to be processed
430 * and the last completed hasn't changed since the last watchdog
431 * if they haven't hit the pending level
432 * issue the pending to push them through
433 * else
434 * try resetting the channel
435 */
436 } else if (ioat_chan->device->version == IOAT_VER_2_0
437 && ioat_chan->used_desc.prev
438 && ioat_chan->last_completion
439 && ioat_chan->last_completion == ioat_chan->watchdog_completion) {
440
441 if (ioat_chan->pending < ioat_pending_level)
442 ioat2_dma_memcpy_issue_pending(&ioat_chan->common);
443 else {
444 ioat_dma_reset_channel(ioat_chan);
445 ioat_chan->watchdog_completion = 0;
446 }
447 } else {
448 ioat_chan->last_compl_desc_addr_hw = 0;
449 ioat_chan->watchdog_completion
450 = ioat_chan->last_completion;
451 }
452
453 ioat_chan->watchdog_last_tcp_cookie =
454 ioat_chan->watchdog_tcp_cookie;
455 }
456
457 schedule_delayed_work(&device->work, WATCHDOG_DELAY);
458}
459
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800460static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700461{
462 struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700463 struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
464 struct ioat_desc_sw *prev, *new;
465 struct ioat_dma_descriptor *hw;
Dan Williams7405f742007-01-02 11:10:43 -0700466 dma_cookie_t cookie;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700467 LIST_HEAD(new_chain);
468 u32 copy;
469 size_t len;
470 dma_addr_t src, dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700471 unsigned long orig_flags;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700472 unsigned int desc_count = 0;
Dan Williams7405f742007-01-02 11:10:43 -0700473
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700474 /* src and dest and len are stored in the initial descriptor */
475 len = first->len;
476 src = first->src;
477 dst = first->dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700478 orig_flags = first->async_tx.flags;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700479 new = first;
480
Dan Williams7405f742007-01-02 11:10:43 -0700481 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700482 prev = to_ioat_desc(ioat_chan->used_desc.prev);
483 prefetch(prev->hw);
484 do {
Shannon Nelson711924b2007-12-17 16:20:08 -0800485 copy = min_t(size_t, len, ioat_chan->xfercap);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700486
Dan Williams636bdea2008-04-17 20:17:26 -0700487 async_tx_ack(&new->async_tx);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700488
489 hw = new->hw;
490 hw->size = copy;
491 hw->ctl = 0;
492 hw->src_addr = src;
493 hw->dst_addr = dst;
494 hw->next = 0;
495
496 /* chain together the physical address list for the HW */
497 wmb();
498 prev->hw->next = (u64) new->async_tx.phys;
499
500 len -= copy;
501 dst += copy;
502 src += copy;
503
504 list_add_tail(&new->node, &new_chain);
505 desc_count++;
506 prev = new;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800507 } while (len && (new = ioat1_dma_get_next_descriptor(ioat_chan)));
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700508
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700509 if (!new) {
510 dev_err(&ioat_chan->device->pdev->dev,
511 "tx submit failed\n");
512 spin_unlock_bh(&ioat_chan->desc_lock);
513 return -ENOMEM;
514 }
515
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700516 hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
Maciej Sosnowski12ccea22008-11-07 01:46:55 +0000517 if (first->async_tx.callback) {
Shannon Nelson95218432007-10-18 03:07:15 -0700518 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
519 if (first != new) {
520 /* move callback into to last desc */
521 new->async_tx.callback = first->async_tx.callback;
522 new->async_tx.callback_param
523 = first->async_tx.callback_param;
524 first->async_tx.callback = NULL;
525 first->async_tx.callback_param = NULL;
526 }
527 }
528
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700529 new->tx_cnt = desc_count;
Dan Williams636bdea2008-04-17 20:17:26 -0700530 new->async_tx.flags = orig_flags; /* client is in control of this ack */
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700531
532 /* store the original values for use in later cleanup */
533 if (new != first) {
534 new->src = first->src;
535 new->dst = first->dst;
536 new->len = first->len;
537 }
538
Dan Williams7405f742007-01-02 11:10:43 -0700539 /* cookie incr and addition to used_list must be atomic */
540 cookie = ioat_chan->common.cookie;
541 cookie++;
542 if (cookie < 0)
543 cookie = 1;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700544 ioat_chan->common.cookie = new->async_tx.cookie = cookie;
Dan Williams7405f742007-01-02 11:10:43 -0700545
546 /* write address into NextDescriptor field of last desc in chain */
547 to_ioat_desc(ioat_chan->used_desc.prev)->hw->next =
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700548 first->async_tx.phys;
Luis R. Rodriguez7d283ae2008-08-06 15:21:26 -0700549 list_splice_tail(&new_chain, &ioat_chan->used_desc);
Dan Williams7405f742007-01-02 11:10:43 -0700550
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800551 ioat_chan->dmacount += desc_count;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700552 ioat_chan->pending += desc_count;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800553 if (ioat_chan->pending >= ioat_pending_level)
554 __ioat1_dma_memcpy_issue_pending(ioat_chan);
Dan Williams7405f742007-01-02 11:10:43 -0700555 spin_unlock_bh(&ioat_chan->desc_lock);
556
Dan Williams7405f742007-01-02 11:10:43 -0700557 return cookie;
558}
559
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800560static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
561{
562 struct ioat_dma_chan *ioat_chan = to_ioat_chan(tx->chan);
563 struct ioat_desc_sw *first = tx_to_ioat_desc(tx);
564 struct ioat_desc_sw *new;
565 struct ioat_dma_descriptor *hw;
566 dma_cookie_t cookie;
567 u32 copy;
568 size_t len;
569 dma_addr_t src, dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700570 unsigned long orig_flags;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800571 unsigned int desc_count = 0;
572
573 /* src and dest and len are stored in the initial descriptor */
574 len = first->len;
575 src = first->src;
576 dst = first->dst;
Dan Williams636bdea2008-04-17 20:17:26 -0700577 orig_flags = first->async_tx.flags;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800578 new = first;
579
Shannon Nelson711924b2007-12-17 16:20:08 -0800580 /*
581 * ioat_chan->desc_lock is still in force in version 2 path
582 * it gets unlocked at end of this function
583 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800584 do {
Shannon Nelson711924b2007-12-17 16:20:08 -0800585 copy = min_t(size_t, len, ioat_chan->xfercap);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800586
Dan Williams636bdea2008-04-17 20:17:26 -0700587 async_tx_ack(&new->async_tx);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800588
589 hw = new->hw;
590 hw->size = copy;
591 hw->ctl = 0;
592 hw->src_addr = src;
593 hw->dst_addr = dst;
594
595 len -= copy;
596 dst += copy;
597 src += copy;
598 desc_count++;
599 } while (len && (new = ioat2_dma_get_next_descriptor(ioat_chan)));
600
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700601 if (!new) {
602 dev_err(&ioat_chan->device->pdev->dev,
603 "tx submit failed\n");
604 spin_unlock_bh(&ioat_chan->desc_lock);
605 return -ENOMEM;
606 }
607
608 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
Maciej Sosnowski12ccea22008-11-07 01:46:55 +0000609 if (first->async_tx.callback) {
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800610 hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
611 if (first != new) {
612 /* move callback into to last desc */
613 new->async_tx.callback = first->async_tx.callback;
614 new->async_tx.callback_param
615 = first->async_tx.callback_param;
616 first->async_tx.callback = NULL;
617 first->async_tx.callback_param = NULL;
618 }
619 }
620
621 new->tx_cnt = desc_count;
Dan Williams636bdea2008-04-17 20:17:26 -0700622 new->async_tx.flags = orig_flags; /* client is in control of this ack */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800623
624 /* store the original values for use in later cleanup */
625 if (new != first) {
626 new->src = first->src;
627 new->dst = first->dst;
628 new->len = first->len;
629 }
630
631 /* cookie incr and addition to used_list must be atomic */
632 cookie = ioat_chan->common.cookie;
633 cookie++;
634 if (cookie < 0)
635 cookie = 1;
636 ioat_chan->common.cookie = new->async_tx.cookie = cookie;
637
638 ioat_chan->dmacount += desc_count;
639 ioat_chan->pending += desc_count;
640 if (ioat_chan->pending >= ioat_pending_level)
641 __ioat2_dma_memcpy_issue_pending(ioat_chan);
642 spin_unlock_bh(&ioat_chan->desc_lock);
643
644 return cookie;
645}
646
647/**
648 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
649 * @ioat_chan: the channel supplying the memory pool for the descriptors
650 * @flags: allocation flags
651 */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700652static struct ioat_desc_sw *ioat_dma_alloc_descriptor(
Shannon Nelson43d6e362007-10-16 01:27:39 -0700653 struct ioat_dma_chan *ioat_chan,
654 gfp_t flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700655{
656 struct ioat_dma_descriptor *desc;
657 struct ioat_desc_sw *desc_sw;
Shannon Nelson8ab89562007-10-16 01:27:39 -0700658 struct ioatdma_device *ioatdma_device;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700659 dma_addr_t phys;
660
Shannon Nelson8ab89562007-10-16 01:27:39 -0700661 ioatdma_device = to_ioatdma_device(ioat_chan->common.device);
662 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700663 if (unlikely(!desc))
664 return NULL;
665
666 desc_sw = kzalloc(sizeof(*desc_sw), flags);
667 if (unlikely(!desc_sw)) {
Shannon Nelson8ab89562007-10-16 01:27:39 -0700668 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700669 return NULL;
670 }
671
672 memset(desc, 0, sizeof(*desc));
Dan Williams7405f742007-01-02 11:10:43 -0700673 dma_async_tx_descriptor_init(&desc_sw->async_tx, &ioat_chan->common);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800674 switch (ioat_chan->device->version) {
675 case IOAT_VER_1_2:
676 desc_sw->async_tx.tx_submit = ioat1_tx_submit;
677 break;
678 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700679 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800680 desc_sw->async_tx.tx_submit = ioat2_tx_submit;
681 break;
682 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800683
Chris Leech0bbd5f42006-05-23 17:35:34 -0700684 desc_sw->hw = desc;
Dan Williams7405f742007-01-02 11:10:43 -0700685 desc_sw->async_tx.phys = phys;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700686
687 return desc_sw;
688}
689
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800690static int ioat_initial_desc_count = 256;
691module_param(ioat_initial_desc_count, int, 0644);
692MODULE_PARM_DESC(ioat_initial_desc_count,
693 "initial descriptors per channel (default: 256)");
694
695/**
696 * ioat2_dma_massage_chan_desc - link the descriptors into a circle
697 * @ioat_chan: the channel to be massaged
698 */
699static void ioat2_dma_massage_chan_desc(struct ioat_dma_chan *ioat_chan)
700{
701 struct ioat_desc_sw *desc, *_desc;
702
703 /* setup used_desc */
704 ioat_chan->used_desc.next = ioat_chan->free_desc.next;
705 ioat_chan->used_desc.prev = NULL;
706
707 /* pull free_desc out of the circle so that every node is a hw
708 * descriptor, but leave it pointing to the list
709 */
710 ioat_chan->free_desc.prev->next = ioat_chan->free_desc.next;
711 ioat_chan->free_desc.next->prev = ioat_chan->free_desc.prev;
712
713 /* circle link the hw descriptors */
714 desc = to_ioat_desc(ioat_chan->free_desc.next);
715 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
716 list_for_each_entry_safe(desc, _desc, ioat_chan->free_desc.next, node) {
717 desc->hw->next = to_ioat_desc(desc->node.next)->async_tx.phys;
718 }
719}
720
721/**
722 * ioat_dma_alloc_chan_resources - returns the number of allocated descriptors
723 * @chan: the channel to be filled out
724 */
Dan Williamsaa1e6f12009-01-06 11:38:17 -0700725static int ioat_dma_alloc_chan_resources(struct dma_chan *chan)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700726{
727 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
Shannon Nelson711924b2007-12-17 16:20:08 -0800728 struct ioat_desc_sw *desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700729 u16 chanctrl;
730 u32 chanerr;
731 int i;
732 LIST_HEAD(tmp_list);
733
Shannon Nelsone4223972007-08-24 23:02:53 -0700734 /* have we already been set up? */
735 if (!list_empty(&ioat_chan->free_desc))
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800736 return ioat_chan->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700737
Shannon Nelson43d6e362007-10-16 01:27:39 -0700738 /* Setup register to interrupt and write completion status on error */
Shannon Nelsone4223972007-08-24 23:02:53 -0700739 chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
Chris Leech0bbd5f42006-05-23 17:35:34 -0700740 IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
741 IOAT_CHANCTRL_ERR_COMPLETION_EN;
Shannon Nelson43d6e362007-10-16 01:27:39 -0700742 writew(chanctrl, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700743
Chris Leeche3828812007-03-08 09:57:35 -0800744 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700745 if (chanerr) {
Shannon Nelson43d6e362007-10-16 01:27:39 -0700746 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -0700747 "CHANERR = %x, clearing\n", chanerr);
Chris Leeche3828812007-03-08 09:57:35 -0800748 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700749 }
750
751 /* Allocate descriptors */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800752 for (i = 0; i < ioat_initial_desc_count; i++) {
Chris Leech0bbd5f42006-05-23 17:35:34 -0700753 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_KERNEL);
754 if (!desc) {
Shannon Nelson43d6e362007-10-16 01:27:39 -0700755 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -0700756 "Only %d initial descriptors\n", i);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700757 break;
758 }
759 list_add_tail(&desc->node, &tmp_list);
760 }
761 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800762 ioat_chan->desccount = i;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700763 list_splice(&tmp_list, &ioat_chan->free_desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800764 if (ioat_chan->device->version != IOAT_VER_1_2)
765 ioat2_dma_massage_chan_desc(ioat_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700766 spin_unlock_bh(&ioat_chan->desc_lock);
767
768 /* allocate a completion writeback area */
769 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
770 ioat_chan->completion_virt =
771 pci_pool_alloc(ioat_chan->device->completion_pool,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700772 GFP_KERNEL,
773 &ioat_chan->completion_addr);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700774 memset(ioat_chan->completion_virt, 0,
775 sizeof(*ioat_chan->completion_virt));
Chris Leeche3828812007-03-08 09:57:35 -0800776 writel(((u64) ioat_chan->completion_addr) & 0x00000000FFFFFFFF,
777 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
778 writel(((u64) ioat_chan->completion_addr) >> 32,
779 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700780
Shannon Nelson3e037452007-10-16 01:27:40 -0700781 tasklet_enable(&ioat_chan->cleanup_task);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800782 ioat_dma_start_null_desc(ioat_chan); /* give chain to dma device */
783 return ioat_chan->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700784}
785
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800786/**
787 * ioat_dma_free_chan_resources - release all the descriptors
788 * @chan: the channel to be cleaned
789 */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700790static void ioat_dma_free_chan_resources(struct dma_chan *chan)
791{
792 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700793 struct ioatdma_device *ioatdma_device = to_ioatdma_device(chan->device);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700794 struct ioat_desc_sw *desc, *_desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700795 int in_use_descs = 0;
796
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000797 /* Before freeing channel resources first check
798 * if they have been previously allocated for this channel.
799 */
800 if (ioat_chan->desccount == 0)
801 return;
802
Shannon Nelson3e037452007-10-16 01:27:40 -0700803 tasklet_disable(&ioat_chan->cleanup_task);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700804 ioat_dma_memcpy_cleanup(ioat_chan);
805
Shannon Nelson3e037452007-10-16 01:27:40 -0700806 /* Delay 100ms after reset to allow internal DMA logic to quiesce
807 * before removing DMA descriptor resources.
808 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800809 writeb(IOAT_CHANCMD_RESET,
810 ioat_chan->reg_base
811 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
Shannon Nelson3e037452007-10-16 01:27:40 -0700812 mdelay(100);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700813
814 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800815 switch (ioat_chan->device->version) {
816 case IOAT_VER_1_2:
817 list_for_each_entry_safe(desc, _desc,
818 &ioat_chan->used_desc, node) {
819 in_use_descs++;
820 list_del(&desc->node);
821 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
822 desc->async_tx.phys);
823 kfree(desc);
824 }
825 list_for_each_entry_safe(desc, _desc,
826 &ioat_chan->free_desc, node) {
827 list_del(&desc->node);
828 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
829 desc->async_tx.phys);
830 kfree(desc);
831 }
832 break;
833 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700834 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800835 list_for_each_entry_safe(desc, _desc,
836 ioat_chan->free_desc.next, node) {
837 list_del(&desc->node);
838 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
839 desc->async_tx.phys);
840 kfree(desc);
841 }
842 desc = to_ioat_desc(ioat_chan->free_desc.next);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700843 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
Dan Williams7405f742007-01-02 11:10:43 -0700844 desc->async_tx.phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700845 kfree(desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800846 INIT_LIST_HEAD(&ioat_chan->free_desc);
847 INIT_LIST_HEAD(&ioat_chan->used_desc);
848 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700849 }
850 spin_unlock_bh(&ioat_chan->desc_lock);
851
Shannon Nelson8ab89562007-10-16 01:27:39 -0700852 pci_pool_free(ioatdma_device->completion_pool,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700853 ioat_chan->completion_virt,
854 ioat_chan->completion_addr);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700855
856 /* one is ok since we left it on there on purpose */
857 if (in_use_descs > 1)
Shannon Nelson43d6e362007-10-16 01:27:39 -0700858 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -0700859 "Freeing %d in use descriptors!\n",
Chris Leech0bbd5f42006-05-23 17:35:34 -0700860 in_use_descs - 1);
861
862 ioat_chan->last_completion = ioat_chan->completion_addr = 0;
Shannon Nelson3e037452007-10-16 01:27:40 -0700863 ioat_chan->pending = 0;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800864 ioat_chan->dmacount = 0;
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000865 ioat_chan->desccount = 0;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700866 ioat_chan->watchdog_completion = 0;
867 ioat_chan->last_compl_desc_addr_hw = 0;
868 ioat_chan->watchdog_tcp_cookie =
869 ioat_chan->watchdog_last_tcp_cookie = 0;
Shannon Nelson3e037452007-10-16 01:27:40 -0700870}
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700871
Shannon Nelson3e037452007-10-16 01:27:40 -0700872/**
873 * ioat_dma_get_next_descriptor - return the next available descriptor
874 * @ioat_chan: IOAT DMA channel handle
875 *
876 * Gets the next descriptor from the chain, and must be called with the
877 * channel's desc_lock held. Allocates more descriptors if the channel
878 * has run out.
879 */
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700880static struct ioat_desc_sw *
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800881ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
Shannon Nelson3e037452007-10-16 01:27:40 -0700882{
Shannon Nelson711924b2007-12-17 16:20:08 -0800883 struct ioat_desc_sw *new;
Shannon Nelson3e037452007-10-16 01:27:40 -0700884
885 if (!list_empty(&ioat_chan->free_desc)) {
886 new = to_ioat_desc(ioat_chan->free_desc.next);
887 list_del(&new->node);
888 } else {
889 /* try to get another desc */
890 new = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
Shannon Nelson711924b2007-12-17 16:20:08 -0800891 if (!new) {
892 dev_err(&ioat_chan->device->pdev->dev,
893 "alloc failed\n");
894 return NULL;
895 }
Shannon Nelson3e037452007-10-16 01:27:40 -0700896 }
897
898 prefetch(new->hw);
899 return new;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700900}
901
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800902static struct ioat_desc_sw *
903ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
904{
Shannon Nelson711924b2007-12-17 16:20:08 -0800905 struct ioat_desc_sw *new;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800906
907 /*
908 * used.prev points to where to start processing
909 * used.next points to next free descriptor
910 * if used.prev == NULL, there are none waiting to be processed
911 * if used.next == used.prev.prev, there is only one free descriptor,
912 * and we need to use it to as a noop descriptor before
913 * linking in a new set of descriptors, since the device
914 * has probably already read the pointer to it
915 */
916 if (ioat_chan->used_desc.prev &&
917 ioat_chan->used_desc.next == ioat_chan->used_desc.prev->prev) {
918
Shannon Nelson711924b2007-12-17 16:20:08 -0800919 struct ioat_desc_sw *desc;
920 struct ioat_desc_sw *noop_desc;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800921 int i;
922
923 /* set up the noop descriptor */
924 noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700925 /* set size to non-zero value (channel returns error when size is 0) */
926 noop_desc->hw->size = NULL_DESC_BUFFER_SIZE;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800927 noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
928 noop_desc->hw->src_addr = 0;
929 noop_desc->hw->dst_addr = 0;
930
931 ioat_chan->used_desc.next = ioat_chan->used_desc.next->next;
932 ioat_chan->pending++;
933 ioat_chan->dmacount++;
934
Shannon Nelson711924b2007-12-17 16:20:08 -0800935 /* try to get a few more descriptors */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800936 for (i = 16; i; i--) {
937 desc = ioat_dma_alloc_descriptor(ioat_chan, GFP_ATOMIC);
Shannon Nelson711924b2007-12-17 16:20:08 -0800938 if (!desc) {
939 dev_err(&ioat_chan->device->pdev->dev,
940 "alloc failed\n");
941 break;
942 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800943 list_add_tail(&desc->node, ioat_chan->used_desc.next);
944
945 desc->hw->next
946 = to_ioat_desc(desc->node.next)->async_tx.phys;
947 to_ioat_desc(desc->node.prev)->hw->next
948 = desc->async_tx.phys;
949 ioat_chan->desccount++;
950 }
951
952 ioat_chan->used_desc.next = noop_desc->node.next;
953 }
954 new = to_ioat_desc(ioat_chan->used_desc.next);
955 prefetch(new);
956 ioat_chan->used_desc.next = new->node.next;
957
958 if (ioat_chan->used_desc.prev == NULL)
959 ioat_chan->used_desc.prev = &new->node;
960
961 prefetch(new->hw);
962 return new;
963}
964
965static struct ioat_desc_sw *ioat_dma_get_next_descriptor(
966 struct ioat_dma_chan *ioat_chan)
967{
968 if (!ioat_chan)
969 return NULL;
970
971 switch (ioat_chan->device->version) {
972 case IOAT_VER_1_2:
973 return ioat1_dma_get_next_descriptor(ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800974 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700975 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800976 return ioat2_dma_get_next_descriptor(ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800977 }
978 return NULL;
979}
980
981static struct dma_async_tx_descriptor *ioat1_dma_prep_memcpy(
Shannon Nelson43d6e362007-10-16 01:27:39 -0700982 struct dma_chan *chan,
Dan Williams00367312008-02-02 19:49:57 -0700983 dma_addr_t dma_dest,
984 dma_addr_t dma_src,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700985 size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -0700986 unsigned long flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700987{
Dan Williams7405f742007-01-02 11:10:43 -0700988 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700989 struct ioat_desc_sw *new;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700990
991 spin_lock_bh(&ioat_chan->desc_lock);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700992 new = ioat_dma_get_next_descriptor(ioat_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700993 spin_unlock_bh(&ioat_chan->desc_lock);
994
Shannon Nelson711924b2007-12-17 16:20:08 -0800995 if (new) {
996 new->len = len;
Dan Williams00367312008-02-02 19:49:57 -0700997 new->dst = dma_dest;
998 new->src = dma_src;
Dan Williams636bdea2008-04-17 20:17:26 -0700999 new->async_tx.flags = flags;
Shannon Nelson711924b2007-12-17 16:20:08 -08001000 return &new->async_tx;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001001 } else {
1002 dev_err(&ioat_chan->device->pdev->dev,
1003 "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1004 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
Shannon Nelson711924b2007-12-17 16:20:08 -08001005 return NULL;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001006 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001007}
1008
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001009static struct dma_async_tx_descriptor *ioat2_dma_prep_memcpy(
1010 struct dma_chan *chan,
Dan Williams00367312008-02-02 19:49:57 -07001011 dma_addr_t dma_dest,
1012 dma_addr_t dma_src,
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001013 size_t len,
Dan Williamsd4c56f92008-02-02 19:49:58 -07001014 unsigned long flags)
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001015{
1016 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1017 struct ioat_desc_sw *new;
1018
1019 spin_lock_bh(&ioat_chan->desc_lock);
1020 new = ioat2_dma_get_next_descriptor(ioat_chan);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001021
Shannon Nelson711924b2007-12-17 16:20:08 -08001022 /*
1023 * leave ioat_chan->desc_lock set in ioat 2 path
1024 * it will get unlocked at end of tx_submit
1025 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001026
Shannon Nelson711924b2007-12-17 16:20:08 -08001027 if (new) {
1028 new->len = len;
Dan Williams00367312008-02-02 19:49:57 -07001029 new->dst = dma_dest;
1030 new->src = dma_src;
Dan Williams636bdea2008-04-17 20:17:26 -07001031 new->async_tx.flags = flags;
Shannon Nelson711924b2007-12-17 16:20:08 -08001032 return &new->async_tx;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001033 } else {
1034 spin_unlock_bh(&ioat_chan->desc_lock);
1035 dev_err(&ioat_chan->device->pdev->dev,
1036 "chan%d - get_next_desc failed: %d descs waiting, %d total desc\n",
1037 chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
Shannon Nelson711924b2007-12-17 16:20:08 -08001038 return NULL;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001039 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001040}
1041
Shannon Nelson3e037452007-10-16 01:27:40 -07001042static void ioat_dma_cleanup_tasklet(unsigned long data)
1043{
1044 struct ioat_dma_chan *chan = (void *)data;
1045 ioat_dma_memcpy_cleanup(chan);
1046 writew(IOAT_CHANCTRL_INT_DISABLE,
1047 chan->reg_base + IOAT_CHANCTRL_OFFSET);
1048}
1049
Dan Williamse1d181e2008-07-04 00:13:40 -07001050static void
1051ioat_dma_unmap(struct ioat_dma_chan *ioat_chan, struct ioat_desc_sw *desc)
1052{
Maciej Sosnowski4f005db2009-04-23 12:31:51 +02001053 if (!(desc->async_tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1054 if (desc->async_tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1055 pci_unmap_single(ioat_chan->device->pdev,
1056 pci_unmap_addr(desc, dst),
1057 pci_unmap_len(desc, len),
1058 PCI_DMA_FROMDEVICE);
1059 else
1060 pci_unmap_page(ioat_chan->device->pdev,
1061 pci_unmap_addr(desc, dst),
1062 pci_unmap_len(desc, len),
1063 PCI_DMA_FROMDEVICE);
1064 }
Dan Williamse1d181e2008-07-04 00:13:40 -07001065
Maciej Sosnowski4f005db2009-04-23 12:31:51 +02001066 if (!(desc->async_tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1067 if (desc->async_tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1068 pci_unmap_single(ioat_chan->device->pdev,
1069 pci_unmap_addr(desc, src),
1070 pci_unmap_len(desc, len),
1071 PCI_DMA_TODEVICE);
1072 else
1073 pci_unmap_page(ioat_chan->device->pdev,
1074 pci_unmap_addr(desc, src),
1075 pci_unmap_len(desc, len),
1076 PCI_DMA_TODEVICE);
1077 }
Dan Williamse1d181e2008-07-04 00:13:40 -07001078}
1079
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001080/**
1081 * ioat_dma_memcpy_cleanup - cleanup up finished descriptors
1082 * @chan: ioat channel to be cleaned up
1083 */
Shannon Nelson43d6e362007-10-16 01:27:39 -07001084static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001085{
1086 unsigned long phys_complete;
1087 struct ioat_desc_sw *desc, *_desc;
1088 dma_cookie_t cookie = 0;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001089 unsigned long desc_phys;
1090 struct ioat_desc_sw *latest_desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001091
Shannon Nelson43d6e362007-10-16 01:27:39 -07001092 prefetch(ioat_chan->completion_virt);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001093
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001094 if (!spin_trylock_bh(&ioat_chan->cleanup_lock))
Chris Leech0bbd5f42006-05-23 17:35:34 -07001095 return;
1096
1097 /* The completion writeback can happen at any time,
1098 so reads by the driver need to be atomic operations
1099 The descriptor physical addresses are limited to 32-bits
1100 when the CPU can only do a 32-bit mov */
1101
1102#if (BITS_PER_LONG == 64)
1103 phys_complete =
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001104 ioat_chan->completion_virt->full
1105 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001106#else
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001107 phys_complete =
1108 ioat_chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001109#endif
1110
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001111 if ((ioat_chan->completion_virt->full
1112 & IOAT_CHANSTS_DMA_TRANSFER_STATUS) ==
Shannon Nelson43d6e362007-10-16 01:27:39 -07001113 IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) {
1114 dev_err(&ioat_chan->device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001115 "Channel halted, chanerr = %x\n",
Shannon Nelson43d6e362007-10-16 01:27:39 -07001116 readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET));
Chris Leech0bbd5f42006-05-23 17:35:34 -07001117
1118 /* TODO do something to salvage the situation */
1119 }
1120
Shannon Nelson43d6e362007-10-16 01:27:39 -07001121 if (phys_complete == ioat_chan->last_completion) {
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001122 spin_unlock_bh(&ioat_chan->cleanup_lock);
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001123 /*
1124 * perhaps we're stuck so hard that the watchdog can't go off?
1125 * try to catch it after 2 seconds
1126 */
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001127 if (ioat_chan->device->version != IOAT_VER_3_0) {
1128 if (time_after(jiffies,
1129 ioat_chan->last_completion_time + HZ*WATCHDOG_DELAY)) {
1130 ioat_dma_chan_watchdog(&(ioat_chan->device->work.work));
1131 ioat_chan->last_completion_time = jiffies;
1132 }
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001133 }
1134 return;
1135 }
1136 ioat_chan->last_completion_time = jiffies;
1137
1138 cookie = 0;
1139 if (!spin_trylock_bh(&ioat_chan->desc_lock)) {
1140 spin_unlock_bh(&ioat_chan->cleanup_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001141 return;
1142 }
1143
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001144 switch (ioat_chan->device->version) {
1145 case IOAT_VER_1_2:
1146 list_for_each_entry_safe(desc, _desc,
1147 &ioat_chan->used_desc, node) {
Chris Leech0bbd5f42006-05-23 17:35:34 -07001148
Shannon Nelson43d6e362007-10-16 01:27:39 -07001149 /*
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001150 * Incoming DMA requests may use multiple descriptors,
1151 * due to exceeding xfercap, perhaps. If so, only the
1152 * last one will have a cookie, and require unmapping.
Shannon Nelson43d6e362007-10-16 01:27:39 -07001153 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001154 if (desc->async_tx.cookie) {
1155 cookie = desc->async_tx.cookie;
Dan Williamse1d181e2008-07-04 00:13:40 -07001156 ioat_dma_unmap(ioat_chan, desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001157 if (desc->async_tx.callback) {
1158 desc->async_tx.callback(desc->async_tx.callback_param);
1159 desc->async_tx.callback = NULL;
1160 }
1161 }
1162
1163 if (desc->async_tx.phys != phys_complete) {
1164 /*
1165 * a completed entry, but not the last, so clean
1166 * up if the client is done with the descriptor
1167 */
Dan Williams636bdea2008-04-17 20:17:26 -07001168 if (async_tx_test_ack(&desc->async_tx)) {
Eric Sesterhennaa2d0b82009-02-26 11:05:30 +01001169 list_move_tail(&desc->node,
1170 &ioat_chan->free_desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001171 } else
1172 desc->async_tx.cookie = 0;
1173 } else {
1174 /*
1175 * last used desc. Do not remove, so we can
1176 * append from it, but don't look at it next
1177 * time, either
1178 */
1179 desc->async_tx.cookie = 0;
1180
1181 /* TODO check status bits? */
1182 break;
Shannon Nelson95218432007-10-18 03:07:15 -07001183 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001184 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001185 break;
1186 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001187 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001188 /* has some other thread has already cleaned up? */
1189 if (ioat_chan->used_desc.prev == NULL)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001190 break;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001191
1192 /* work backwards to find latest finished desc */
1193 desc = to_ioat_desc(ioat_chan->used_desc.next);
1194 latest_desc = NULL;
1195 do {
1196 desc = to_ioat_desc(desc->node.prev);
1197 desc_phys = (unsigned long)desc->async_tx.phys
1198 & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
1199 if (desc_phys == phys_complete) {
1200 latest_desc = desc;
1201 break;
1202 }
1203 } while (&desc->node != ioat_chan->used_desc.prev);
1204
1205 if (latest_desc != NULL) {
1206
1207 /* work forwards to clear finished descriptors */
1208 for (desc = to_ioat_desc(ioat_chan->used_desc.prev);
1209 &desc->node != latest_desc->node.next &&
1210 &desc->node != ioat_chan->used_desc.next;
1211 desc = to_ioat_desc(desc->node.next)) {
1212 if (desc->async_tx.cookie) {
1213 cookie = desc->async_tx.cookie;
1214 desc->async_tx.cookie = 0;
Dan Williamse1d181e2008-07-04 00:13:40 -07001215 ioat_dma_unmap(ioat_chan, desc);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001216 if (desc->async_tx.callback) {
1217 desc->async_tx.callback(desc->async_tx.callback_param);
1218 desc->async_tx.callback = NULL;
1219 }
1220 }
1221 }
1222
1223 /* move used.prev up beyond those that are finished */
1224 if (&desc->node == ioat_chan->used_desc.next)
1225 ioat_chan->used_desc.prev = NULL;
1226 else
1227 ioat_chan->used_desc.prev = &desc->node;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001228 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001229 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001230 }
1231
Shannon Nelson43d6e362007-10-16 01:27:39 -07001232 spin_unlock_bh(&ioat_chan->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001233
Shannon Nelson43d6e362007-10-16 01:27:39 -07001234 ioat_chan->last_completion = phys_complete;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001235 if (cookie != 0)
Shannon Nelson43d6e362007-10-16 01:27:39 -07001236 ioat_chan->completed_cookie = cookie;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001237
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001238 spin_unlock_bh(&ioat_chan->cleanup_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001239}
1240
1241/**
1242 * ioat_dma_is_complete - poll the status of a IOAT DMA transaction
1243 * @chan: IOAT DMA channel handle
1244 * @cookie: DMA transaction identifier
Randy Dunlap65088712006-07-03 19:45:31 -07001245 * @done: if not %NULL, updated with last completed transaction
1246 * @used: if not %NULL, updated with last used transaction
Chris Leech0bbd5f42006-05-23 17:35:34 -07001247 */
Chris Leech0bbd5f42006-05-23 17:35:34 -07001248static enum dma_status ioat_dma_is_complete(struct dma_chan *chan,
Shannon Nelson43d6e362007-10-16 01:27:39 -07001249 dma_cookie_t cookie,
1250 dma_cookie_t *done,
1251 dma_cookie_t *used)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001252{
1253 struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
1254 dma_cookie_t last_used;
1255 dma_cookie_t last_complete;
1256 enum dma_status ret;
1257
1258 last_used = chan->cookie;
1259 last_complete = ioat_chan->completed_cookie;
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001260 ioat_chan->watchdog_tcp_cookie = cookie;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001261
1262 if (done)
Shannon Nelson43d6e362007-10-16 01:27:39 -07001263 *done = last_complete;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001264 if (used)
1265 *used = last_used;
1266
1267 ret = dma_async_is_complete(cookie, last_complete, last_used);
1268 if (ret == DMA_SUCCESS)
1269 return ret;
1270
1271 ioat_dma_memcpy_cleanup(ioat_chan);
1272
1273 last_used = chan->cookie;
1274 last_complete = ioat_chan->completed_cookie;
1275
1276 if (done)
Shannon Nelson43d6e362007-10-16 01:27:39 -07001277 *done = last_complete;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001278 if (used)
1279 *used = last_used;
1280
1281 return dma_async_is_complete(cookie, last_complete, last_used);
1282}
1283
Shannon Nelson43d6e362007-10-16 01:27:39 -07001284static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001285{
1286 struct ioat_desc_sw *desc;
1287
1288 spin_lock_bh(&ioat_chan->desc_lock);
1289
Shannon Nelson3e037452007-10-16 01:27:40 -07001290 desc = ioat_dma_get_next_descriptor(ioat_chan);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001291
1292 if (!desc) {
1293 dev_err(&ioat_chan->device->pdev->dev,
1294 "Unable to start null desc - get next desc failed\n");
1295 spin_unlock_bh(&ioat_chan->desc_lock);
1296 return;
1297 }
1298
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001299 desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
1300 | IOAT_DMA_DESCRIPTOR_CTL_INT_GN
1301 | IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001302 /* set size to non-zero value (channel returns error when size is 0) */
1303 desc->hw->size = NULL_DESC_BUFFER_SIZE;
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001304 desc->hw->src_addr = 0;
1305 desc->hw->dst_addr = 0;
Dan Williams636bdea2008-04-17 20:17:26 -07001306 async_tx_ack(&desc->async_tx);
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001307 switch (ioat_chan->device->version) {
1308 case IOAT_VER_1_2:
1309 desc->hw->next = 0;
1310 list_add_tail(&desc->node, &ioat_chan->used_desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001311
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001312 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1313 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
1314 writel(((u64) desc->async_tx.phys) >> 32,
1315 ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
1316
1317 writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
1318 + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
1319 break;
1320 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001321 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001322 writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
1323 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
1324 writel(((u64) desc->async_tx.phys) >> 32,
1325 ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
1326
1327 ioat_chan->dmacount++;
1328 __ioat2_dma_memcpy_issue_pending(ioat_chan);
1329 break;
1330 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001331 spin_unlock_bh(&ioat_chan->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001332}
1333
1334/*
1335 * Perform a IOAT transaction to verify the HW works.
1336 */
1337#define IOAT_TEST_SIZE 2000
1338
Shannon Nelson95218432007-10-18 03:07:15 -07001339static void ioat_dma_test_callback(void *dma_async_param)
1340{
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001341 struct completion *cmp = dma_async_param;
1342
1343 complete(cmp);
Shannon Nelson95218432007-10-18 03:07:15 -07001344}
1345
Shannon Nelson3e037452007-10-16 01:27:40 -07001346/**
1347 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
1348 * @device: device to be tested
1349 */
1350static int ioat_dma_self_test(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001351{
1352 int i;
1353 u8 *src;
1354 u8 *dest;
1355 struct dma_chan *dma_chan;
Shannon Nelson711924b2007-12-17 16:20:08 -08001356 struct dma_async_tx_descriptor *tx;
Dan Williams00367312008-02-02 19:49:57 -07001357 dma_addr_t dma_dest, dma_src;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001358 dma_cookie_t cookie;
1359 int err = 0;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001360 struct completion cmp;
Dan Williams0c33e1c2009-03-02 13:31:35 -07001361 unsigned long tmo;
Maciej Sosnowski4f005db2009-04-23 12:31:51 +02001362 unsigned long flags;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001363
Christoph Lametere94b1762006-12-06 20:33:17 -08001364 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001365 if (!src)
1366 return -ENOMEM;
Christoph Lametere94b1762006-12-06 20:33:17 -08001367 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001368 if (!dest) {
1369 kfree(src);
1370 return -ENOMEM;
1371 }
1372
1373 /* Fill in src buffer */
1374 for (i = 0; i < IOAT_TEST_SIZE; i++)
1375 src[i] = (u8)i;
1376
1377 /* Start copy, using first DMA channel */
1378 dma_chan = container_of(device->common.channels.next,
Shannon Nelson43d6e362007-10-16 01:27:39 -07001379 struct dma_chan,
1380 device_node);
Dan Williamsaa1e6f12009-01-06 11:38:17 -07001381 if (device->common.device_alloc_chan_resources(dma_chan) < 1) {
Shannon Nelson43d6e362007-10-16 01:27:39 -07001382 dev_err(&device->pdev->dev,
1383 "selftest cannot allocate chan resource\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -07001384 err = -ENODEV;
1385 goto out;
1386 }
1387
Dan Williams00367312008-02-02 19:49:57 -07001388 dma_src = dma_map_single(dma_chan->device->dev, src, IOAT_TEST_SIZE,
1389 DMA_TO_DEVICE);
1390 dma_dest = dma_map_single(dma_chan->device->dev, dest, IOAT_TEST_SIZE,
1391 DMA_FROM_DEVICE);
Maciej Sosnowski4f005db2009-04-23 12:31:51 +02001392 flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE;
Dan Williams00367312008-02-02 19:49:57 -07001393 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
Maciej Sosnowski4f005db2009-04-23 12:31:51 +02001394 IOAT_TEST_SIZE, flags);
Shannon Nelson5149fd02007-10-18 03:07:13 -07001395 if (!tx) {
1396 dev_err(&device->pdev->dev,
1397 "Self-test prep failed, disabling\n");
1398 err = -ENODEV;
1399 goto free_resources;
1400 }
1401
Dan Williams7405f742007-01-02 11:10:43 -07001402 async_tx_ack(tx);
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001403 init_completion(&cmp);
Shannon Nelson95218432007-10-18 03:07:15 -07001404 tx->callback = ioat_dma_test_callback;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -07001405 tx->callback_param = &cmp;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001406 cookie = tx->tx_submit(tx);
Shannon Nelson7f2b2912007-10-18 03:07:14 -07001407 if (cookie < 0) {
1408 dev_err(&device->pdev->dev,
1409 "Self-test setup failed, disabling\n");
1410 err = -ENODEV;
1411 goto free_resources;
1412 }
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001413 device->common.device_issue_pending(dma_chan);
Dan Williams532d3b12008-12-03 17:16:55 -07001414
Dan Williams0c33e1c2009-03-02 13:31:35 -07001415 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
Chris Leech0bbd5f42006-05-23 17:35:34 -07001416
Dan Williams0c33e1c2009-03-02 13:31:35 -07001417 if (tmo == 0 ||
1418 device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL)
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001419 != DMA_SUCCESS) {
Shannon Nelson43d6e362007-10-16 01:27:39 -07001420 dev_err(&device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001421 "Self-test copy timed out, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -07001422 err = -ENODEV;
1423 goto free_resources;
1424 }
1425 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
Shannon Nelson43d6e362007-10-16 01:27:39 -07001426 dev_err(&device->pdev->dev,
Shannon Nelson5149fd02007-10-18 03:07:13 -07001427 "Self-test copy failed compare, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -07001428 err = -ENODEV;
1429 goto free_resources;
1430 }
1431
1432free_resources:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001433 device->common.device_free_chan_resources(dma_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001434out:
1435 kfree(src);
1436 kfree(dest);
1437 return err;
1438}
1439
Shannon Nelson3e037452007-10-16 01:27:40 -07001440static char ioat_interrupt_style[32] = "msix";
1441module_param_string(ioat_interrupt_style, ioat_interrupt_style,
1442 sizeof(ioat_interrupt_style), 0644);
1443MODULE_PARM_DESC(ioat_interrupt_style,
1444 "set ioat interrupt style: msix (default), "
1445 "msix-single-vector, msi, intx)");
1446
1447/**
1448 * ioat_dma_setup_interrupts - setup interrupt handler
1449 * @device: ioat device
1450 */
1451static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
1452{
1453 struct ioat_dma_chan *ioat_chan;
Dan Williamse6c0b692009-09-08 17:29:44 -07001454 struct pci_dev *pdev = device->pdev;
1455 struct device *dev = &pdev->dev;
1456 struct msix_entry *msix;
1457 int i, j, msixcnt;
1458 int err = -EINVAL;
Shannon Nelson3e037452007-10-16 01:27:40 -07001459 u8 intrctrl = 0;
1460
1461 if (!strcmp(ioat_interrupt_style, "msix"))
1462 goto msix;
1463 if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
1464 goto msix_single_vector;
1465 if (!strcmp(ioat_interrupt_style, "msi"))
1466 goto msi;
1467 if (!strcmp(ioat_interrupt_style, "intx"))
1468 goto intx;
Dan Williamse6c0b692009-09-08 17:29:44 -07001469 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
Shannon Nelson5149fd02007-10-18 03:07:13 -07001470 goto err_no_irq;
Shannon Nelson3e037452007-10-16 01:27:40 -07001471
1472msix:
1473 /* The number of MSI-X vectors should equal the number of channels */
1474 msixcnt = device->common.chancnt;
1475 for (i = 0; i < msixcnt; i++)
1476 device->msix_entries[i].entry = i;
1477
Dan Williamse6c0b692009-09-08 17:29:44 -07001478 err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
Shannon Nelson3e037452007-10-16 01:27:40 -07001479 if (err < 0)
1480 goto msi;
1481 if (err > 0)
1482 goto msix_single_vector;
1483
1484 for (i = 0; i < msixcnt; i++) {
Dan Williamse6c0b692009-09-08 17:29:44 -07001485 msix = &device->msix_entries[i];
Shannon Nelson3e037452007-10-16 01:27:40 -07001486 ioat_chan = ioat_lookup_chan_by_index(device, i);
Dan Williamse6c0b692009-09-08 17:29:44 -07001487 err = devm_request_irq(dev, msix->vector,
1488 ioat_dma_do_interrupt_msix, 0,
1489 "ioat-msix", ioat_chan);
Shannon Nelson3e037452007-10-16 01:27:40 -07001490 if (err) {
1491 for (j = 0; j < i; j++) {
Dan Williamse6c0b692009-09-08 17:29:44 -07001492 msix = &device->msix_entries[j];
Shannon Nelson3e037452007-10-16 01:27:40 -07001493 ioat_chan =
1494 ioat_lookup_chan_by_index(device, j);
Dan Williamse6c0b692009-09-08 17:29:44 -07001495 devm_free_irq(dev, msix->vector, ioat_chan);
Shannon Nelson3e037452007-10-16 01:27:40 -07001496 }
1497 goto msix_single_vector;
1498 }
1499 }
1500 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
Shannon Nelson3e037452007-10-16 01:27:40 -07001501 goto done;
1502
1503msix_single_vector:
Dan Williamse6c0b692009-09-08 17:29:44 -07001504 msix = &device->msix_entries[0];
1505 msix->entry = 0;
1506 err = pci_enable_msix(pdev, device->msix_entries, 1);
Shannon Nelson3e037452007-10-16 01:27:40 -07001507 if (err)
1508 goto msi;
1509
Dan Williamse6c0b692009-09-08 17:29:44 -07001510 err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
1511 "ioat-msix", device);
Shannon Nelson3e037452007-10-16 01:27:40 -07001512 if (err) {
Dan Williamse6c0b692009-09-08 17:29:44 -07001513 pci_disable_msix(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -07001514 goto msi;
1515 }
Shannon Nelson3e037452007-10-16 01:27:40 -07001516 goto done;
1517
1518msi:
Dan Williamse6c0b692009-09-08 17:29:44 -07001519 err = pci_enable_msi(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -07001520 if (err)
1521 goto intx;
1522
Dan Williamse6c0b692009-09-08 17:29:44 -07001523 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
1524 "ioat-msi", device);
Shannon Nelson3e037452007-10-16 01:27:40 -07001525 if (err) {
Dan Williamse6c0b692009-09-08 17:29:44 -07001526 pci_disable_msi(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -07001527 goto intx;
1528 }
1529 /*
1530 * CB 1.2 devices need a bit set in configuration space to enable MSI
1531 */
1532 if (device->version == IOAT_VER_1_2) {
1533 u32 dmactrl;
Dan Williamse6c0b692009-09-08 17:29:44 -07001534 pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
Shannon Nelson3e037452007-10-16 01:27:40 -07001535 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
Dan Williamse6c0b692009-09-08 17:29:44 -07001536 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
Shannon Nelson3e037452007-10-16 01:27:40 -07001537 }
Shannon Nelson3e037452007-10-16 01:27:40 -07001538 goto done;
1539
1540intx:
Dan Williamse6c0b692009-09-08 17:29:44 -07001541 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
1542 IRQF_SHARED, "ioat-intx", device);
Shannon Nelson3e037452007-10-16 01:27:40 -07001543 if (err)
1544 goto err_no_irq;
Shannon Nelson3e037452007-10-16 01:27:40 -07001545
1546done:
1547 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
1548 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
1549 return 0;
1550
1551err_no_irq:
1552 /* Disable all interrupt generation */
1553 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
Dan Williamse6c0b692009-09-08 17:29:44 -07001554 dev_err(dev, "no usable interrupts\n");
1555 return err;
Shannon Nelson3e037452007-10-16 01:27:40 -07001556}
1557
Dan Williamse6c0b692009-09-08 17:29:44 -07001558static void ioat_disable_interrupts(struct ioatdma_device *device)
Shannon Nelson3e037452007-10-16 01:27:40 -07001559{
Shannon Nelson3e037452007-10-16 01:27:40 -07001560 /* Disable all interrupt generation */
1561 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
Shannon Nelson3e037452007-10-16 01:27:40 -07001562}
1563
Shannon Nelson8ab89562007-10-16 01:27:39 -07001564struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
1565 void __iomem *iobase)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001566{
1567 int err;
Dan Williamse6c0b692009-09-08 17:29:44 -07001568 struct device *dev = &pdev->dev;
Shannon Nelson8ab89562007-10-16 01:27:39 -07001569 struct ioatdma_device *device;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001570
Dan Williamse6c0b692009-09-08 17:29:44 -07001571 device = devm_kzalloc(dev, sizeof(*device), GFP_KERNEL);
1572 if (!device)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001573 err = -ENOMEM;
Shannon Nelson8ab89562007-10-16 01:27:39 -07001574 device->pdev = pdev;
1575 device->reg_base = iobase;
1576 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001577
1578 /* DMA coherent memory pool for DMA descriptor allocations */
1579 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
Shannon Nelson8ab89562007-10-16 01:27:39 -07001580 sizeof(struct ioat_dma_descriptor),
1581 64, 0);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001582 if (!device->dma_pool) {
1583 err = -ENOMEM;
1584 goto err_dma_pool;
1585 }
1586
Shannon Nelson43d6e362007-10-16 01:27:39 -07001587 device->completion_pool = pci_pool_create("completion_pool", pdev,
1588 sizeof(u64), SMP_CACHE_BYTES,
1589 SMP_CACHE_BYTES);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001590 if (!device->completion_pool) {
1591 err = -ENOMEM;
1592 goto err_completion_pool;
1593 }
1594
Chris Leech0bbd5f42006-05-23 17:35:34 -07001595 INIT_LIST_HEAD(&device->common.channels);
Shannon Nelson43d6e362007-10-16 01:27:39 -07001596 ioat_dma_enumerate_channels(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001597
Shannon Nelson43d6e362007-10-16 01:27:39 -07001598 device->common.device_alloc_chan_resources =
1599 ioat_dma_alloc_chan_resources;
1600 device->common.device_free_chan_resources =
1601 ioat_dma_free_chan_resources;
Dan Williams7405f742007-01-02 11:10:43 -07001602 device->common.dev = &pdev->dev;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001603
1604 dma_cap_set(DMA_MEMCPY, device->common.cap_mask);
1605 device->common.device_is_tx_complete = ioat_dma_is_complete;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001606 switch (device->version) {
1607 case IOAT_VER_1_2:
1608 device->common.device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1609 device->common.device_issue_pending =
1610 ioat1_dma_memcpy_issue_pending;
1611 break;
1612 case IOAT_VER_2_0:
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001613 case IOAT_VER_3_0:
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001614 device->common.device_prep_dma_memcpy = ioat2_dma_prep_memcpy;
1615 device->common.device_issue_pending =
1616 ioat2_dma_memcpy_issue_pending;
1617 break;
1618 }
1619
Dan Williamse6c0b692009-09-08 17:29:44 -07001620 dev_err(dev, "Intel(R) I/OAT DMA Engine found,"
Shannon Nelson5149fd02007-10-18 03:07:13 -07001621 " %d channels, device version 0x%02x, driver version %s\n",
1622 device->common.chancnt, device->version, IOAT_DMA_VERSION);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001623
Maciej Sosnowski8b794b12009-02-26 11:04:54 +01001624 if (!device->common.chancnt) {
Dan Williamse6c0b692009-09-08 17:29:44 -07001625 dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: "
Maciej Sosnowski8b794b12009-02-26 11:04:54 +01001626 "zero channels detected\n");
1627 goto err_setup_interrupts;
1628 }
1629
Shannon Nelson3e037452007-10-16 01:27:40 -07001630 err = ioat_dma_setup_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001631 if (err)
Shannon Nelson3e037452007-10-16 01:27:40 -07001632 goto err_setup_interrupts;
Shannon Nelson8ab89562007-10-16 01:27:39 -07001633
Shannon Nelson3e037452007-10-16 01:27:40 -07001634 err = ioat_dma_self_test(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001635 if (err)
1636 goto err_self_test;
1637
Dan Williamse6c0b692009-09-08 17:29:44 -07001638 err = dma_async_device_register(&device->common);
1639 if (err)
1640 goto err_self_test;
Maciej Sosnowski16a37ac2008-07-22 17:30:57 -07001641
Dan Williamse6c0b692009-09-08 17:29:44 -07001642 ioat_set_tcp_copy_break(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001643
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -07001644 if (device->version != IOAT_VER_3_0) {
1645 INIT_DELAYED_WORK(&device->work, ioat_dma_chan_watchdog);
1646 schedule_delayed_work(&device->work,
1647 WATCHDOG_DELAY);
1648 }
Maciej Sosnowski09177e82008-07-22 10:07:33 -07001649
Shannon Nelson8ab89562007-10-16 01:27:39 -07001650 return device;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001651
1652err_self_test:
Dan Williamse6c0b692009-09-08 17:29:44 -07001653 ioat_disable_interrupts(device);
Shannon Nelson3e037452007-10-16 01:27:40 -07001654err_setup_interrupts:
Chris Leech0bbd5f42006-05-23 17:35:34 -07001655 pci_pool_destroy(device->completion_pool);
1656err_completion_pool:
1657 pci_pool_destroy(device->dma_pool);
1658err_dma_pool:
Shannon Nelson8ab89562007-10-16 01:27:39 -07001659 return NULL;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001660}
1661
Shannon Nelson8ab89562007-10-16 01:27:39 -07001662void ioat_dma_remove(struct ioatdma_device *device)
Dan Aloni428ed602007-03-08 09:57:36 -08001663{
Chris Leech0bbd5f42006-05-23 17:35:34 -07001664 struct dma_chan *chan, *_chan;
1665 struct ioat_dma_chan *ioat_chan;
1666
Maciej Sosnowski2b8a6bf2009-02-26 11:05:07 +01001667 if (device->version != IOAT_VER_3_0)
1668 cancel_delayed_work(&device->work);
1669
Dan Williamse6c0b692009-09-08 17:29:44 -07001670 ioat_disable_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001671
Shannon Nelsondfe22992007-10-18 03:07:13 -07001672 dma_async_device_unregister(&device->common);
1673
Chris Leech0bbd5f42006-05-23 17:35:34 -07001674 pci_pool_destroy(device->dma_pool);
1675 pci_pool_destroy(device->completion_pool);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001676
Shannon Nelson43d6e362007-10-16 01:27:39 -07001677 list_for_each_entry_safe(chan, _chan,
1678 &device->common.channels, device_node) {
Chris Leech0bbd5f42006-05-23 17:35:34 -07001679 ioat_chan = to_ioat_chan(chan);
1680 list_del(&chan->device_node);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001681 }
Chris Leech0bbd5f42006-05-23 17:35:34 -07001682}
1683