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review.evervolv.com / android_kernel_oneplus_msm8996 / e94233c287890a4236cfccc1be7d663435dd1aff / . / arch / arm / boot / dts / am33xx.dtsi
blob: d62feb2db3503c705ae6f775e7be7950c711d954 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame^]11#include <dt-bindings/gpio/gpio.h>
12
Florian Vaussardeb33ef62013-06-03 16:12:22 +0200[diff] [blame]13#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]14
15/ {
16 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]17 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]18
19 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]26 d_can0 = &dcan0;
27 d_can1 = &dcan1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]28 };
29
30 cpus {
31 cpu@0 {
32 compatible = "arm,cortex-a8";
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]33
34 /*
35 * To consider voltage drop between PMIC and SoC,
36 * tolerance value is reduced to 2% from 4% and
37 * voltage value is increased as a precaution.
38 */
39 operating-points = <
40 /* kHz uV */
41 720000 1285000
42 600000 1225000
43 500000 1125000
44 275000 1125000
45 >;
46 voltage-tolerance = <2>; /* 2 percentage */
47 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]48 };
49 };
50
51 /*
52 * The soc node represents the soc top level view. It is uses for IPs
53 * that are not memory mapped in the MPU view or for the MPU itself.
54 */
55 soc {
56 compatible = "ti,omap-infra";
57 mpu {
58 compatible = "ti,omap3-mpu";
59 ti,hwmods = "mpu";
60 };
61 };
62
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]63 am33xx_pinmux: pinmux@44e10800 {
64 compatible = "pinctrl-single";
65 reg = <0x44e10800 0x0238>;
66 #address-cells = <1>;
67 #size-cells = <0>;
68 pinctrl-single,register-width = <32>;
69 pinctrl-single,function-mask = <0x7f>;
70 };
71
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]72 /*
73 * XXX: Use a flat representation of the AM33XX interconnect.
74 * The real AM33XX interconnect network is quite complex.Since
75 * that will not bring real advantage to represent that in DT
76 * for the moment, just use a fake OCP bus entry to represent
77 * the whole bus hierarchy.
78 */
79 ocp {
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 ranges;
84 ti,hwmods = "l3_main";
85
86 intc: interrupt-controller@48200000 {
87 compatible = "ti,omap2-intc";
88 interrupt-controller;
89 #interrupt-cells = <1>;
90 ti,intc-size = <128>;
91 reg = <0x48200000 0x1000>;
92 };
93
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]94 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]95 compatible = "ti,omap4-gpio";
96 ti,hwmods = "gpio1";
97 gpio-controller;
98 #gpio-cells = <2>;
99 interrupt-controller;
100 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]101 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]102 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]103 };
104
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]105 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]106 compatible = "ti,omap4-gpio";
107 ti,hwmods = "gpio2";
108 gpio-controller;
109 #gpio-cells = <2>;
110 interrupt-controller;
111 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]112 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]113 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]114 };
115
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]116 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]117 compatible = "ti,omap4-gpio";
118 ti,hwmods = "gpio3";
119 gpio-controller;
120 #gpio-cells = <2>;
121 interrupt-controller;
122 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]123 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]124 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]125 };
126
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]127 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]128 compatible = "ti,omap4-gpio";
129 ti,hwmods = "gpio4";
130 gpio-controller;
131 #gpio-cells = <2>;
132 interrupt-controller;
133 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]134 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]135 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]136 };
137
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]138 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]139 compatible = "ti,omap3-uart";
140 ti,hwmods = "uart1";
141 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]142 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]143 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]144 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]145 };
146
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]147 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]148 compatible = "ti,omap3-uart";
149 ti,hwmods = "uart2";
150 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]151 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]152 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]153 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]154 };
155
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]156 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]157 compatible = "ti,omap3-uart";
158 ti,hwmods = "uart3";
159 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]160 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]161 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]162 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]163 };
164
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]165 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]166 compatible = "ti,omap3-uart";
167 ti,hwmods = "uart4";
168 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]169 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]170 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]171 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]172 };
173
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]174 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]175 compatible = "ti,omap3-uart";
176 ti,hwmods = "uart5";
177 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]178 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]179 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]180 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]181 };
182
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]183 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]184 compatible = "ti,omap3-uart";
185 ti,hwmods = "uart6";
186 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]187 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]188 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]189 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]190 };
191
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]192 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]193 compatible = "ti,omap4-i2c";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]197 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]198 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]199 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]200 };
201
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]202 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]203 compatible = "ti,omap4-i2c";
204 #address-cells = <1>;
205 #size-cells = <0>;
206 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]207 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]208 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]209 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]210 };
211
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]212 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]213 compatible = "ti,omap4-i2c";
214 #address-cells = <1>;
215 #size-cells = <0>;
216 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]217 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]218 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]219 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]220 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]221
222 wdt2: wdt@44e35000 {
223 compatible = "ti,omap3-wdt";
224 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]225 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]226 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]227 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]228
229 dcan0: d_can@481cc000 {
230 compatible = "bosch,d_can";
231 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]232 reg = <0x481cc000 0x2000
233 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]234 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]235 status = "disabled";
236 };
237
238 dcan1: d_can@481d0000 {
239 compatible = "bosch,d_can";
240 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]241 reg = <0x481d0000 0x2000
242 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]243 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]244 status = "disabled";
245 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]246
247 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]248 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]249 reg = <0x44e31000 0x400>;
250 interrupts = <67>;
251 ti,hwmods = "timer1";
252 ti,timer-alwon;
253 };
254
255 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]256 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]257 reg = <0x48040000 0x400>;
258 interrupts = <68>;
259 ti,hwmods = "timer2";
260 };
261
262 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]263 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]264 reg = <0x48042000 0x400>;
265 interrupts = <69>;
266 ti,hwmods = "timer3";
267 };
268
269 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]270 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]271 reg = <0x48044000 0x400>;
272 interrupts = <92>;
273 ti,hwmods = "timer4";
274 ti,timer-pwm;
275 };
276
277 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]278 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]279 reg = <0x48046000 0x400>;
280 interrupts = <93>;
281 ti,hwmods = "timer5";
282 ti,timer-pwm;
283 };
284
285 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]286 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]287 reg = <0x48048000 0x400>;
288 interrupts = <94>;
289 ti,hwmods = "timer6";
290 ti,timer-pwm;
291 };
292
293 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]294 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]295 reg = <0x4804a000 0x400>;
296 interrupts = <95>;
297 ti,hwmods = "timer7";
298 ti,timer-pwm;
299 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]300
301 rtc@44e3e000 {
302 compatible = "ti,da830-rtc";
303 reg = <0x44e3e000 0x1000>;
304 interrupts = <75
305 76>;
306 ti,hwmods = "rtc";
307 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]308
309 spi0: spi@48030000 {
310 compatible = "ti,omap4-mcspi";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]314 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]315 ti,spi-num-cs = <2>;
316 ti,hwmods = "spi0";
317 status = "disabled";
318 };
319
320 spi1: spi@481a0000 {
321 compatible = "ti,omap4-mcspi";
322 #address-cells = <1>;
323 #size-cells = <0>;
324 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]325 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]326 ti,spi-num-cs = <2>;
327 ti,hwmods = "spi1";
328 status = "disabled";
329 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]330
331 usb@47400000 {
332 compatible = "ti,musb-am33xx";
333 reg = <0x47400000 0x1000 /* usbss */
334 0x47401000 0x800 /* musb instance 0 */
335 0x47401800 0x800>; /* musb instance 1 */
336 interrupts = <17 /* usbss */
337 18 /* musb instance 0 */
338 19>; /* musb instance 1 */
339 multipoint = <1>;
340 num-eps = <16>;
341 ram-bits = <12>;
342 port0-mode = <3>;
343 port1-mode = <3>;
344 power = <250>;
345 ti,hwmods = "usb_otg_hs";
346 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]347
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]348 mac: ethernet@4a100000 {
349 compatible = "ti,cpsw";
350 ti,hwmods = "cpgmac0";
351 cpdma_channels = <8>;
352 ale_entries = <1024>;
353 bd_ram_size = <0x2000>;
354 no_bd_ram = <0>;
355 rx_descs = <64>;
356 mac_control = <0x20>;
357 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]358 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]359 cpts_clock_mult = <0x80000000>;
360 cpts_clock_shift = <29>;
361 reg = <0x4a100000 0x800
362 0x4a101200 0x100>;
363 #address-cells = <1>;
364 #size-cells = <1>;
365 interrupt-parent = <&intc>;
366 /*
367 * c0_rx_thresh_pend
368 * c0_rx_pend
369 * c0_tx_pend
370 * c0_misc_pend
371 */
372 interrupts = <40 41 42 43>;
373 ranges;
374
375 davinci_mdio: mdio@4a101000 {
376 compatible = "ti,davinci_mdio";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 ti,hwmods = "davinci_mdio";
380 bus_freq = <1000000>;
381 reg = <0x4a101000 0x100>;
382 };
383
384 cpsw_emac0: slave@4a100200 {
385 /* Filled in by U-Boot */
386 mac-address = [ 00 00 00 00 00 00 ];
387 };
388
389 cpsw_emac1: slave@4a100300 {
390 /* Filled in by U-Boot */
391 mac-address = [ 00 00 00 00 00 00 ];
392 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]393 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]394
395 ocmcram: ocmcram@40300000 {
396 compatible = "ti,am3352-ocmcram";
397 reg = <0x40300000 0x10000>;
398 ti,hwmods = "ocmcram";
399 ti,no_idle_on_suspend;
400 };
401
402 wkup_m3: wkup_m3@44d00000 {
403 compatible = "ti,am3353-wkup-m3";
404 reg = <0x44d00000 0x4000 /* M3 UMEM */
405 0x44d80000 0x2000>; /* M3 DMEM */
406 ti,hwmods = "wkup_m3";
407 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]408
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]409 elm: elm@48080000 {
410 compatible = "ti,am3352-elm";
411 reg = <0x48080000 0x2000>;
412 interrupts = <4>;
413 ti,hwmods = "elm";
414 status = "disabled";
415 };
416
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]417 gpmc: gpmc@50000000 {
418 compatible = "ti,am3352-gpmc";
419 ti,hwmods = "gpmc";
420 reg = <0x50000000 0x2000>;
421 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]422 gpmc,num-cs = <7>;
423 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]424 #address-cells = <2>;
425 #size-cells = <1>;
426 status = "disabled";
427 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]428 };
429};