Blame - drivers/scsi/qla2xxx/qla_dbg.c - android_kernel_oneplus_msm8996

blob: 2bf02147bcced4541d3c70b32d6e7eeb82ba7a81 [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Saurav Kashyap	1e63395	2013-02-08 01:57:54 -0500	[diff] [blame]	3	* Copyright (c) 2003-2013 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Chad Dupuis	8d93f55	2013-01-30 03:34:37 -0500	[diff] [blame]	14	* \| Module Init and Probe \| 0x0126 \| 0x4b,0xba,0xfa \|
Joe Carnuccio	fe52f6e	2013-02-08 01:58:03 -0500	[diff] [blame]	15	* \| Mailbox commands \| 0x115b \| 0x111a-0x111b \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	16	* \| \| \| 0x112c-0x112e \|
Andrew Vasquez	af11f64	2012-02-09 11:15:43 -0800	[diff] [blame]	17	* \| \| \| 0x113a \|
Joe Carnuccio	e9f4f41	2013-03-25 02:21:36 -0400	[diff] [blame^]	18	* \| \| \| 0x1155-0x1158 \|
Saurav Kashyap	2a8593f	2012-08-22 14:21:27 -0400	[diff] [blame]	19	* \| Device Discovery \| 0x2087 \| 0x2020-0x2022, \|
				20	* \| \| \| 0x2016 \|
Chad Dupuis	3c290d0	2013-01-30 03:34:38 -0500	[diff] [blame]	21	* \| Queue Command and IO tracing \| 0x3031 \| 0x3006-0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	22	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	23	* \| \| \| 0x302d-0x302e \|
Chad Dupuis	8fcd6b8	2012-08-22 14:21:06 -0400	[diff] [blame]	24	* \| DPC Thread \| 0x401d \| 0x4002,0x4013 \|
Saurav Kashyap	8117877	2012-08-22 14:21:04 -0400	[diff] [blame]	25	* \| Async Events \| 0x5071 \| 0x502b-0x502f \|
Giridhar Malavali	9ba56b9	2012-02-09 11:15:36 -0800	[diff] [blame]	26	* \| \| \| 0x5047,0x5052 \|
Giridhar Malavali	5988aeb	2012-05-15 14:34:12 -0400	[diff] [blame]	27	* \| Timer Routines \| 0x6011 \| \|
Chad Dupuis	1bcc46c	2013-02-08 01:57:46 -0500	[diff] [blame]	28	* \| User Space Interactions \| 0x70c4 \| 0x7018,0x702e, \|
Saurav Kashyap	78d56df	2013-01-30 03:34:42 -0500	[diff] [blame]	29	* \| \| \| 0x7020,0x7024, \|
Joe Carnuccio	733a95b	2012-02-09 11:15:55 -0800	[diff] [blame]	30	* \| \| \| 0x7039,0x7045, \|
				31	* \| \| \| 0x7073-0x7075, \|
Saurav Kashyap	a9b6f72	2012-08-22 14:21:01 -0400	[diff] [blame]	32	* \| \| \| 0x708c, \|
				33	* \| \| \| 0x70a5,0x70a6, \|
				34	* \| \| \| 0x70a8,0x70ab, \|
				35	* \| \| \| 0x70ad-0x70ae \|
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	36	* \| Task Management \| 0x803c \| 0x8025-0x8026 \|
				37	* \| \| \| 0x800b,0x8039 \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	38	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	39	* \| Virtual Port \| 0xa007 \| \|
Saurav Kashyap	6c31555	2013-02-08 01:57:53 -0500	[diff] [blame]	40	* \| ISP82XX Specific \| 0xb086 \| 0xb002,0xb024 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	41	* \| MultiQ \| 0xc00c \| \|
				42	* \| Misc \| 0xd010 \| \|
Arun Easi	33c36c0	2013-01-30 03:34:41 -0500	[diff] [blame]	43	* \| Target Mode \| 0xe070 \| \|
Arun Easi	aa230bc	2013-01-30 03:34:39 -0500	[diff] [blame]	44	* \| Target Mode Management \| 0xf072 \| \|
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	45	* \| Target Mode Task Management \| 0x1000b \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	46	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	47	*/
				48
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	49	#include "qla_def.h"
				50
				51	#include <linux/delay.h>
				52
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	53	static uint32_t ql_dbg_offset = 0x800;
				54
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	55	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	56	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	57	{
				58	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				59	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				60	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				61	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				62
				63	fw_dump->vendor = htonl(ha->pdev->vendor);
				64	fw_dump->device = htonl(ha->pdev->device);
				65	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				66	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				67	}
				68
				69	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	70	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	71	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	72	struct req_que *req = ha->req_q_map[0];
				73	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	74	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	75	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	76	sizeof(request_t));
				77
				78	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	79	ptr += req->length * sizeof(request_t);
				80	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	81	sizeof(response_t));
				82
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	83	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	84	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	85
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	86	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	87	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	88	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	89	{
				90	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	91	uint32_t cnt, stat, timer, dwords, idx;
				92	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	93	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	94	dma_addr_t dump_dma = ha->gid_list_dma;
				95	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	96
				97	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	98	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	99
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	100	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	101	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				102
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	103	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	104	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				105	cnt += dwords, addr += dwords) {
				106	if (cnt + dwords > ram_dwords)
				107	dwords = ram_dwords - cnt;
				108
				109	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				110	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				111
				112	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				113	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				114	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				115	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				116
				117	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				118	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	119	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				120
				121	for (timer = 6000000; timer; timer--) {
				122	/* Check for pending interrupts. */
				123	stat = RD_REG_DWORD(&reg->host_status);
				124	if (stat & HSRX_RISC_INT) {
				125	stat &= 0xff;
				126
				127	if (stat == 0x1 \|\| stat == 0x2 \|\|
				128	stat == 0x10 \|\| stat == 0x11) {
				129	set_bit(MBX_INTERRUPT,
				130	&ha->mbx_cmd_flags);
				131
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	132	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	133
				134	WRT_REG_DWORD(&reg->hccr,
				135	HCCRX_CLR_RISC_INT);
				136	RD_REG_DWORD(&reg->hccr);
				137	break;
				138	}
				139
				140	/* Clear this intr; it wasn't a mailbox intr */
				141	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				142	RD_REG_DWORD(&reg->hccr);
				143	}
				144	udelay(5);
				145	}
				146
				147	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	148	rval = mb0 & MBS_MASK;
				149	for (idx = 0; idx < dwords; idx++)
				150	ram[cnt + idx] = swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	151	} else {
				152	rval = QLA_FUNCTION_FAILED;
				153	}
				154	}
				155
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	156	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	157	return rval;
				158	}
				159
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	160	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	161	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	162	uint32_t cram_size, void **nxt)
				163	{
				164	int rval;
				165
				166	/* Code RAM. */
				167	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				168	if (rval != QLA_SUCCESS)
				169	return rval;
				170
				171	/* External Memory. */
				172	return qla24xx_dump_ram(ha, 0x100000, *nxt,
				173	ha->fw_memory_size - 0x100000 + 1, nxt);
				174	}
				175
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	176	static uint32_t *
				177	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				178	uint32_t count, uint32_t *buf)
				179	{
				180	uint32_t __iomem *dmp_reg;
				181
				182	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				183	dmp_reg = &reg->iobase_window;
				184	while (count--)
				185	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				186
				187	return buf;
				188	}
				189
				190	static inline int
				191	qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
				192	{
				193	int rval = QLA_SUCCESS;
				194	uint32_t cnt;
				195
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	196	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	aed1088	2009-06-03 09:55:26 -0700	[diff] [blame]	197	for (cnt = 30000;
				198	((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	199	rval == QLA_SUCCESS; cnt--) {
				200	if (cnt)
				201	udelay(100);
				202	else
				203	rval = QLA_FUNCTION_TIMEOUT;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	204	}
				205
				206	return rval;
				207	}
				208
				209	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	210	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	211	{
				212	int rval = QLA_SUCCESS;
				213	uint32_t cnt;
				214	uint16_t mb0, wd;
				215	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				216
				217	/* Reset RISC. */
				218	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				219	for (cnt = 0; cnt < 30000; cnt++) {
				220	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				221	break;
				222
				223	udelay(10);
				224	}
				225
				226	WRT_REG_DWORD(&reg->ctrl_status,
				227	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				228	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				229
				230	udelay(100);
				231	/* Wait for firmware to complete NVRAM accesses. */
				232	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				233	for (cnt = 10000 ; cnt && mb0; cnt--) {
				234	udelay(5);
				235	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				236	barrier();
				237	}
				238
				239	/* Wait for soft-reset to complete. */
				240	for (cnt = 0; cnt < 30000; cnt++) {
				241	if ((RD_REG_DWORD(&reg->ctrl_status) &
				242	CSRX_ISP_SOFT_RESET) == 0)
				243	break;
				244
				245	udelay(10);
				246	}
				247	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				248	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				249
				250	for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
				251	rval == QLA_SUCCESS; cnt--) {
				252	if (cnt)
				253	udelay(100);
				254	else
				255	rval = QLA_FUNCTION_TIMEOUT;
				256	}
				257
				258	return rval;
				259	}
				260
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	261	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	262	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	263	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	264	{
				265	int rval;
				266	uint32_t cnt, stat, timer, words, idx;
				267	uint16_t mb0;
				268	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				269	dma_addr_t dump_dma = ha->gid_list_dma;
				270	uint16_t dump = (uint16_t )ha->gid_list;
				271
				272	rval = QLA_SUCCESS;
				273	mb0 = 0;
				274
				275	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				276	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				277
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	278	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	279	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				280	cnt += words, addr += words) {
				281	if (cnt + words > ram_words)
				282	words = ram_words - cnt;
				283
				284	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				285	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				286
				287	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				288	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				289	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				290	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				291
				292	WRT_MAILBOX_REG(ha, reg, 4, words);
				293	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				294
				295	for (timer = 6000000; timer; timer--) {
				296	/* Check for pending interrupts. */
				297	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				298	if (stat & HSR_RISC_INT) {
				299	stat &= 0xff;
				300
				301	if (stat == 0x1 \|\| stat == 0x2) {
				302	set_bit(MBX_INTERRUPT,
				303	&ha->mbx_cmd_flags);
				304
				305	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				306
				307	/* Release mailbox registers. */
				308	WRT_REG_WORD(&reg->semaphore, 0);
				309	WRT_REG_WORD(&reg->hccr,
				310	HCCR_CLR_RISC_INT);
				311	RD_REG_WORD(&reg->hccr);
				312	break;
				313	} else if (stat == 0x10 \|\| stat == 0x11) {
				314	set_bit(MBX_INTERRUPT,
				315	&ha->mbx_cmd_flags);
				316
				317	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				318
				319	WRT_REG_WORD(&reg->hccr,
				320	HCCR_CLR_RISC_INT);
				321	RD_REG_WORD(&reg->hccr);
				322	break;
				323	}
				324
				325	/* clear this intr; it wasn't a mailbox intr */
				326	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				327	RD_REG_WORD(&reg->hccr);
				328	}
				329	udelay(5);
				330	}
				331
				332	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				333	rval = mb0 & MBS_MASK;
				334	for (idx = 0; idx < words; idx++)
				335	ram[cnt + idx] = swab16(dump[idx]);
				336	} else {
				337	rval = QLA_FUNCTION_FAILED;
				338	}
				339	}
				340
				341	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				342	return rval;
				343	}
				344
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	345	static inline void
				346	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				347	uint16_t *buf)
				348	{
				349	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				350
				351	while (count--)
				352	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				353	}
				354
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	355	static inline void *
				356	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				357	{
				358	if (!ha->eft)
				359	return ptr;
				360
				361	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				362	return ptr + ntohl(ha->fw_dump->eft_size);
				363	}
				364
				365	static inline void *
				366	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				367	{
				368	uint32_t cnt;
				369	uint32_t *iter_reg;
				370	struct qla2xxx_fce_chain *fcec = ptr;
				371
				372	if (!ha->fce)
				373	return ptr;
				374
				375	*last_chain = &fcec->type;
				376	fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
				377	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				378	fce_calc_size(ha->fce_bufs));
				379	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				380	fcec->addr_l = htonl(LSD(ha->fce_dma));
				381	fcec->addr_h = htonl(MSD(ha->fce_dma));
				382
				383	iter_reg = fcec->eregs;
				384	for (cnt = 0; cnt < 8; cnt++)
				385	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				386
				387	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				388
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	389	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	390	}
				391
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	392	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	393	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				394	uint32_t **last_chain)
				395	{
				396	struct qla2xxx_mqueue_chain *q;
				397	struct qla2xxx_mqueue_header *qh;
				398	uint32_t num_queues;
				399	int que;
				400	struct {
				401	int length;
				402	void *ring;
				403	} aq, *aqp;
				404
				405	if (!ha->tgt.atio_q_length)
				406	return ptr;
				407
				408	num_queues = 1;
				409	aqp = &aq;
				410	aqp->length = ha->tgt.atio_q_length;
				411	aqp->ring = ha->tgt.atio_ring;
				412
				413	for (que = 0; que < num_queues; que++) {
				414	/* aqp = ha->atio_q_map[que]; */
				415	q = ptr;
				416	*last_chain = &q->type;
				417	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				418	q->chain_size = htonl(
				419	sizeof(struct qla2xxx_mqueue_chain) +
				420	sizeof(struct qla2xxx_mqueue_header) +
				421	(aqp->length * sizeof(request_t)));
				422	ptr += sizeof(struct qla2xxx_mqueue_chain);
				423
				424	/* Add header. */
				425	qh = ptr;
				426	qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
				427	qh->number = htonl(que);
				428	qh->size = htonl(aqp->length * sizeof(request_t));
				429	ptr += sizeof(struct qla2xxx_mqueue_header);
				430
				431	/* Add data. */
				432	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				433
				434	ptr += aqp->length * sizeof(request_t);
				435	}
				436
				437	return ptr;
				438	}
				439
				440	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	441	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				442	{
				443	struct qla2xxx_mqueue_chain *q;
				444	struct qla2xxx_mqueue_header *qh;
				445	struct req_que *req;
				446	struct rsp_que *rsp;
				447	int que;
				448
				449	if (!ha->mqenable)
				450	return ptr;
				451
				452	/* Request queues */
				453	for (que = 1; que < ha->max_req_queues; que++) {
				454	req = ha->req_q_map[que];
				455	if (!req)
				456	break;
				457
				458	/* Add chain. */
				459	q = ptr;
				460	*last_chain = &q->type;
				461	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				462	q->chain_size = htonl(
				463	sizeof(struct qla2xxx_mqueue_chain) +
				464	sizeof(struct qla2xxx_mqueue_header) +
				465	(req->length * sizeof(request_t)));
				466	ptr += sizeof(struct qla2xxx_mqueue_chain);
				467
				468	/* Add header. */
				469	qh = ptr;
				470	qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
				471	qh->number = htonl(que);
				472	qh->size = htonl(req->length * sizeof(request_t));
				473	ptr += sizeof(struct qla2xxx_mqueue_header);
				474
				475	/* Add data. */
				476	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				477	ptr += req->length * sizeof(request_t);
				478	}
				479
				480	/* Response queues */
				481	for (que = 1; que < ha->max_rsp_queues; que++) {
				482	rsp = ha->rsp_q_map[que];
				483	if (!rsp)
				484	break;
				485
				486	/* Add chain. */
				487	q = ptr;
				488	*last_chain = &q->type;
				489	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				490	q->chain_size = htonl(
				491	sizeof(struct qla2xxx_mqueue_chain) +
				492	sizeof(struct qla2xxx_mqueue_header) +
				493	(rsp->length * sizeof(response_t)));
				494	ptr += sizeof(struct qla2xxx_mqueue_chain);
				495
				496	/* Add header. */
				497	qh = ptr;
				498	qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
				499	qh->number = htonl(que);
				500	qh->size = htonl(rsp->length * sizeof(response_t));
				501	ptr += sizeof(struct qla2xxx_mqueue_header);
				502
				503	/* Add data. */
				504	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				505	ptr += rsp->length * sizeof(response_t);
				506	}
				507
				508	return ptr;
				509	}
				510
				511	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	512	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				513	{
				514	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	515	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	516	struct qla2xxx_mq_chain *mq = ptr;
				517	struct device_reg_25xxmq __iomem *reg;
				518
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	519	if (!ha->mqenable \|\| IS_QLA83XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	520	return ptr;
				521
				522	mq = ptr;
				523	*last_chain = &mq->type;
				524	mq->type = __constant_htonl(DUMP_CHAIN_MQ);
				525	mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
				526
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	527	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				528	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	529	mq->count = htonl(que_cnt);
				530	for (cnt = 0; cnt < que_cnt; cnt++) {
Saurav Kashyap	fa49263	2012-11-21 02:40:29 -0500	[diff] [blame]	531	reg = (struct device_reg_25xxmq __iomem *)
				532	(ha->mqiobase + cnt * QLA_QUE_PAGE);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	533	que_idx = cnt * 4;
				534	mq->qregs[que_idx] = htonl(RD_REG_DWORD(&reg->req_q_in));
				535	mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(&reg->req_q_out));
				536	mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(&reg->rsp_q_in));
				537	mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(&reg->rsp_q_out));
				538	}
				539
				540	return ptr + sizeof(struct qla2xxx_mq_chain);
				541	}
				542
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	543	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	544	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				545	{
				546	struct qla_hw_data *ha = vha->hw;
				547
				548	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	549	ql_log(ql_log_warn, vha, 0xd000,
				550	"Failed to dump firmware (%x).\n", rval);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	551	ha->fw_dumped = 0;
				552	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	553	ql_log(ql_log_info, vha, 0xd001,
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	554	"Firmware dump saved to temp buffer (%ld/%p).\n",
				555	vha->host_no, ha->fw_dump);
				556	ha->fw_dumped = 1;
				557	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				558	}
				559	}
				560
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	561	/**
				562	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				563	* @ha: HA context
				564	* @hardware_locked: Called with the hardware_lock
				565	*/
				566	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	567	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	568	{
				569	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	570	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	571	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	572	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	573	uint16_t __iomem *dmp_reg;
				574	unsigned long flags;
				575	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	576	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	577	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	578
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	579	flags = 0;
				580
				581	if (!hardware_locked)
				582	spin_lock_irqsave(&ha->hardware_lock, flags);
				583
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	584	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	585	ql_log(ql_log_warn, vha, 0xd002,
				586	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	587	goto qla2300_fw_dump_failed;
				588	}
				589
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	590	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	591	ql_log(ql_log_warn, vha, 0xd003,
				592	"Firmware has been previously dumped (%p) "
				593	"-- ignoring request.\n",
				594	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	595	goto qla2300_fw_dump_failed;
				596	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	597	fw = &ha->fw_dump->isp.isp23;
				598	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	599
				600	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	601	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	602
				603	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	604	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	605	if (IS_QLA2300(ha)) {
				606	for (cnt = 30000;
				607	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				608	rval == QLA_SUCCESS; cnt--) {
				609	if (cnt)
				610	udelay(100);
				611	else
				612	rval = QLA_FUNCTION_TIMEOUT;
				613	}
				614	} else {
				615	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				616	udelay(10);
				617	}
				618
				619	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	620	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	621	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	622	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	623
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	624	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	625	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	626	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	627
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	628	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	629	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	630	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	631
				632	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	633	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	634
				635	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	636	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	637
				638	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	639	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	640	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	641	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	642
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	643	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	644	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	645
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	646	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	647	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	648
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	649	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	650	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	651
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	652	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	653	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	654
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	655	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	656	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	657
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	658	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	659	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	660
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	661	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	662	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	663
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	664	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	665	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	666
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	667	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	668	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	669
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	670	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	671	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	672
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	673	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	674	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	675
				676	/* Reset RISC. */
				677	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				678	for (cnt = 0; cnt < 30000; cnt++) {
				679	if ((RD_REG_WORD(&reg->ctrl_status) &
				680	CSR_ISP_SOFT_RESET) == 0)
				681	break;
				682
				683	udelay(10);
				684	}
				685	}
				686
				687	if (!IS_QLA2300(ha)) {
				688	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				689	rval == QLA_SUCCESS; cnt--) {
				690	if (cnt)
				691	udelay(100);
				692	else
				693	rval = QLA_FUNCTION_TIMEOUT;
				694	}
				695	}
				696
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	697	/* Get RISC SRAM. */
				698	if (rval == QLA_SUCCESS)
				699	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				700	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	701
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	702	/* Get stack SRAM. */
				703	if (rval == QLA_SUCCESS)
				704	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				705	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	706
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	707	/* Get data SRAM. */
				708	if (rval == QLA_SUCCESS)
				709	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				710	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	711
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	712	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	713	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	714
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	715	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	716
				717	qla2300_fw_dump_failed:
				718	if (!hardware_locked)
				719	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				720	}
				721
				722	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	723	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				724	* @ha: HA context
				725	* @hardware_locked: Called with the hardware_lock
				726	*/
				727	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	728	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	729	{
				730	int rval;
				731	uint32_t cnt, timer;
				732	uint16_t risc_address;
				733	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	734	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	735	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	736	uint16_t __iomem *dmp_reg;
				737	unsigned long flags;
				738	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	739	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	740
				741	risc_address = 0;
				742	mb0 = mb2 = 0;
				743	flags = 0;
				744
				745	if (!hardware_locked)
				746	spin_lock_irqsave(&ha->hardware_lock, flags);
				747
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	748	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	749	ql_log(ql_log_warn, vha, 0xd004,
				750	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	751	goto qla2100_fw_dump_failed;
				752	}
				753
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	754	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	755	ql_log(ql_log_warn, vha, 0xd005,
				756	"Firmware has been previously dumped (%p) "
				757	"-- ignoring request.\n",
				758	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	759	goto qla2100_fw_dump_failed;
				760	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	761	fw = &ha->fw_dump->isp.isp21;
				762	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	763
				764	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	765	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	766
				767	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	768	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	769	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				770	rval == QLA_SUCCESS; cnt--) {
				771	if (cnt)
				772	udelay(100);
				773	else
				774	rval = QLA_FUNCTION_TIMEOUT;
				775	}
				776	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	777	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	778	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	779	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	780
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	781	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	782	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	783	if (cnt == 8)
				784	dmp_reg = &reg->u_end.isp2200.mailbox8;
				785
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	786	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	787	}
				788
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	789	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	790	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	791	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	792
				793	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	794	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	795	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	796	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	797
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	798	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	799	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	800
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	801	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	802	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	803
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	804	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	805	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	806
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	807	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	808	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	809
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	810	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	811	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	812
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	813	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	814	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	815
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	816	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	817	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	818
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	819	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	820	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	821
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	822	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	823	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	824
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	825	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	826	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	827
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	828	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	829	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	830
				831	/* Reset the ISP. */
				832	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				833	}
				834
				835	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				836	rval == QLA_SUCCESS; cnt--) {
				837	if (cnt)
				838	udelay(100);
				839	else
				840	rval = QLA_FUNCTION_TIMEOUT;
				841	}
				842
				843	/* Pause RISC. */
				844	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				845	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				846
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	847	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	848	for (cnt = 30000;
				849	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				850	rval == QLA_SUCCESS; cnt--) {
				851	if (cnt)
				852	udelay(100);
				853	else
				854	rval = QLA_FUNCTION_TIMEOUT;
				855	}
				856	if (rval == QLA_SUCCESS) {
				857	/* Set memory configuration and timing. */
				858	if (IS_QLA2100(ha))
				859	WRT_REG_WORD(&reg->mctr, 0xf1);
				860	else
				861	WRT_REG_WORD(&reg->mctr, 0xf2);
				862	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				863
				864	/* Release RISC. */
				865	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				866	}
				867	}
				868
				869	if (rval == QLA_SUCCESS) {
				870	/* Get RISC SRAM. */
				871	risc_address = 0x1000;
				872	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				873	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				874	}
				875	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				876	cnt++, risc_address++) {
				877	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				878	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				879
				880	for (timer = 6000000; timer != 0; timer--) {
				881	/* Check for pending interrupts. */
				882	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				883	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				884	set_bit(MBX_INTERRUPT,
				885	&ha->mbx_cmd_flags);
				886
				887	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				888	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				889
				890	WRT_REG_WORD(&reg->semaphore, 0);
				891	WRT_REG_WORD(&reg->hccr,
				892	HCCR_CLR_RISC_INT);
				893	RD_REG_WORD(&reg->hccr);
				894	break;
				895	}
				896	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				897	RD_REG_WORD(&reg->hccr);
				898	}
				899	udelay(5);
				900	}
				901
				902	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				903	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	904	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	905	} else {
				906	rval = QLA_FUNCTION_FAILED;
				907	}
				908	}
				909
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	910	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	911	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	912
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	913	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	914
				915	qla2100_fw_dump_failed:
				916	if (!hardware_locked)
				917	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				918	}
				919
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	920	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	921	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	922	{
				923	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	924	uint32_t cnt;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	925	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	926	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	927	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				928	uint32_t __iomem *dmp_reg;
				929	uint32_t *iter_reg;
				930	uint16_t __iomem *mbx_reg;
				931	unsigned long flags;
				932	struct qla24xx_fw_dump *fw;
				933	uint32_t ext_mem_cnt;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	934	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	935	void *nxt_chain;
				936	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	937	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	938
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	939	if (IS_QLA82XX(ha))
				940	return;
				941
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	942	risc_address = ext_mem_cnt = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	943	flags = 0;
				944
				945	if (!hardware_locked)
				946	spin_lock_irqsave(&ha->hardware_lock, flags);
				947
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	948	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	949	ql_log(ql_log_warn, vha, 0xd006,
				950	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	951	goto qla24xx_fw_dump_failed;
				952	}
				953
				954	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	955	ql_log(ql_log_warn, vha, 0xd007,
				956	"Firmware has been previously dumped (%p) "
				957	"-- ignoring request.\n",
				958	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	959	goto qla24xx_fw_dump_failed;
				960	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	961	fw = &ha->fw_dump->isp.isp24;
				962	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	963
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	964	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	965
				966	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	967	rval = qla24xx_pause_risc(reg);
				968	if (rval != QLA_SUCCESS)
				969	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	970
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	971	/* Host interface registers. */
				972	dmp_reg = &reg->flash_addr;
				973	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				974	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	975
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	976	/* Disable interrupts. */
				977	WRT_REG_DWORD(&reg->ictrl, 0);
				978	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	979
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	980	/* Shadow registers. */
				981	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				982	RD_REG_DWORD(&reg->iobase_addr);
				983	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				984	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	985
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	986	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				987	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	988
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	989	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				990	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	991
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	992	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				993	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	994
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	995	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				996	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	997
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	998	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				999	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1000
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1001	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1002	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1003
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1004	/* Mailbox registers. */
				1005	mbx_reg = &reg->mailbox0;
				1006	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1007	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1008
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1009	/* Transfer sequence registers. */
				1010	iter_reg = fw->xseq_gp_reg;
				1011	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1012	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1013	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1014	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1015	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1016	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1017	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1018	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1019
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1020	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1021	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1022
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1023	/* Receive sequence registers. */
				1024	iter_reg = fw->rseq_gp_reg;
				1025	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1026	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1027	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1028	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1029	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1030	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1031	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1032	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1033
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1034	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1035	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1036	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1037
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1038	/* Command DMA registers. */
				1039	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1040
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1041	/* Queues. */
				1042	iter_reg = fw->req0_dma_reg;
				1043	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1044	dmp_reg = &reg->iobase_q;
				1045	for (cnt = 0; cnt < 7; cnt++)
				1046	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1047
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1048	iter_reg = fw->resp0_dma_reg;
				1049	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1050	dmp_reg = &reg->iobase_q;
				1051	for (cnt = 0; cnt < 7; cnt++)
				1052	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1053
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1054	iter_reg = fw->req1_dma_reg;
				1055	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1056	dmp_reg = &reg->iobase_q;
				1057	for (cnt = 0; cnt < 7; cnt++)
				1058	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1059
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1060	/* Transmit DMA registers. */
				1061	iter_reg = fw->xmt0_dma_reg;
				1062	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1063	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1064
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1065	iter_reg = fw->xmt1_dma_reg;
				1066	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1067	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1068
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1069	iter_reg = fw->xmt2_dma_reg;
				1070	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1071	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1072
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1073	iter_reg = fw->xmt3_dma_reg;
				1074	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1075	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1076
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1077	iter_reg = fw->xmt4_dma_reg;
				1078	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1079	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1080
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1081	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1082
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1083	/* Receive DMA registers. */
				1084	iter_reg = fw->rcvt0_data_dma_reg;
				1085	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1086	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1087
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1088	iter_reg = fw->rcvt1_data_dma_reg;
				1089	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1090	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1091
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1092	/* RISC registers. */
				1093	iter_reg = fw->risc_gp_reg;
				1094	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1095	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1096	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1097	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1098	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1099	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1100	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1101	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1102
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1103	/* Local memory controller registers. */
				1104	iter_reg = fw->lmc_reg;
				1105	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1106	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1107	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1108	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1109	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1110	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1111	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1112
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1113	/* Fibre Protocol Module registers. */
				1114	iter_reg = fw->fpm_hdw_reg;
				1115	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1116	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1117	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1118	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1119	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1120	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1121	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1122	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1123	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1124	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1125	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1126	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1127
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1128	/* Frame Buffer registers. */
				1129	iter_reg = fw->fb_hdw_reg;
				1130	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1131	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1132	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1133	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1134	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1135	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1136	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1137	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1138	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1139	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1140	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1141
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1142	rval = qla24xx_soft_reset(ha);
				1143	if (rval != QLA_SUCCESS)
				1144	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1145
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1146	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1147	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1148	if (rval != QLA_SUCCESS)
				1149	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1150
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1151	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1152
				1153	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1154
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1155	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1156	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1157	if (last_chain) {
				1158	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1159	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1160	}
				1161
				1162	/* Adjust valid length. */
				1163	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1164
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1165	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1166	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1167
				1168	qla24xx_fw_dump_failed:
				1169	if (!hardware_locked)
				1170	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1171	}
				1172
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1173	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1174	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1175	{
				1176	int rval;
				1177	uint32_t cnt;
				1178	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1179	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1180	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1181	uint32_t __iomem *dmp_reg;
				1182	uint32_t *iter_reg;
				1183	uint16_t __iomem *mbx_reg;
				1184	unsigned long flags;
				1185	struct qla25xx_fw_dump *fw;
				1186	uint32_t ext_mem_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1187	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1188	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1189	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1190
				1191	risc_address = ext_mem_cnt = 0;
				1192	flags = 0;
				1193
				1194	if (!hardware_locked)
				1195	spin_lock_irqsave(&ha->hardware_lock, flags);
				1196
				1197	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1198	ql_log(ql_log_warn, vha, 0xd008,
				1199	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1200	goto qla25xx_fw_dump_failed;
				1201	}
				1202
				1203	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1204	ql_log(ql_log_warn, vha, 0xd009,
				1205	"Firmware has been previously dumped (%p) "
				1206	"-- ignoring request.\n",
				1207	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1208	goto qla25xx_fw_dump_failed;
				1209	}
				1210	fw = &ha->fw_dump->isp.isp25;
				1211	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1212	ha->fw_dump->version = __constant_htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1213
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1214	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1215
				1216	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1217	rval = qla24xx_pause_risc(reg);
				1218	if (rval != QLA_SUCCESS)
				1219	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1220
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1221	/* Host/Risc registers. */
				1222	iter_reg = fw->host_risc_reg;
				1223	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1224	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1225
				1226	/* PCIe registers. */
				1227	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1228	RD_REG_DWORD(&reg->iobase_addr);
				1229	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1230	dmp_reg = &reg->iobase_c4;
				1231	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1232	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1233	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1234	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1235
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1236	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1237	RD_REG_DWORD(&reg->iobase_window);
				1238
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1239	/* Host interface registers. */
				1240	dmp_reg = &reg->flash_addr;
				1241	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1242	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1243
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1244	/* Disable interrupts. */
				1245	WRT_REG_DWORD(&reg->ictrl, 0);
				1246	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1247
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1248	/* Shadow registers. */
				1249	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1250	RD_REG_DWORD(&reg->iobase_addr);
				1251	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1252	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1253
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1254	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1255	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1256
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1257	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1258	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1259
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1260	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1261	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1262
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1263	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1264	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1265
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1266	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1267	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1268
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1269	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1270	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1271
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1272	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1273	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1274
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1275	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1276	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1277
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1278	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1279	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1280
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1281	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1282	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1283
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1284	/* RISC I/O register. */
				1285	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1286	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1287
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1288	/* Mailbox registers. */
				1289	mbx_reg = &reg->mailbox0;
				1290	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1291	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1292
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1293	/* Transfer sequence registers. */
				1294	iter_reg = fw->xseq_gp_reg;
				1295	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1296	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1297	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1298	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1299	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1300	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1301	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1302	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1303
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1304	iter_reg = fw->xseq_0_reg;
				1305	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1306	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1307	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1308
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1309	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1310
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1311	/* Receive sequence registers. */
				1312	iter_reg = fw->rseq_gp_reg;
				1313	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1314	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1315	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1316	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1317	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1318	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1319	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1320	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1321
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1322	iter_reg = fw->rseq_0_reg;
				1323	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1324	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1325
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1326	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1327	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1328
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1329	/* Auxiliary sequence registers. */
				1330	iter_reg = fw->aseq_gp_reg;
				1331	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1332	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1333	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1334	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1335	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1336	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1337	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1338	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1339
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1340	iter_reg = fw->aseq_0_reg;
				1341	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1342	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1343
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1344	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1345	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1346
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1347	/* Command DMA registers. */
				1348	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1349
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1350	/* Queues. */
				1351	iter_reg = fw->req0_dma_reg;
				1352	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1353	dmp_reg = &reg->iobase_q;
				1354	for (cnt = 0; cnt < 7; cnt++)
				1355	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1356
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1357	iter_reg = fw->resp0_dma_reg;
				1358	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1359	dmp_reg = &reg->iobase_q;
				1360	for (cnt = 0; cnt < 7; cnt++)
				1361	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1362
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1363	iter_reg = fw->req1_dma_reg;
				1364	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1365	dmp_reg = &reg->iobase_q;
				1366	for (cnt = 0; cnt < 7; cnt++)
				1367	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1368
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1369	/* Transmit DMA registers. */
				1370	iter_reg = fw->xmt0_dma_reg;
				1371	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1372	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1373
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1374	iter_reg = fw->xmt1_dma_reg;
				1375	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1376	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1377
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1378	iter_reg = fw->xmt2_dma_reg;
				1379	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1380	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1381
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1382	iter_reg = fw->xmt3_dma_reg;
				1383	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1384	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1385
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1386	iter_reg = fw->xmt4_dma_reg;
				1387	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1388	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1389
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1390	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1391
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1392	/* Receive DMA registers. */
				1393	iter_reg = fw->rcvt0_data_dma_reg;
				1394	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1395	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1396
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1397	iter_reg = fw->rcvt1_data_dma_reg;
				1398	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1399	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1400
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1401	/* RISC registers. */
				1402	iter_reg = fw->risc_gp_reg;
				1403	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1404	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1405	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1406	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1407	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1408	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1409	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1410	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1411
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1412	/* Local memory controller registers. */
				1413	iter_reg = fw->lmc_reg;
				1414	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1415	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1416	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1417	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1418	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1419	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1420	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1421	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1422
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1423	/* Fibre Protocol Module registers. */
				1424	iter_reg = fw->fpm_hdw_reg;
				1425	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1426	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1427	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1428	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1429	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1430	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1431	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1432	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1433	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1434	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1435	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1436	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1437
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1438	/* Frame Buffer registers. */
				1439	iter_reg = fw->fb_hdw_reg;
				1440	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1441	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1442	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1443	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1444	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1445	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1446	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1447	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1448	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1449	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1450	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1451	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1452
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1453	/* Multi queue registers */
				1454	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1455	&last_chain);
				1456
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1457	rval = qla24xx_soft_reset(ha);
				1458	if (rval != QLA_SUCCESS)
				1459	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1460
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1461	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1462	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1463	if (rval != QLA_SUCCESS)
				1464	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1465
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1466	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1467
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1468	nxt = qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1469
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1470	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1471	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1472	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1473	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1474	if (last_chain) {
				1475	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1476	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1477	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1478
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1479	/* Adjust valid length. */
				1480	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1481
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1482	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1483	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1484
				1485	qla25xx_fw_dump_failed:
				1486	if (!hardware_locked)
				1487	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1488	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1489
				1490	void
				1491	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1492	{
				1493	int rval;
				1494	uint32_t cnt;
				1495	uint32_t risc_address;
				1496	struct qla_hw_data *ha = vha->hw;
				1497	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1498	uint32_t __iomem *dmp_reg;
				1499	uint32_t *iter_reg;
				1500	uint16_t __iomem *mbx_reg;
				1501	unsigned long flags;
				1502	struct qla81xx_fw_dump *fw;
				1503	uint32_t ext_mem_cnt;
				1504	void nxt, nxt_chain;
				1505	uint32_t *last_chain = NULL;
				1506	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1507
				1508	risc_address = ext_mem_cnt = 0;
				1509	flags = 0;
				1510
				1511	if (!hardware_locked)
				1512	spin_lock_irqsave(&ha->hardware_lock, flags);
				1513
				1514	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1515	ql_log(ql_log_warn, vha, 0xd00a,
				1516	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1517	goto qla81xx_fw_dump_failed;
				1518	}
				1519
				1520	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1521	ql_log(ql_log_warn, vha, 0xd00b,
				1522	"Firmware has been previously dumped (%p) "
				1523	"-- ignoring request.\n",
				1524	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1525	goto qla81xx_fw_dump_failed;
				1526	}
				1527	fw = &ha->fw_dump->isp.isp81;
				1528	qla2xxx_prep_dump(ha, ha->fw_dump);
				1529
				1530	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1531
				1532	/* Pause RISC. */
				1533	rval = qla24xx_pause_risc(reg);
				1534	if (rval != QLA_SUCCESS)
				1535	goto qla81xx_fw_dump_failed_0;
				1536
				1537	/* Host/Risc registers. */
				1538	iter_reg = fw->host_risc_reg;
				1539	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1540	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1541
				1542	/* PCIe registers. */
				1543	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1544	RD_REG_DWORD(&reg->iobase_addr);
				1545	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1546	dmp_reg = &reg->iobase_c4;
				1547	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1548	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1549	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1550	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1551
				1552	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1553	RD_REG_DWORD(&reg->iobase_window);
				1554
				1555	/* Host interface registers. */
				1556	dmp_reg = &reg->flash_addr;
				1557	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1558	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1559
				1560	/* Disable interrupts. */
				1561	WRT_REG_DWORD(&reg->ictrl, 0);
				1562	RD_REG_DWORD(&reg->ictrl);
				1563
				1564	/* Shadow registers. */
				1565	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1566	RD_REG_DWORD(&reg->iobase_addr);
				1567	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1568	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1569
				1570	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1571	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1572
				1573	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1574	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1575
				1576	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1577	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1578
				1579	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1580	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1581
				1582	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1583	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1584
				1585	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1586	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1587
				1588	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1589	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1590
				1591	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1592	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1593
				1594	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1595	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1596
				1597	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1598	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1599
				1600	/* RISC I/O register. */
				1601	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1602	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1603
				1604	/* Mailbox registers. */
				1605	mbx_reg = &reg->mailbox0;
				1606	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1607	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1608
				1609	/* Transfer sequence registers. */
				1610	iter_reg = fw->xseq_gp_reg;
				1611	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1612	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1613	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1614	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1615	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1616	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1617	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1618	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1619
				1620	iter_reg = fw->xseq_0_reg;
				1621	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1622	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1623	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1624
				1625	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1626
				1627	/* Receive sequence registers. */
				1628	iter_reg = fw->rseq_gp_reg;
				1629	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1630	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1631	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1632	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1633	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1634	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1635	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1636	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1637
				1638	iter_reg = fw->rseq_0_reg;
				1639	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1640	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1641
				1642	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1643	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1644
				1645	/* Auxiliary sequence registers. */
				1646	iter_reg = fw->aseq_gp_reg;
				1647	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1648	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1649	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1650	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1651	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1652	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1653	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1654	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1655
				1656	iter_reg = fw->aseq_0_reg;
				1657	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1658	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1659
				1660	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1661	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1662
				1663	/* Command DMA registers. */
				1664	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1665
				1666	/* Queues. */
				1667	iter_reg = fw->req0_dma_reg;
				1668	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1669	dmp_reg = &reg->iobase_q;
				1670	for (cnt = 0; cnt < 7; cnt++)
				1671	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1672
				1673	iter_reg = fw->resp0_dma_reg;
				1674	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1675	dmp_reg = &reg->iobase_q;
				1676	for (cnt = 0; cnt < 7; cnt++)
				1677	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1678
				1679	iter_reg = fw->req1_dma_reg;
				1680	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1681	dmp_reg = &reg->iobase_q;
				1682	for (cnt = 0; cnt < 7; cnt++)
				1683	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1684
				1685	/* Transmit DMA registers. */
				1686	iter_reg = fw->xmt0_dma_reg;
				1687	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1688	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1689
				1690	iter_reg = fw->xmt1_dma_reg;
				1691	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1692	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1693
				1694	iter_reg = fw->xmt2_dma_reg;
				1695	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1696	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1697
				1698	iter_reg = fw->xmt3_dma_reg;
				1699	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1700	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1701
				1702	iter_reg = fw->xmt4_dma_reg;
				1703	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1704	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1705
				1706	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1707
				1708	/* Receive DMA registers. */
				1709	iter_reg = fw->rcvt0_data_dma_reg;
				1710	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1711	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1712
				1713	iter_reg = fw->rcvt1_data_dma_reg;
				1714	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1715	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1716
				1717	/* RISC registers. */
				1718	iter_reg = fw->risc_gp_reg;
				1719	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1720	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1721	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1722	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1723	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1724	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1725	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1726	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1727
				1728	/* Local memory controller registers. */
				1729	iter_reg = fw->lmc_reg;
				1730	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1731	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1732	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1733	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1734	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1735	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1736	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1737	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1738
				1739	/* Fibre Protocol Module registers. */
				1740	iter_reg = fw->fpm_hdw_reg;
				1741	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1742	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1743	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1744	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1745	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1746	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1747	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1748	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1749	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1750	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1751	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1752	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1753	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1754	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1755
				1756	/* Frame Buffer registers. */
				1757	iter_reg = fw->fb_hdw_reg;
				1758	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1759	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1760	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1761	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1762	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1763	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1764	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1765	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1766	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1767	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1768	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1769	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1770	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1771
				1772	/* Multi queue registers */
				1773	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1774	&last_chain);
				1775
				1776	rval = qla24xx_soft_reset(ha);
				1777	if (rval != QLA_SUCCESS)
				1778	goto qla81xx_fw_dump_failed_0;
				1779
				1780	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1781	&nxt);
				1782	if (rval != QLA_SUCCESS)
				1783	goto qla81xx_fw_dump_failed_0;
				1784
				1785	nxt = qla2xxx_copy_queues(ha, nxt);
				1786
				1787	nxt = qla24xx_copy_eft(ha, nxt);
				1788
				1789	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1790	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1791	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1792	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1793	if (last_chain) {
				1794	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1795	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1796	}
				1797
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1798	/* Adjust valid length. */
				1799	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1800
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1801	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1802	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1803
				1804	qla81xx_fw_dump_failed:
				1805	if (!hardware_locked)
				1806	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1807	}
				1808
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1809	void
				1810	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1811	{
				1812	int rval;
				1813	uint32_t cnt, reg_data;
				1814	uint32_t risc_address;
				1815	struct qla_hw_data *ha = vha->hw;
				1816	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1817	uint32_t __iomem *dmp_reg;
				1818	uint32_t *iter_reg;
				1819	uint16_t __iomem *mbx_reg;
				1820	unsigned long flags;
				1821	struct qla83xx_fw_dump *fw;
				1822	uint32_t ext_mem_cnt;
				1823	void nxt, nxt_chain;
				1824	uint32_t *last_chain = NULL;
				1825	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1826
				1827	risc_address = ext_mem_cnt = 0;
				1828	flags = 0;
				1829
				1830	if (!hardware_locked)
				1831	spin_lock_irqsave(&ha->hardware_lock, flags);
				1832
				1833	if (!ha->fw_dump) {
				1834	ql_log(ql_log_warn, vha, 0xd00c,
				1835	"No buffer available for dump!!!\n");
				1836	goto qla83xx_fw_dump_failed;
				1837	}
				1838
				1839	if (ha->fw_dumped) {
				1840	ql_log(ql_log_warn, vha, 0xd00d,
				1841	"Firmware has been previously dumped (%p) -- ignoring "
				1842	"request...\n", ha->fw_dump);
				1843	goto qla83xx_fw_dump_failed;
				1844	}
				1845	fw = &ha->fw_dump->isp.isp83;
				1846	qla2xxx_prep_dump(ha, ha->fw_dump);
				1847
				1848	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1849
				1850	/* Pause RISC. */
				1851	rval = qla24xx_pause_risc(reg);
				1852	if (rval != QLA_SUCCESS)
				1853	goto qla83xx_fw_dump_failed_0;
				1854
				1855	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1856	dmp_reg = &reg->iobase_window;
				1857	reg_data = RD_REG_DWORD(dmp_reg);
				1858	WRT_REG_DWORD(dmp_reg, 0);
				1859
				1860	dmp_reg = &reg->unused_4_1[0];
				1861	reg_data = RD_REG_DWORD(dmp_reg);
				1862	WRT_REG_DWORD(dmp_reg, 0);
				1863
				1864	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				1865	dmp_reg = &reg->unused_4_1[2];
				1866	reg_data = RD_REG_DWORD(dmp_reg);
				1867	WRT_REG_DWORD(dmp_reg, 0);
				1868
				1869	/* select PCR and disable ecc checking and correction */
				1870	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1871	RD_REG_DWORD(&reg->iobase_addr);
				1872	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				1873
				1874	/* Host/Risc registers. */
				1875	iter_reg = fw->host_risc_reg;
				1876	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1877	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1878	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				1879
				1880	/* PCIe registers. */
				1881	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1882	RD_REG_DWORD(&reg->iobase_addr);
				1883	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1884	dmp_reg = &reg->iobase_c4;
				1885	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1886	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1887	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1888	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1889
				1890	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1891	RD_REG_DWORD(&reg->iobase_window);
				1892
				1893	/* Host interface registers. */
				1894	dmp_reg = &reg->flash_addr;
				1895	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1896	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1897
				1898	/* Disable interrupts. */
				1899	WRT_REG_DWORD(&reg->ictrl, 0);
				1900	RD_REG_DWORD(&reg->ictrl);
				1901
				1902	/* Shadow registers. */
				1903	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1904	RD_REG_DWORD(&reg->iobase_addr);
				1905	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1906	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1907
				1908	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1909	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1910
				1911	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1912	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1913
				1914	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1915	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1916
				1917	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1918	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1919
				1920	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1921	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1922
				1923	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1924	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1925
				1926	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1927	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1928
				1929	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1930	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1931
				1932	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1933	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1934
				1935	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1936	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1937
				1938	/* RISC I/O register. */
				1939	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1940	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1941
				1942	/* Mailbox registers. */
				1943	mbx_reg = &reg->mailbox0;
				1944	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1945	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1946
				1947	/* Transfer sequence registers. */
				1948	iter_reg = fw->xseq_gp_reg;
				1949	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				1950	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				1951	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				1952	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				1953	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				1954	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				1955	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				1956	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				1957	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1958	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1959	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1960	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1961	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1962	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1963	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1964	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1965
				1966	iter_reg = fw->xseq_0_reg;
				1967	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1968	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1969	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1970
				1971	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1972
				1973	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				1974
				1975	/* Receive sequence registers. */
				1976	iter_reg = fw->rseq_gp_reg;
				1977	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				1978	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				1979	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				1980	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				1981	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				1982	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				1983	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				1984	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				1985	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1986	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1987	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1988	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1989	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1990	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1991	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1992	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1993
				1994	iter_reg = fw->rseq_0_reg;
				1995	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1996	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1997
				1998	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1999	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2000	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2001
				2002	/* Auxiliary sequence registers. */
				2003	iter_reg = fw->aseq_gp_reg;
				2004	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2005	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2006	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2007	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2008	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2009	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2010	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2011	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2012	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2013	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2014	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2015	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2016	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2017	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2018	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2019	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2020
				2021	iter_reg = fw->aseq_0_reg;
				2022	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2023	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2024
				2025	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2026	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2027	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2028
				2029	/* Command DMA registers. */
				2030	iter_reg = fw->cmd_dma_reg;
				2031	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2032	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2033	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2034	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2035
				2036	/* Queues. */
				2037	iter_reg = fw->req0_dma_reg;
				2038	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2039	dmp_reg = &reg->iobase_q;
				2040	for (cnt = 0; cnt < 7; cnt++)
				2041	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2042
				2043	iter_reg = fw->resp0_dma_reg;
				2044	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2045	dmp_reg = &reg->iobase_q;
				2046	for (cnt = 0; cnt < 7; cnt++)
				2047	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2048
				2049	iter_reg = fw->req1_dma_reg;
				2050	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2051	dmp_reg = &reg->iobase_q;
				2052	for (cnt = 0; cnt < 7; cnt++)
				2053	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2054
				2055	/* Transmit DMA registers. */
				2056	iter_reg = fw->xmt0_dma_reg;
				2057	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2058	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2059
				2060	iter_reg = fw->xmt1_dma_reg;
				2061	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2062	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2063
				2064	iter_reg = fw->xmt2_dma_reg;
				2065	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2066	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2067
				2068	iter_reg = fw->xmt3_dma_reg;
				2069	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2070	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2071
				2072	iter_reg = fw->xmt4_dma_reg;
				2073	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2074	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2075
				2076	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2077
				2078	/* Receive DMA registers. */
				2079	iter_reg = fw->rcvt0_data_dma_reg;
				2080	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2081	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2082
				2083	iter_reg = fw->rcvt1_data_dma_reg;
				2084	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2085	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2086
				2087	/* RISC registers. */
				2088	iter_reg = fw->risc_gp_reg;
				2089	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2090	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2091	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2092	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2093	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2094	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2095	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2096	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2097
				2098	/* Local memory controller registers. */
				2099	iter_reg = fw->lmc_reg;
				2100	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2101	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2102	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2103	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2104	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2105	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2106	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2107	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2108
				2109	/* Fibre Protocol Module registers. */
				2110	iter_reg = fw->fpm_hdw_reg;
				2111	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2112	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2113	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2114	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2115	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2116	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2117	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2118	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2119	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2120	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2121	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2122	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2123	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2124	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2125	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2126	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2127
				2128	/* RQ0 Array registers. */
				2129	iter_reg = fw->rq0_array_reg;
				2130	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2131	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2132	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2133	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2134	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2135	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2137	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2138	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2139	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2140	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2141	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2142	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2143	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2144	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2145	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2146
				2147	/* RQ1 Array registers. */
				2148	iter_reg = fw->rq1_array_reg;
				2149	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2150	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2151	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2152	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2153	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2154	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2155	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2157	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2158	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2159	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2160	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2161	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2162	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2163	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2164	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2165
				2166	/* RP0 Array registers. */
				2167	iter_reg = fw->rp0_array_reg;
				2168	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2169	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2170	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2171	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2172	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2173	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2174	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2175	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2176	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2177	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2178	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2179	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2180	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2181	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2182	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2183	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2184
				2185	/* RP1 Array registers. */
				2186	iter_reg = fw->rp1_array_reg;
				2187	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2188	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2189	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2190	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2191	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2192	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2193	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2194	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2195	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2196	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2197	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2198	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2199	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2200	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2201	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2202	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2203
				2204	iter_reg = fw->at0_array_reg;
				2205	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2206	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2207	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2208	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2209	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2210	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2211	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2212	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2213
				2214	/* I/O Queue Control registers. */
				2215	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2216
				2217	/* Frame Buffer registers. */
				2218	iter_reg = fw->fb_hdw_reg;
				2219	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2220	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2221	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2222	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2223	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2224	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2225	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2226	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2227	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2228	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2229	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2230	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2231	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2232	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2233	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2234	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2235	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2236	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2237	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2238	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2239	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2240	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2241	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2245	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2246
				2247	/* Multi queue registers */
				2248	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2249	&last_chain);
				2250
				2251	rval = qla24xx_soft_reset(ha);
				2252	if (rval != QLA_SUCCESS) {
				2253	ql_log(ql_log_warn, vha, 0xd00e,
				2254	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2255	rval = QLA_SUCCESS;
				2256
				2257	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2258
				2259	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2260	RD_REG_DWORD(&reg->hccr);
				2261
				2262	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2263	RD_REG_DWORD(&reg->hccr);
				2264
				2265	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2266	RD_REG_DWORD(&reg->hccr);
				2267
				2268	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2269	udelay(5);
				2270
				2271	if (!cnt) {
				2272	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2273	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2274	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2275	goto copy_queue;
				2276	} else
				2277	ql_log(ql_log_warn, vha, 0xd010,
				2278	"bigger hammer success?\n");
				2279	}
				2280
				2281	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2282	&nxt);
				2283	if (rval != QLA_SUCCESS)
				2284	goto qla83xx_fw_dump_failed_0;
				2285
				2286	copy_queue:
				2287	nxt = qla2xxx_copy_queues(ha, nxt);
				2288
				2289	nxt = qla24xx_copy_eft(ha, nxt);
				2290
				2291	/* Chain entries -- started with MQ. */
				2292	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2293	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2294	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2295	if (last_chain) {
				2296	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				2297	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				2298	}
				2299
				2300	/* Adjust valid length. */
				2301	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2302
				2303	qla83xx_fw_dump_failed_0:
				2304	qla2xxx_dump_post_process(base_vha, rval);
				2305
				2306	qla83xx_fw_dump_failed:
				2307	if (!hardware_locked)
				2308	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				2309	}
				2310
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2311	/****************************************************************************/
				2312	/* Driver Debug Functions. */
				2313	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2314
				2315	static inline int
				2316	ql_mask_match(uint32_t level)
				2317	{
				2318	if (ql2xextended_error_logging == 1)
				2319	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2320	return (level & ql2xextended_error_logging) == level;
				2321	}
				2322
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2323	/*
				2324	* This function is for formatting and logging debug information.
				2325	* It is to be used when vha is available. It formats the message
				2326	* and logs it to the messages file.
				2327	* parameters:
				2328	* level: The level of the debug messages to be printed.
				2329	* If ql2xextended_error_logging value is correctly set,
				2330	* this message will appear in the messages file.
				2331	* vha: Pointer to the scsi_qla_host_t.
				2332	* id: This is a unique identifier for the level. It identifies the
				2333	* part of the code from where the message originated.
				2334	* msg: The message to be displayed.
				2335	*/
				2336	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2337	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2338	{
				2339	va_list va;
				2340	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2341
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2342	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2343	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2344
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2345	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2346
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2347	vaf.fmt = fmt;
				2348	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2349
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2350	if (vha != NULL) {
				2351	const struct pci_dev *pdev = vha->hw->pdev;
				2352	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2353	pr_warn("%s [%s]-%04x:%ld: %pV",
				2354	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2355	vha->host_no, &vaf);
				2356	} else {
				2357	pr_warn("%s [%s]-%04x: : %pV",
				2358	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2359	}
				2360
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2361	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2362
				2363	}
				2364
				2365	/*
				2366	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2367	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2368	* i.e., before host allocation. It formats the message and logs it
				2369	* to the messages file.
				2370	* parameters:
				2371	* level: The level of the debug messages to be printed.
				2372	* If ql2xextended_error_logging value is correctly set,
				2373	* this message will appear in the messages file.
				2374	* pdev: Pointer to the struct pci_dev.
				2375	* id: This is a unique id for the level. It identifies the part
				2376	* of the code from where the message originated.
				2377	* msg: The message to be displayed.
				2378	*/
				2379	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2380	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2381	const char *fmt, ...)
				2382	{
				2383	va_list va;
				2384	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2385
				2386	if (pdev == NULL)
				2387	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2388	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2389	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2390
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2391	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2392
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2393	vaf.fmt = fmt;
				2394	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2395
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2396	/* <module-name> <dev-name>:<msg-id> Message */
				2397	pr_warn("%s [%s]-%04x: : %pV",
				2398	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2399
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2400	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2401	}
				2402
				2403	/*
				2404	* This function is for formatting and logging log messages.
				2405	* It is to be used when vha is available. It formats the message
				2406	* and logs it to the messages file. All the messages will be logged
				2407	* irrespective of value of ql2xextended_error_logging.
				2408	* parameters:
				2409	* level: The level of the log messages to be printed in the
				2410	* messages file.
				2411	* vha: Pointer to the scsi_qla_host_t
				2412	* id: This is a unique id for the level. It identifies the
				2413	* part of the code from where the message originated.
				2414	* msg: The message to be displayed.
				2415	*/
				2416	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2417	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2418	{
				2419	va_list va;
				2420	struct va_format vaf;
				2421	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2422
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2423	if (level > ql_errlev)
				2424	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2425
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2426	if (vha != NULL) {
				2427	const struct pci_dev *pdev = vha->hw->pdev;
				2428	/* <module-name> <msg-id>:<host> Message */
				2429	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2430	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2431	} else {
				2432	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2433	QL_MSGHDR, "0000:00:00.0", id);
				2434	}
				2435	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2436
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2437	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2438
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2439	vaf.fmt = fmt;
				2440	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2441
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2442	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2443	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2444	pr_crit("%s%pV", pbuf, &vaf);
				2445	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2446	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2447	pr_err("%s%pV", pbuf, &vaf);
				2448	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2449	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2450	pr_warn("%s%pV", pbuf, &vaf);
				2451	break;
				2452	default:
				2453	pr_info("%s%pV", pbuf, &vaf);
				2454	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2455	}
				2456
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2457	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2458	}
				2459
				2460	/*
				2461	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2462	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2463	* i.e., before host allocation. It formats the message and logs
				2464	* it to the messages file. All the messages are logged irrespective
				2465	* of the value of ql2xextended_error_logging.
				2466	* parameters:
				2467	* level: The level of the log messages to be printed in the
				2468	* messages file.
				2469	* pdev: Pointer to the struct pci_dev.
				2470	* id: This is a unique id for the level. It identifies the
				2471	* part of the code from where the message originated.
				2472	* msg: The message to be displayed.
				2473	*/
				2474	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2475	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2476	const char *fmt, ...)
				2477	{
				2478	va_list va;
				2479	struct va_format vaf;
				2480	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2481
				2482	if (pdev == NULL)
				2483	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2484	if (level > ql_errlev)
				2485	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2486
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2487	/* <module-name> <dev-name>:<msg-id> Message */
				2488	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2489	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2490	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2491
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2492	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2493
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2494	vaf.fmt = fmt;
				2495	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2496
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2497	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2498	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2499	pr_crit("%s%pV", pbuf, &vaf);
				2500	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2501	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2502	pr_err("%s%pV", pbuf, &vaf);
				2503	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2504	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2505	pr_warn("%s%pV", pbuf, &vaf);
				2506	break;
				2507	default:
				2508	pr_info("%s%pV", pbuf, &vaf);
				2509	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2510	}
				2511
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2512	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2513	}
				2514
				2515	void
				2516	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2517	{
				2518	int i;
				2519	struct qla_hw_data *ha = vha->hw;
				2520	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2521	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2522	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2523	uint16_t __iomem *mbx_reg;
				2524
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2525	if (!ql_mask_match(level))
				2526	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2527
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2528	if (IS_QLA82XX(ha))
				2529	mbx_reg = &reg82->mailbox_in[0];
				2530	else if (IS_FWI2_CAPABLE(ha))
				2531	mbx_reg = &reg24->mailbox0;
				2532	else
				2533	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2534
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2535	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2536	for (i = 0; i < 6; i++)
				2537	ql_dbg(level, vha, id,
				2538	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2539	}
				2540
				2541
				2542	void
				2543	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2544	uint8_t *b, uint32_t size)
				2545	{
				2546	uint32_t cnt;
				2547	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2548
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2549	if (!ql_mask_match(level))
				2550	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2551
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2552	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2553	"9 Ah Bh Ch Dh Eh Fh\n");
				2554	ql_dbg(level, vha, id, "----------------------------------"
				2555	"----------------------------\n");
				2556
				2557	ql_dbg(level, vha, id, " ");
				2558	for (cnt = 0; cnt < size;) {
				2559	c = *b++;
				2560	printk("%02x", (uint32_t) c);
				2561	cnt++;
				2562	if (!(cnt % 16))
				2563	printk("\n");
				2564	else
				2565	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2566	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2567	if (cnt % 16)
				2568	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2569	}