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Chris Leech0bbd5f42006-05-23 17:35:34 -07001/*
Shannon Nelson43d6e362007-10-16 01:27:39 -07002 * Intel I/OAT DMA Linux driver
Maciej Sosnowski211a22c2009-02-26 11:05:43 +01003 * Copyright(c) 2004 - 2009 Intel Corporation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07004 *
5 * This program is free software; you can redistribute it and/or modify it
Shannon Nelson43d6e362007-10-16 01:27:39 -07006 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
Chris Leech0bbd5f42006-05-23 17:35:34 -07008 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
Shannon Nelson43d6e362007-10-16 01:27:39 -070015 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
Chris Leech0bbd5f42006-05-23 17:35:34 -070017 *
Shannon Nelson43d6e362007-10-16 01:27:39 -070018 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
Chris Leech0bbd5f42006-05-23 17:35:34 -070021 */
22
23/*
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
25 * copy operations.
26 */
27
28#include <linux/init.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
David S. Miller6b00c922006-05-23 17:37:58 -070034#include <linux/dma-mapping.h>
Maciej Sosnowski09177e82008-07-22 10:07:33 -070035#include <linux/workqueue.h>
Venki Pallipadi3ad0b022008-10-22 16:34:52 -070036#include <linux/i7300_idle.h>
Dan Williams584ec222009-07-28 14:32:12 -070037#include "dma.h"
38#include "registers.h"
39#include "hw.h"
Chris Leech0bbd5f42006-05-23 17:35:34 -070040
Dan Williams5cbafa62009-08-26 13:01:44 -070041int ioat_pending_level = 4;
Shannon Nelson7bb67c12007-11-14 16:59:51 -080042module_param(ioat_pending_level, int, 0644);
43MODULE_PARM_DESC(ioat_pending_level,
44 "high-water mark for pushing ioat descriptors (default: 4)");
45
Chris Leech0bbd5f42006-05-23 17:35:34 -070046/* internal functions */
Dan Williams5cbafa62009-08-26 13:01:44 -070047static void ioat1_cleanup(struct ioat_dma_chan *ioat);
48static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
Shannon Nelson3e037452007-10-16 01:27:40 -070049
50/**
51 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
52 * @irq: interrupt id
53 * @data: interrupt data
54 */
55static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
56{
57 struct ioatdma_device *instance = data;
Dan Williamsdcbc8532009-07-28 14:44:50 -070058 struct ioat_chan_common *chan;
Shannon Nelson3e037452007-10-16 01:27:40 -070059 unsigned long attnstatus;
60 int bit;
61 u8 intrctrl;
62
63 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
64
65 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
66 return IRQ_NONE;
67
68 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
69 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
70 return IRQ_NONE;
71 }
72
73 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
74 for_each_bit(bit, &attnstatus, BITS_PER_LONG) {
Dan Williamsdcbc8532009-07-28 14:44:50 -070075 chan = ioat_chan_by_index(instance, bit);
76 tasklet_schedule(&chan->cleanup_task);
Shannon Nelson3e037452007-10-16 01:27:40 -070077 }
78
79 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
80 return IRQ_HANDLED;
81}
82
83/**
84 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
85 * @irq: interrupt id
86 * @data: interrupt data
87 */
88static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
89{
Dan Williamsdcbc8532009-07-28 14:44:50 -070090 struct ioat_chan_common *chan = data;
Shannon Nelson3e037452007-10-16 01:27:40 -070091
Dan Williamsdcbc8532009-07-28 14:44:50 -070092 tasklet_schedule(&chan->cleanup_task);
Shannon Nelson3e037452007-10-16 01:27:40 -070093
94 return IRQ_HANDLED;
95}
96
Dan Williams5cbafa62009-08-26 13:01:44 -070097static void ioat1_cleanup_tasklet(unsigned long data);
98
99/* common channel initialization */
100void ioat_init_channel(struct ioatdma_device *device,
101 struct ioat_chan_common *chan, int idx,
Dan Williams09c8a5b2009-09-08 12:01:49 -0700102 void (*timer_fn)(unsigned long),
103 void (*tasklet)(unsigned long),
104 unsigned long ioat)
Dan Williams5cbafa62009-08-26 13:01:44 -0700105{
106 struct dma_device *dma = &device->common;
107
108 chan->device = device;
109 chan->reg_base = device->reg_base + (0x80 * (idx + 1));
Dan Williams5cbafa62009-08-26 13:01:44 -0700110 spin_lock_init(&chan->cleanup_lock);
111 chan->common.device = dma;
112 list_add_tail(&chan->common.device_node, &dma->channels);
113 device->idx[idx] = chan;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700114 init_timer(&chan->timer);
115 chan->timer.function = timer_fn;
116 chan->timer.data = ioat;
117 tasklet_init(&chan->cleanup_task, tasklet, ioat);
Dan Williams5cbafa62009-08-26 13:01:44 -0700118 tasklet_disable(&chan->cleanup_task);
119}
120
Dan Williams09c8a5b2009-09-08 12:01:49 -0700121static void ioat1_timer_event(unsigned long data);
Shannon Nelson3e037452007-10-16 01:27:40 -0700122
123/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700124 * ioat1_dma_enumerate_channels - find and initialize the device's channels
Shannon Nelson3e037452007-10-16 01:27:40 -0700125 * @device: the device to be enumerated
126 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700127static int ioat1_enumerate_channels(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700128{
129 u8 xfercap_scale;
130 u32 xfercap;
131 int i;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700132 struct ioat_dma_chan *ioat;
Dan Williamse6c0b692009-09-08 17:29:44 -0700133 struct device *dev = &device->pdev->dev;
Dan Williamsf2427e22009-07-28 14:42:38 -0700134 struct dma_device *dma = &device->common;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700135
Dan Williamsf2427e22009-07-28 14:42:38 -0700136 INIT_LIST_HEAD(&dma->channels);
137 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700138 dma->chancnt &= 0x1f; /* bits [4:0] valid */
139 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
140 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
141 dma->chancnt, ARRAY_SIZE(device->idx));
142 dma->chancnt = ARRAY_SIZE(device->idx);
143 }
Chris Leeche3828812007-03-08 09:57:35 -0800144 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
Dan Williamsbb320782009-09-08 12:01:14 -0700145 xfercap_scale &= 0x1f; /* bits [4:0] valid */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700146 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
Dan Williams6df91832009-09-08 12:00:55 -0700147 dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700148
Venki Pallipadif371be62008-10-23 15:39:06 -0700149#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
Dan Williamsf2427e22009-07-28 14:42:38 -0700150 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
151 dma->chancnt--;
Andy Henroid27471fd2008-10-09 11:45:22 -0700152#endif
Dan Williamsf2427e22009-07-28 14:42:38 -0700153 for (i = 0; i < dma->chancnt; i++) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700154 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
Dan Williams5cbafa62009-08-26 13:01:44 -0700155 if (!ioat)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700156 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700157
Dan Williams5cbafa62009-08-26 13:01:44 -0700158 ioat_init_channel(device, &ioat->base, i,
Dan Williams09c8a5b2009-09-08 12:01:49 -0700159 ioat1_timer_event,
Dan Williams5cbafa62009-08-26 13:01:44 -0700160 ioat1_cleanup_tasklet,
161 (unsigned long) ioat);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700162 ioat->xfercap = xfercap;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700163 spin_lock_init(&ioat->desc_lock);
164 INIT_LIST_HEAD(&ioat->free_desc);
165 INIT_LIST_HEAD(&ioat->used_desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700166 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700167 dma->chancnt = i;
168 return i;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700169}
170
Shannon Nelson711924b2007-12-17 16:20:08 -0800171/**
172 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
173 * descriptors to hw
174 * @chan: DMA channel handle
175 */
Dan Williamsbc3c7022009-07-28 14:33:42 -0700176static inline void
Dan Williamsdcbc8532009-07-28 14:44:50 -0700177__ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
Shannon Nelson711924b2007-12-17 16:20:08 -0800178{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700179 void __iomem *reg_base = ioat->base.reg_base;
180
Dan Williams6df91832009-09-08 12:00:55 -0700181 dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
182 __func__, ioat->pending);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700183 ioat->pending = 0;
184 writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
Shannon Nelson711924b2007-12-17 16:20:08 -0800185}
186
187static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
188{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700189 struct ioat_dma_chan *ioat = to_ioat_chan(chan);
Shannon Nelson711924b2007-12-17 16:20:08 -0800190
Dan Williamsdcbc8532009-07-28 14:44:50 -0700191 if (ioat->pending > 0) {
192 spin_lock_bh(&ioat->desc_lock);
193 __ioat1_dma_memcpy_issue_pending(ioat);
194 spin_unlock_bh(&ioat->desc_lock);
Shannon Nelson711924b2007-12-17 16:20:08 -0800195 }
196}
197
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700198/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700199 * ioat1_reset_channel - restart a channel
Dan Williamsdcbc8532009-07-28 14:44:50 -0700200 * @ioat: IOAT DMA channel handle
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700201 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700202static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700203{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700204 struct ioat_chan_common *chan = &ioat->base;
205 void __iomem *reg_base = chan->reg_base;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700206 u32 chansts, chanerr;
207
Dan Williams09c8a5b2009-09-08 12:01:49 -0700208 dev_warn(to_dev(chan), "reset\n");
Dan Williamsdcbc8532009-07-28 14:44:50 -0700209 chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700210 chansts = *chan->completion & IOAT_CHANSTS_STATUS;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700211 if (chanerr) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700212 dev_err(to_dev(chan),
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700213 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
Dan Williamsdcbc8532009-07-28 14:44:50 -0700214 chan_num(chan), chansts, chanerr);
215 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700216 }
217
218 /*
219 * whack it upside the head with a reset
220 * and wait for things to settle out.
221 * force the pending count to a really big negative
222 * to make sure no one forces an issue_pending
223 * while we're waiting.
224 */
225
Dan Williamsdcbc8532009-07-28 14:44:50 -0700226 ioat->pending = INT_MIN;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700227 writeb(IOAT_CHANCMD_RESET,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700228 reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
Dan Williams09c8a5b2009-09-08 12:01:49 -0700229 set_bit(IOAT_RESET_PENDING, &chan->state);
230 mod_timer(&chan->timer, jiffies + RESET_DELAY);
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700231}
232
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800233static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
Dan Williams7405f742007-01-02 11:10:43 -0700234{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700235 struct dma_chan *c = tx->chan;
236 struct ioat_dma_chan *ioat = to_ioat_chan(c);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700237 struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700238 struct ioat_chan_common *chan = &ioat->base;
Dan Williamsa0587bc2009-07-28 14:44:04 -0700239 struct ioat_desc_sw *first;
240 struct ioat_desc_sw *chain_tail;
Dan Williams7405f742007-01-02 11:10:43 -0700241 dma_cookie_t cookie;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700242
Dan Williamsdcbc8532009-07-28 14:44:50 -0700243 spin_lock_bh(&ioat->desc_lock);
Dan Williams7405f742007-01-02 11:10:43 -0700244 /* cookie incr and addition to used_list must be atomic */
Dan Williamsdcbc8532009-07-28 14:44:50 -0700245 cookie = c->cookie;
Dan Williams7405f742007-01-02 11:10:43 -0700246 cookie++;
247 if (cookie < 0)
248 cookie = 1;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700249 c->cookie = cookie;
250 tx->cookie = cookie;
Dan Williams6df91832009-09-08 12:00:55 -0700251 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
Dan Williams7405f742007-01-02 11:10:43 -0700252
253 /* write address into NextDescriptor field of last desc in chain */
Dan Williamsea259682009-09-08 17:53:02 -0700254 first = to_ioat_desc(desc->tx_list.next);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700255 chain_tail = to_ioat_desc(ioat->used_desc.prev);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700256 /* make descriptor updates globally visible before chaining */
257 wmb();
258 chain_tail->hw->next = first->txd.phys;
Dan Williamsea259682009-09-08 17:53:02 -0700259 list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
Dan Williams6df91832009-09-08 12:00:55 -0700260 dump_desc_dbg(ioat, chain_tail);
261 dump_desc_dbg(ioat, first);
Dan Williams7405f742007-01-02 11:10:43 -0700262
Dan Williams09c8a5b2009-09-08 12:01:49 -0700263 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
264 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
265
Dan Williamsad643f52009-09-08 12:01:38 -0700266 ioat->pending += desc->hw->tx_cnt;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700267 if (ioat->pending >= ioat_pending_level)
268 __ioat1_dma_memcpy_issue_pending(ioat);
269 spin_unlock_bh(&ioat->desc_lock);
Dan Williams7405f742007-01-02 11:10:43 -0700270
Dan Williams7405f742007-01-02 11:10:43 -0700271 return cookie;
272}
273
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800274/**
275 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
Dan Williamsdcbc8532009-07-28 14:44:50 -0700276 * @ioat: the channel supplying the memory pool for the descriptors
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800277 * @flags: allocation flags
278 */
Dan Williamsbc3c7022009-07-28 14:33:42 -0700279static struct ioat_desc_sw *
Dan Williamsdcbc8532009-07-28 14:44:50 -0700280ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700281{
282 struct ioat_dma_descriptor *desc;
283 struct ioat_desc_sw *desc_sw;
Shannon Nelson8ab89562007-10-16 01:27:39 -0700284 struct ioatdma_device *ioatdma_device;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700285 dma_addr_t phys;
286
Dan Williamsdcbc8532009-07-28 14:44:50 -0700287 ioatdma_device = ioat->base.device;
Shannon Nelson8ab89562007-10-16 01:27:39 -0700288 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700289 if (unlikely(!desc))
290 return NULL;
291
292 desc_sw = kzalloc(sizeof(*desc_sw), flags);
293 if (unlikely(!desc_sw)) {
Shannon Nelson8ab89562007-10-16 01:27:39 -0700294 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700295 return NULL;
296 }
297
298 memset(desc, 0, sizeof(*desc));
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800299
Dan Williamsea259682009-09-08 17:53:02 -0700300 INIT_LIST_HEAD(&desc_sw->tx_list);
Dan Williams5cbafa62009-08-26 13:01:44 -0700301 dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
302 desc_sw->txd.tx_submit = ioat1_tx_submit;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700303 desc_sw->hw = desc;
Dan Williamsbc3c7022009-07-28 14:33:42 -0700304 desc_sw->txd.phys = phys;
Dan Williams6df91832009-09-08 12:00:55 -0700305 set_desc_id(desc_sw, -1);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700306
307 return desc_sw;
308}
309
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800310static int ioat_initial_desc_count = 256;
311module_param(ioat_initial_desc_count, int, 0644);
312MODULE_PARM_DESC(ioat_initial_desc_count,
Dan Williams5cbafa62009-08-26 13:01:44 -0700313 "ioat1: initial descriptors per channel (default: 256)");
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800314/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700315 * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800316 * @chan: the channel to be filled out
317 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700318static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700319{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700320 struct ioat_dma_chan *ioat = to_ioat_chan(c);
321 struct ioat_chan_common *chan = &ioat->base;
Shannon Nelson711924b2007-12-17 16:20:08 -0800322 struct ioat_desc_sw *desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700323 u32 chanerr;
324 int i;
325 LIST_HEAD(tmp_list);
326
Shannon Nelsone4223972007-08-24 23:02:53 -0700327 /* have we already been set up? */
Dan Williamsdcbc8532009-07-28 14:44:50 -0700328 if (!list_empty(&ioat->free_desc))
329 return ioat->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700330
Shannon Nelson43d6e362007-10-16 01:27:39 -0700331 /* Setup register to interrupt and write completion status on error */
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700332 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700333
Dan Williamsdcbc8532009-07-28 14:44:50 -0700334 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700335 if (chanerr) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700336 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
337 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700338 }
339
340 /* Allocate descriptors */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800341 for (i = 0; i < ioat_initial_desc_count; i++) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700342 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700343 if (!desc) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700344 dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700345 break;
346 }
Dan Williams6df91832009-09-08 12:00:55 -0700347 set_desc_id(desc, i);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700348 list_add_tail(&desc->node, &tmp_list);
349 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700350 spin_lock_bh(&ioat->desc_lock);
351 ioat->desccount = i;
352 list_splice(&tmp_list, &ioat->free_desc);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700353 spin_unlock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700354
355 /* allocate a completion writeback area */
356 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700357 chan->completion = pci_pool_alloc(chan->device->completion_pool,
358 GFP_KERNEL, &chan->completion_dma);
359 memset(chan->completion, 0, sizeof(*chan->completion));
360 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700361 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700362 writel(((u64) chan->completion_dma) >> 32,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700363 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700364
Dan Williamsdcbc8532009-07-28 14:44:50 -0700365 tasklet_enable(&chan->cleanup_task);
Dan Williams5cbafa62009-08-26 13:01:44 -0700366 ioat1_dma_start_null_desc(ioat); /* give chain to dma device */
Dan Williams6df91832009-09-08 12:00:55 -0700367 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
368 __func__, ioat->desccount);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700369 return ioat->desccount;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700370}
371
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800372/**
Dan Williams5cbafa62009-08-26 13:01:44 -0700373 * ioat1_dma_free_chan_resources - release all the descriptors
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800374 * @chan: the channel to be cleaned
375 */
Dan Williams5cbafa62009-08-26 13:01:44 -0700376static void ioat1_dma_free_chan_resources(struct dma_chan *c)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700377{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700378 struct ioat_dma_chan *ioat = to_ioat_chan(c);
379 struct ioat_chan_common *chan = &ioat->base;
380 struct ioatdma_device *ioatdma_device = chan->device;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700381 struct ioat_desc_sw *desc, *_desc;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700382 int in_use_descs = 0;
383
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000384 /* Before freeing channel resources first check
385 * if they have been previously allocated for this channel.
386 */
Dan Williamsdcbc8532009-07-28 14:44:50 -0700387 if (ioat->desccount == 0)
Maciej Sosnowskic3d4f442008-11-07 01:45:52 +0000388 return;
389
Dan Williamsdcbc8532009-07-28 14:44:50 -0700390 tasklet_disable(&chan->cleanup_task);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700391 del_timer_sync(&chan->timer);
Dan Williams5cbafa62009-08-26 13:01:44 -0700392 ioat1_cleanup(ioat);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700393
Shannon Nelson3e037452007-10-16 01:27:40 -0700394 /* Delay 100ms after reset to allow internal DMA logic to quiesce
395 * before removing DMA descriptor resources.
396 */
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800397 writeb(IOAT_CHANCMD_RESET,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700398 chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
Shannon Nelson3e037452007-10-16 01:27:40 -0700399 mdelay(100);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700400
Dan Williamsdcbc8532009-07-28 14:44:50 -0700401 spin_lock_bh(&ioat->desc_lock);
Dan Williams6df91832009-09-08 12:00:55 -0700402 list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
403 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
404 __func__, desc_id(desc));
405 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700406 in_use_descs++;
407 list_del(&desc->node);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700408 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
Dan Williamsbc3c7022009-07-28 14:33:42 -0700409 desc->txd.phys);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700410 kfree(desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700411 }
412 list_for_each_entry_safe(desc, _desc,
413 &ioat->free_desc, node) {
414 list_del(&desc->node);
415 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
416 desc->txd.phys);
417 kfree(desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700418 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700419 spin_unlock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700420
Shannon Nelson8ab89562007-10-16 01:27:39 -0700421 pci_pool_free(ioatdma_device->completion_pool,
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700422 chan->completion,
423 chan->completion_dma);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700424
425 /* one is ok since we left it on there on purpose */
426 if (in_use_descs > 1)
Dan Williamsdcbc8532009-07-28 14:44:50 -0700427 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
Chris Leech0bbd5f42006-05-23 17:35:34 -0700428 in_use_descs - 1);
429
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700430 chan->last_completion = 0;
431 chan->completion_dma = 0;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700432 ioat->pending = 0;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700433 ioat->desccount = 0;
Shannon Nelson3e037452007-10-16 01:27:40 -0700434}
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700435
Shannon Nelson3e037452007-10-16 01:27:40 -0700436/**
Dan Williamsdcbc8532009-07-28 14:44:50 -0700437 * ioat1_dma_get_next_descriptor - return the next available descriptor
438 * @ioat: IOAT DMA channel handle
Shannon Nelson3e037452007-10-16 01:27:40 -0700439 *
440 * Gets the next descriptor from the chain, and must be called with the
441 * channel's desc_lock held. Allocates more descriptors if the channel
442 * has run out.
443 */
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700444static struct ioat_desc_sw *
Dan Williamsdcbc8532009-07-28 14:44:50 -0700445ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
Shannon Nelson3e037452007-10-16 01:27:40 -0700446{
Shannon Nelson711924b2007-12-17 16:20:08 -0800447 struct ioat_desc_sw *new;
Shannon Nelson3e037452007-10-16 01:27:40 -0700448
Dan Williamsdcbc8532009-07-28 14:44:50 -0700449 if (!list_empty(&ioat->free_desc)) {
450 new = to_ioat_desc(ioat->free_desc.next);
Shannon Nelson3e037452007-10-16 01:27:40 -0700451 list_del(&new->node);
452 } else {
453 /* try to get another desc */
Dan Williamsdcbc8532009-07-28 14:44:50 -0700454 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
Shannon Nelson711924b2007-12-17 16:20:08 -0800455 if (!new) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700456 dev_err(to_dev(&ioat->base), "alloc failed\n");
Shannon Nelson711924b2007-12-17 16:20:08 -0800457 return NULL;
458 }
Shannon Nelson3e037452007-10-16 01:27:40 -0700459 }
Dan Williams6df91832009-09-08 12:00:55 -0700460 dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
461 __func__, desc_id(new));
Shannon Nelson3e037452007-10-16 01:27:40 -0700462 prefetch(new->hw);
463 return new;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700464}
465
Dan Williamsbc3c7022009-07-28 14:33:42 -0700466static struct dma_async_tx_descriptor *
Dan Williamsdcbc8532009-07-28 14:44:50 -0700467ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
Dan Williamsbc3c7022009-07-28 14:33:42 -0700468 dma_addr_t dma_src, size_t len, unsigned long flags)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700469{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700470 struct ioat_dma_chan *ioat = to_ioat_chan(c);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700471 struct ioat_desc_sw *desc;
472 size_t copy;
473 LIST_HEAD(chain);
474 dma_addr_t src = dma_src;
475 dma_addr_t dest = dma_dest;
476 size_t total_len = len;
477 struct ioat_dma_descriptor *hw = NULL;
478 int tx_cnt = 0;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700479
Dan Williamsdcbc8532009-07-28 14:44:50 -0700480 spin_lock_bh(&ioat->desc_lock);
Dan Williams5cbafa62009-08-26 13:01:44 -0700481 desc = ioat1_dma_get_next_descriptor(ioat);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700482 do {
483 if (!desc)
484 break;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700485
Dan Williamsa0587bc2009-07-28 14:44:04 -0700486 tx_cnt++;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700487 copy = min_t(size_t, len, ioat->xfercap);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700488
489 hw = desc->hw;
490 hw->size = copy;
491 hw->ctl = 0;
492 hw->src_addr = src;
493 hw->dst_addr = dest;
494
495 list_add_tail(&desc->node, &chain);
496
497 len -= copy;
498 dest += copy;
499 src += copy;
500 if (len) {
501 struct ioat_desc_sw *next;
502
503 async_tx_ack(&desc->txd);
Dan Williams5cbafa62009-08-26 13:01:44 -0700504 next = ioat1_dma_get_next_descriptor(ioat);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700505 hw->next = next ? next->txd.phys : 0;
Dan Williams6df91832009-09-08 12:00:55 -0700506 dump_desc_dbg(ioat, desc);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700507 desc = next;
508 } else
509 hw->next = 0;
510 } while (len);
511
512 if (!desc) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700513 struct ioat_chan_common *chan = &ioat->base;
514
515 dev_err(to_dev(chan),
Dan Williams5cbafa62009-08-26 13:01:44 -0700516 "chan%d - get_next_desc failed\n", chan_num(chan));
Dan Williamsdcbc8532009-07-28 14:44:50 -0700517 list_splice(&chain, &ioat->free_desc);
518 spin_unlock_bh(&ioat->desc_lock);
Shannon Nelson711924b2007-12-17 16:20:08 -0800519 return NULL;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700520 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700521 spin_unlock_bh(&ioat->desc_lock);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700522
523 desc->txd.flags = flags;
Dan Williamsa0587bc2009-07-28 14:44:04 -0700524 desc->len = total_len;
Dan Williamsea259682009-09-08 17:53:02 -0700525 list_splice(&chain, &desc->tx_list);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700526 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
527 hw->ctl_f.compl_write = 1;
Dan Williamsad643f52009-09-08 12:01:38 -0700528 hw->tx_cnt = tx_cnt;
Dan Williams6df91832009-09-08 12:00:55 -0700529 dump_desc_dbg(ioat, desc);
Dan Williamsa0587bc2009-07-28 14:44:04 -0700530
531 return &desc->txd;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700532}
533
Dan Williams5cbafa62009-08-26 13:01:44 -0700534static void ioat1_cleanup_tasklet(unsigned long data)
Shannon Nelson3e037452007-10-16 01:27:40 -0700535{
536 struct ioat_dma_chan *chan = (void *)data;
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700537
Dan Williams5cbafa62009-08-26 13:01:44 -0700538 ioat1_cleanup(chan);
Dan Williamsf6ab95b2009-09-08 12:01:21 -0700539 writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
Shannon Nelson3e037452007-10-16 01:27:40 -0700540}
541
Dan Williams5cbafa62009-08-26 13:01:44 -0700542static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
543 int direction, enum dma_ctrl_flags flags, bool dst)
Dan Williamse1d181e2008-07-04 00:13:40 -0700544{
Dan Williams5cbafa62009-08-26 13:01:44 -0700545 if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
546 (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
547 pci_unmap_single(pdev, addr, len, direction);
548 else
549 pci_unmap_page(pdev, addr, len, direction);
Dan Williamse1d181e2008-07-04 00:13:40 -0700550}
551
Dan Williams5cbafa62009-08-26 13:01:44 -0700552
553void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
554 size_t len, struct ioat_dma_descriptor *hw)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700555{
Dan Williams5cbafa62009-08-26 13:01:44 -0700556 struct pci_dev *pdev = chan->device->pdev;
557 size_t offset = len - hw->size;
558
559 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
560 ioat_unmap(pdev, hw->dst_addr - offset, len,
561 PCI_DMA_FROMDEVICE, flags, 1);
562
563 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
564 ioat_unmap(pdev, hw->src_addr - offset, len,
565 PCI_DMA_TODEVICE, flags, 0);
566}
567
568unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
569{
Chris Leech0bbd5f42006-05-23 17:35:34 -0700570 unsigned long phys_complete;
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700571 u64 completion;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700572
Dan Williams4fb9b9e2009-09-08 12:01:04 -0700573 completion = *chan->completion;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700574 phys_complete = ioat_chansts_to_addr(completion);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700575
Dan Williams6df91832009-09-08 12:00:55 -0700576 dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
577 (unsigned long long) phys_complete);
578
Dan Williams09c8a5b2009-09-08 12:01:49 -0700579 if (is_ioat_halted(completion)) {
580 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700581 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
Dan Williams09c8a5b2009-09-08 12:01:49 -0700582 chanerr);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700583
584 /* TODO do something to salvage the situation */
585 }
586
Dan Williams5cbafa62009-08-26 13:01:44 -0700587 return phys_complete;
588}
589
Dan Williams09c8a5b2009-09-08 12:01:49 -0700590bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
591 unsigned long *phys_complete)
592{
593 *phys_complete = ioat_get_current_completion(chan);
594 if (*phys_complete == chan->last_completion)
595 return false;
596 clear_bit(IOAT_COMPLETION_ACK, &chan->state);
597 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
598
599 return true;
600}
601
602static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
Dan Williams5cbafa62009-08-26 13:01:44 -0700603{
604 struct ioat_chan_common *chan = &ioat->base;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700605 struct list_head *_desc, *n;
Dan Williams5cbafa62009-08-26 13:01:44 -0700606 struct dma_async_tx_descriptor *tx;
607
Dan Williams6df91832009-09-08 12:00:55 -0700608 dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
609 __func__, phys_complete);
Dan Williams09c8a5b2009-09-08 12:01:49 -0700610 list_for_each_safe(_desc, n, &ioat->used_desc) {
611 struct ioat_desc_sw *desc;
612
613 prefetch(n);
614 desc = list_entry(_desc, typeof(*desc), node);
Dan Williamsbc3c7022009-07-28 14:33:42 -0700615 tx = &desc->txd;
Dan Williams5cbafa62009-08-26 13:01:44 -0700616 /*
617 * Incoming DMA requests may use multiple descriptors,
618 * due to exceeding xfercap, perhaps. If so, only the
619 * last one will have a cookie, and require unmapping.
620 */
Dan Williams6df91832009-09-08 12:00:55 -0700621 dump_desc_dbg(ioat, desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700622 if (tx->cookie) {
Dan Williams09c8a5b2009-09-08 12:01:49 -0700623 chan->completed_cookie = tx->cookie;
624 tx->cookie = 0;
Dan Williams5cbafa62009-08-26 13:01:44 -0700625 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
626 if (tx->callback) {
627 tx->callback(tx->callback_param);
628 tx->callback = NULL;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800629 }
Chris Leech0bbd5f42006-05-23 17:35:34 -0700630 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700631
632 if (tx->phys != phys_complete) {
633 /*
634 * a completed entry, but not the last, so clean
635 * up if the client is done with the descriptor
636 */
637 if (async_tx_test_ack(tx))
638 list_move_tail(&desc->node, &ioat->free_desc);
Dan Williams5cbafa62009-08-26 13:01:44 -0700639 } else {
640 /*
641 * last used desc. Do not remove, so we can
Dan Williams09c8a5b2009-09-08 12:01:49 -0700642 * append from it.
Dan Williams5cbafa62009-08-26 13:01:44 -0700643 */
Dan Williams09c8a5b2009-09-08 12:01:49 -0700644
645 /* if nothing else is pending, cancel the
646 * completion timeout
647 */
648 if (n == &ioat->used_desc) {
649 dev_dbg(to_dev(chan),
650 "%s cancel completion timeout\n",
651 __func__);
652 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
653 }
Dan Williams5cbafa62009-08-26 13:01:44 -0700654
655 /* TODO check status bits? */
656 break;
657 }
Chris Leech0bbd5f42006-05-23 17:35:34 -0700658 }
659
Dan Williamsdcbc8532009-07-28 14:44:50 -0700660 chan->last_completion = phys_complete;
Dan Williams09c8a5b2009-09-08 12:01:49 -0700661}
Chris Leech0bbd5f42006-05-23 17:35:34 -0700662
Dan Williams09c8a5b2009-09-08 12:01:49 -0700663/**
664 * ioat1_cleanup - cleanup up finished descriptors
665 * @chan: ioat channel to be cleaned up
666 *
667 * To prevent lock contention we defer cleanup when the locks are
668 * contended with a terminal timeout that forces cleanup and catches
669 * completion notification errors.
670 */
671static void ioat1_cleanup(struct ioat_dma_chan *ioat)
672{
673 struct ioat_chan_common *chan = &ioat->base;
674 unsigned long phys_complete;
675
676 prefetch(chan->completion);
677
678 if (!spin_trylock_bh(&chan->cleanup_lock))
679 return;
680
681 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
682 spin_unlock_bh(&chan->cleanup_lock);
683 return;
684 }
685
686 if (!spin_trylock_bh(&ioat->desc_lock)) {
687 spin_unlock_bh(&chan->cleanup_lock);
688 return;
689 }
690
691 __cleanup(ioat, phys_complete);
692
693 spin_unlock_bh(&ioat->desc_lock);
694 spin_unlock_bh(&chan->cleanup_lock);
695}
696
697static void ioat1_timer_event(unsigned long data)
698{
699 struct ioat_dma_chan *ioat = (void *) data;
700 struct ioat_chan_common *chan = &ioat->base;
701
702 dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
703
704 spin_lock_bh(&chan->cleanup_lock);
705 if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
706 struct ioat_desc_sw *desc;
707
708 spin_lock_bh(&ioat->desc_lock);
709
710 /* restart active descriptors */
711 desc = to_ioat_desc(ioat->used_desc.prev);
712 ioat_set_chainaddr(ioat, desc->txd.phys);
713 ioat_start(chan);
714
715 ioat->pending = 0;
716 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
717 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
718 spin_unlock_bh(&ioat->desc_lock);
719 } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
720 unsigned long phys_complete;
721
722 spin_lock_bh(&ioat->desc_lock);
723 /* if we haven't made progress and we have already
724 * acknowledged a pending completion once, then be more
725 * forceful with a restart
726 */
727 if (ioat_cleanup_preamble(chan, &phys_complete))
728 __cleanup(ioat, phys_complete);
729 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
730 ioat1_reset_channel(ioat);
731 else {
732 u64 status = ioat_chansts(chan);
733
734 /* manually update the last completion address */
735 if (ioat_chansts_to_addr(status) != 0)
736 *chan->completion = status;
737
738 set_bit(IOAT_COMPLETION_ACK, &chan->state);
739 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
740 }
741 spin_unlock_bh(&ioat->desc_lock);
742 }
Dan Williamsdcbc8532009-07-28 14:44:50 -0700743 spin_unlock_bh(&chan->cleanup_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700744}
745
Dan Williamsbc3c7022009-07-28 14:33:42 -0700746static enum dma_status
Dan Williams5cbafa62009-08-26 13:01:44 -0700747ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie,
748 dma_cookie_t *done, dma_cookie_t *used)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700749{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700750 struct ioat_dma_chan *ioat = to_ioat_chan(c);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700751
Dan Williams5cbafa62009-08-26 13:01:44 -0700752 if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
753 return DMA_SUCCESS;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700754
Dan Williams5cbafa62009-08-26 13:01:44 -0700755 ioat1_cleanup(ioat);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700756
Dan Williams5cbafa62009-08-26 13:01:44 -0700757 return ioat_is_complete(c, cookie, done, used);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700758}
759
Dan Williams5cbafa62009-08-26 13:01:44 -0700760static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700761{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700762 struct ioat_chan_common *chan = &ioat->base;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700763 struct ioat_desc_sw *desc;
Dan Williamsc7984f42009-07-28 14:44:04 -0700764 struct ioat_dma_descriptor *hw;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700765
Dan Williamsdcbc8532009-07-28 14:44:50 -0700766 spin_lock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700767
Dan Williams5cbafa62009-08-26 13:01:44 -0700768 desc = ioat1_dma_get_next_descriptor(ioat);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700769
770 if (!desc) {
Dan Williamsdcbc8532009-07-28 14:44:50 -0700771 dev_err(to_dev(chan),
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700772 "Unable to start null desc - get next desc failed\n");
Dan Williamsdcbc8532009-07-28 14:44:50 -0700773 spin_unlock_bh(&ioat->desc_lock);
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700774 return;
775 }
776
Dan Williamsc7984f42009-07-28 14:44:04 -0700777 hw = desc->hw;
778 hw->ctl = 0;
779 hw->ctl_f.null = 1;
780 hw->ctl_f.int_en = 1;
781 hw->ctl_f.compl_write = 1;
Maciej Sosnowski7f1b3582008-07-22 17:30:57 -0700782 /* set size to non-zero value (channel returns error when size is 0) */
Dan Williamsc7984f42009-07-28 14:44:04 -0700783 hw->size = NULL_DESC_BUFFER_SIZE;
784 hw->src_addr = 0;
785 hw->dst_addr = 0;
Dan Williamsbc3c7022009-07-28 14:33:42 -0700786 async_tx_ack(&desc->txd);
Dan Williams5cbafa62009-08-26 13:01:44 -0700787 hw->next = 0;
788 list_add_tail(&desc->node, &ioat->used_desc);
Dan Williams6df91832009-09-08 12:00:55 -0700789 dump_desc_dbg(ioat, desc);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700790
Dan Williams09c8a5b2009-09-08 12:01:49 -0700791 ioat_set_chainaddr(ioat, desc->txd.phys);
792 ioat_start(chan);
Dan Williamsdcbc8532009-07-28 14:44:50 -0700793 spin_unlock_bh(&ioat->desc_lock);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700794}
795
796/*
797 * Perform a IOAT transaction to verify the HW works.
798 */
799#define IOAT_TEST_SIZE 2000
800
Dan Williams345d8522009-09-08 12:01:30 -0700801static void __devinit ioat_dma_test_callback(void *dma_async_param)
Shannon Nelson95218432007-10-18 03:07:15 -0700802{
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700803 struct completion *cmp = dma_async_param;
804
805 complete(cmp);
Shannon Nelson95218432007-10-18 03:07:15 -0700806}
807
Shannon Nelson3e037452007-10-16 01:27:40 -0700808/**
809 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
810 * @device: device to be tested
811 */
Dan Williams345d8522009-09-08 12:01:30 -0700812static int __devinit ioat_dma_self_test(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -0700813{
814 int i;
815 u8 *src;
816 u8 *dest;
Dan Williamsbc3c7022009-07-28 14:33:42 -0700817 struct dma_device *dma = &device->common;
818 struct device *dev = &device->pdev->dev;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700819 struct dma_chan *dma_chan;
Shannon Nelson711924b2007-12-17 16:20:08 -0800820 struct dma_async_tx_descriptor *tx;
Dan Williams00367312008-02-02 19:49:57 -0700821 dma_addr_t dma_dest, dma_src;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700822 dma_cookie_t cookie;
823 int err = 0;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700824 struct completion cmp;
Dan Williams0c33e1c2009-03-02 13:31:35 -0700825 unsigned long tmo;
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200826 unsigned long flags;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700827
Christoph Lametere94b1762006-12-06 20:33:17 -0800828 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700829 if (!src)
830 return -ENOMEM;
Christoph Lametere94b1762006-12-06 20:33:17 -0800831 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700832 if (!dest) {
833 kfree(src);
834 return -ENOMEM;
835 }
836
837 /* Fill in src buffer */
838 for (i = 0; i < IOAT_TEST_SIZE; i++)
839 src[i] = (u8)i;
840
841 /* Start copy, using first DMA channel */
Dan Williamsbc3c7022009-07-28 14:33:42 -0700842 dma_chan = container_of(dma->channels.next, struct dma_chan,
Shannon Nelson43d6e362007-10-16 01:27:39 -0700843 device_node);
Dan Williamsbc3c7022009-07-28 14:33:42 -0700844 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
845 dev_err(dev, "selftest cannot allocate chan resource\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -0700846 err = -ENODEV;
847 goto out;
848 }
849
Dan Williamsbc3c7022009-07-28 14:33:42 -0700850 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
851 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
Dan Williamsa6a39ca2009-07-28 14:44:05 -0700852 flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
853 DMA_PREP_INTERRUPT;
Dan Williams00367312008-02-02 19:49:57 -0700854 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
Maciej Sosnowski4f005db2009-04-23 12:31:51 +0200855 IOAT_TEST_SIZE, flags);
Shannon Nelson5149fd02007-10-18 03:07:13 -0700856 if (!tx) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700857 dev_err(dev, "Self-test prep failed, disabling\n");
Shannon Nelson5149fd02007-10-18 03:07:13 -0700858 err = -ENODEV;
859 goto free_resources;
860 }
861
Dan Williams7405f742007-01-02 11:10:43 -0700862 async_tx_ack(tx);
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700863 init_completion(&cmp);
Shannon Nelson95218432007-10-18 03:07:15 -0700864 tx->callback = ioat_dma_test_callback;
Dan Williamsb9bdcbb2009-01-06 11:38:22 -0700865 tx->callback_param = &cmp;
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800866 cookie = tx->tx_submit(tx);
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700867 if (cookie < 0) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700868 dev_err(dev, "Self-test setup failed, disabling\n");
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700869 err = -ENODEV;
870 goto free_resources;
871 }
Dan Williamsbc3c7022009-07-28 14:33:42 -0700872 dma->device_issue_pending(dma_chan);
Dan Williams532d3b12008-12-03 17:16:55 -0700873
Dan Williams0c33e1c2009-03-02 13:31:35 -0700874 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
Chris Leech0bbd5f42006-05-23 17:35:34 -0700875
Dan Williams0c33e1c2009-03-02 13:31:35 -0700876 if (tmo == 0 ||
Dan Williamsbc3c7022009-07-28 14:33:42 -0700877 dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL)
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800878 != DMA_SUCCESS) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700879 dev_err(dev, "Self-test copy timed out, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -0700880 err = -ENODEV;
881 goto free_resources;
882 }
883 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
Dan Williamsbc3c7022009-07-28 14:33:42 -0700884 dev_err(dev, "Self-test copy failed compare, disabling\n");
Chris Leech0bbd5f42006-05-23 17:35:34 -0700885 err = -ENODEV;
886 goto free_resources;
887 }
888
889free_resources:
Dan Williamsbc3c7022009-07-28 14:33:42 -0700890 dma->device_free_chan_resources(dma_chan);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700891out:
892 kfree(src);
893 kfree(dest);
894 return err;
895}
896
Shannon Nelson3e037452007-10-16 01:27:40 -0700897static char ioat_interrupt_style[32] = "msix";
898module_param_string(ioat_interrupt_style, ioat_interrupt_style,
899 sizeof(ioat_interrupt_style), 0644);
900MODULE_PARM_DESC(ioat_interrupt_style,
901 "set ioat interrupt style: msix (default), "
902 "msix-single-vector, msi, intx)");
903
904/**
905 * ioat_dma_setup_interrupts - setup interrupt handler
906 * @device: ioat device
907 */
908static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
909{
Dan Williamsdcbc8532009-07-28 14:44:50 -0700910 struct ioat_chan_common *chan;
Dan Williamse6c0b692009-09-08 17:29:44 -0700911 struct pci_dev *pdev = device->pdev;
912 struct device *dev = &pdev->dev;
913 struct msix_entry *msix;
914 int i, j, msixcnt;
915 int err = -EINVAL;
Shannon Nelson3e037452007-10-16 01:27:40 -0700916 u8 intrctrl = 0;
917
918 if (!strcmp(ioat_interrupt_style, "msix"))
919 goto msix;
920 if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
921 goto msix_single_vector;
922 if (!strcmp(ioat_interrupt_style, "msi"))
923 goto msi;
924 if (!strcmp(ioat_interrupt_style, "intx"))
925 goto intx;
Dan Williamse6c0b692009-09-08 17:29:44 -0700926 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
Shannon Nelson5149fd02007-10-18 03:07:13 -0700927 goto err_no_irq;
Shannon Nelson3e037452007-10-16 01:27:40 -0700928
929msix:
930 /* The number of MSI-X vectors should equal the number of channels */
931 msixcnt = device->common.chancnt;
932 for (i = 0; i < msixcnt; i++)
933 device->msix_entries[i].entry = i;
934
Dan Williamse6c0b692009-09-08 17:29:44 -0700935 err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
Shannon Nelson3e037452007-10-16 01:27:40 -0700936 if (err < 0)
937 goto msi;
938 if (err > 0)
939 goto msix_single_vector;
940
941 for (i = 0; i < msixcnt; i++) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700942 msix = &device->msix_entries[i];
Dan Williamsdcbc8532009-07-28 14:44:50 -0700943 chan = ioat_chan_by_index(device, i);
Dan Williamse6c0b692009-09-08 17:29:44 -0700944 err = devm_request_irq(dev, msix->vector,
945 ioat_dma_do_interrupt_msix, 0,
Dan Williamsdcbc8532009-07-28 14:44:50 -0700946 "ioat-msix", chan);
Shannon Nelson3e037452007-10-16 01:27:40 -0700947 if (err) {
948 for (j = 0; j < i; j++) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700949 msix = &device->msix_entries[j];
Dan Williamsdcbc8532009-07-28 14:44:50 -0700950 chan = ioat_chan_by_index(device, j);
951 devm_free_irq(dev, msix->vector, chan);
Shannon Nelson3e037452007-10-16 01:27:40 -0700952 }
953 goto msix_single_vector;
954 }
955 }
956 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
Shannon Nelson3e037452007-10-16 01:27:40 -0700957 goto done;
958
959msix_single_vector:
Dan Williamse6c0b692009-09-08 17:29:44 -0700960 msix = &device->msix_entries[0];
961 msix->entry = 0;
962 err = pci_enable_msix(pdev, device->msix_entries, 1);
Shannon Nelson3e037452007-10-16 01:27:40 -0700963 if (err)
964 goto msi;
965
Dan Williamse6c0b692009-09-08 17:29:44 -0700966 err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
967 "ioat-msix", device);
Shannon Nelson3e037452007-10-16 01:27:40 -0700968 if (err) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700969 pci_disable_msix(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -0700970 goto msi;
971 }
Shannon Nelson3e037452007-10-16 01:27:40 -0700972 goto done;
973
974msi:
Dan Williamse6c0b692009-09-08 17:29:44 -0700975 err = pci_enable_msi(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -0700976 if (err)
977 goto intx;
978
Dan Williamse6c0b692009-09-08 17:29:44 -0700979 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
980 "ioat-msi", device);
Shannon Nelson3e037452007-10-16 01:27:40 -0700981 if (err) {
Dan Williamse6c0b692009-09-08 17:29:44 -0700982 pci_disable_msi(pdev);
Shannon Nelson3e037452007-10-16 01:27:40 -0700983 goto intx;
984 }
Shannon Nelson3e037452007-10-16 01:27:40 -0700985 goto done;
986
987intx:
Dan Williamse6c0b692009-09-08 17:29:44 -0700988 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
989 IRQF_SHARED, "ioat-intx", device);
Shannon Nelson3e037452007-10-16 01:27:40 -0700990 if (err)
991 goto err_no_irq;
Shannon Nelson3e037452007-10-16 01:27:40 -0700992
993done:
Dan Williamsf2427e22009-07-28 14:42:38 -0700994 if (device->intr_quirk)
995 device->intr_quirk(device);
Shannon Nelson3e037452007-10-16 01:27:40 -0700996 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
997 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
998 return 0;
999
1000err_no_irq:
1001 /* Disable all interrupt generation */
1002 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
Dan Williamse6c0b692009-09-08 17:29:44 -07001003 dev_err(dev, "no usable interrupts\n");
1004 return err;
Shannon Nelson3e037452007-10-16 01:27:40 -07001005}
1006
Dan Williamse6c0b692009-09-08 17:29:44 -07001007static void ioat_disable_interrupts(struct ioatdma_device *device)
Shannon Nelson3e037452007-10-16 01:27:40 -07001008{
Shannon Nelson3e037452007-10-16 01:27:40 -07001009 /* Disable all interrupt generation */
1010 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
Shannon Nelson3e037452007-10-16 01:27:40 -07001011}
1012
Dan Williams345d8522009-09-08 12:01:30 -07001013int __devinit ioat_probe(struct ioatdma_device *device)
Chris Leech0bbd5f42006-05-23 17:35:34 -07001014{
Dan Williamsf2427e22009-07-28 14:42:38 -07001015 int err = -ENODEV;
1016 struct dma_device *dma = &device->common;
1017 struct pci_dev *pdev = device->pdev;
Dan Williamse6c0b692009-09-08 17:29:44 -07001018 struct device *dev = &pdev->dev;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001019
1020 /* DMA coherent memory pool for DMA descriptor allocations */
1021 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
Shannon Nelson8ab89562007-10-16 01:27:39 -07001022 sizeof(struct ioat_dma_descriptor),
1023 64, 0);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001024 if (!device->dma_pool) {
1025 err = -ENOMEM;
1026 goto err_dma_pool;
1027 }
1028
Shannon Nelson43d6e362007-10-16 01:27:39 -07001029 device->completion_pool = pci_pool_create("completion_pool", pdev,
1030 sizeof(u64), SMP_CACHE_BYTES,
1031 SMP_CACHE_BYTES);
Dan Williams5cbafa62009-08-26 13:01:44 -07001032
Chris Leech0bbd5f42006-05-23 17:35:34 -07001033 if (!device->completion_pool) {
1034 err = -ENOMEM;
1035 goto err_completion_pool;
1036 }
1037
Dan Williams5cbafa62009-08-26 13:01:44 -07001038 device->enumerate_channels(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001039
Dan Williamsf2427e22009-07-28 14:42:38 -07001040 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
Dan Williamsf2427e22009-07-28 14:42:38 -07001041 dma->dev = &pdev->dev;
Shannon Nelson7bb67c12007-11-14 16:59:51 -08001042
Dan Williamse6c0b692009-09-08 17:29:44 -07001043 dev_err(dev, "Intel(R) I/OAT DMA Engine found,"
Shannon Nelson5149fd02007-10-18 03:07:13 -07001044 " %d channels, device version 0x%02x, driver version %s\n",
Dan Williamsbc3c7022009-07-28 14:33:42 -07001045 dma->chancnt, device->version, IOAT_DMA_VERSION);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001046
Dan Williamsbc3c7022009-07-28 14:33:42 -07001047 if (!dma->chancnt) {
Dan Williamse6c0b692009-09-08 17:29:44 -07001048 dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: "
Maciej Sosnowski8b794b12009-02-26 11:04:54 +01001049 "zero channels detected\n");
1050 goto err_setup_interrupts;
1051 }
1052
Shannon Nelson3e037452007-10-16 01:27:40 -07001053 err = ioat_dma_setup_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001054 if (err)
Shannon Nelson3e037452007-10-16 01:27:40 -07001055 goto err_setup_interrupts;
Shannon Nelson8ab89562007-10-16 01:27:39 -07001056
Shannon Nelson3e037452007-10-16 01:27:40 -07001057 err = ioat_dma_self_test(device);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001058 if (err)
1059 goto err_self_test;
1060
Dan Williamsf2427e22009-07-28 14:42:38 -07001061 return 0;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001062
1063err_self_test:
Dan Williamse6c0b692009-09-08 17:29:44 -07001064 ioat_disable_interrupts(device);
Shannon Nelson3e037452007-10-16 01:27:40 -07001065err_setup_interrupts:
Chris Leech0bbd5f42006-05-23 17:35:34 -07001066 pci_pool_destroy(device->completion_pool);
1067err_completion_pool:
1068 pci_pool_destroy(device->dma_pool);
1069err_dma_pool:
Dan Williamsf2427e22009-07-28 14:42:38 -07001070 return err;
1071}
1072
Dan Williams345d8522009-09-08 12:01:30 -07001073int __devinit ioat_register(struct ioatdma_device *device)
Dan Williamsf2427e22009-07-28 14:42:38 -07001074{
1075 int err = dma_async_device_register(&device->common);
1076
1077 if (err) {
1078 ioat_disable_interrupts(device);
1079 pci_pool_destroy(device->completion_pool);
1080 pci_pool_destroy(device->dma_pool);
1081 }
1082
1083 return err;
1084}
1085
1086/* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1087static void ioat1_intr_quirk(struct ioatdma_device *device)
1088{
1089 struct pci_dev *pdev = device->pdev;
1090 u32 dmactrl;
1091
1092 pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1093 if (pdev->msi_enabled)
1094 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1095 else
1096 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1097 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1098}
1099
Dan Williams345d8522009-09-08 12:01:30 -07001100int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
Dan Williamsf2427e22009-07-28 14:42:38 -07001101{
1102 struct pci_dev *pdev = device->pdev;
1103 struct dma_device *dma;
1104 int err;
1105
1106 device->intr_quirk = ioat1_intr_quirk;
Dan Williams5cbafa62009-08-26 13:01:44 -07001107 device->enumerate_channels = ioat1_enumerate_channels;
Dan Williamsf2427e22009-07-28 14:42:38 -07001108 dma = &device->common;
1109 dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1110 dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
Dan Williams5cbafa62009-08-26 13:01:44 -07001111 dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1112 dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1113 dma->device_is_tx_complete = ioat1_dma_is_complete;
Dan Williamsf2427e22009-07-28 14:42:38 -07001114
1115 err = ioat_probe(device);
1116 if (err)
1117 return err;
1118 ioat_set_tcp_copy_break(4096);
1119 err = ioat_register(device);
1120 if (err)
1121 return err;
1122 if (dca)
1123 device->dca = ioat_dca_init(pdev, device->reg_base);
1124
Dan Williamsf2427e22009-07-28 14:42:38 -07001125 return err;
1126}
1127
Dan Williams345d8522009-09-08 12:01:30 -07001128void __devexit ioat_dma_remove(struct ioatdma_device *device)
Dan Aloni428ed602007-03-08 09:57:36 -08001129{
Dan Williamsbc3c7022009-07-28 14:33:42 -07001130 struct dma_device *dma = &device->common;
Chris Leech0bbd5f42006-05-23 17:35:34 -07001131
Dan Williamse6c0b692009-09-08 17:29:44 -07001132 ioat_disable_interrupts(device);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001133
Dan Williamsbc3c7022009-07-28 14:33:42 -07001134 dma_async_device_unregister(dma);
Shannon Nelsondfe22992007-10-18 03:07:13 -07001135
Chris Leech0bbd5f42006-05-23 17:35:34 -07001136 pci_pool_destroy(device->dma_pool);
1137 pci_pool_destroy(device->completion_pool);
Shannon Nelson8ab89562007-10-16 01:27:39 -07001138
Dan Williamsdcbc8532009-07-28 14:44:50 -07001139 INIT_LIST_HEAD(&dma->channels);
Chris Leech0bbd5f42006-05-23 17:35:34 -07001140}