| Clemens Ladisch | a9d3cc4 | 2008-04-07 10:29:44 +0200 | [diff] [blame] | 1 | /* register 1 */ |
| 2 | #define CS4398_REV_MASK 0x07 |
| 3 | #define CS4398_PART_MASK 0xf8 |
| 4 | #define CS4398_PART_CS4398 0x70 |
| 5 | /* register 2 */ |
| 6 | #define CS4398_FM_MASK 0x03 |
| 7 | #define CS4398_FM_SINGLE 0x00 |
| 8 | #define CS4398_FM_DOUBLE 0x01 |
| 9 | #define CS4398_FM_QUAD 0x02 |
| 10 | #define CS4398_FM_DSD 0x03 |
| 11 | #define CS4398_DEM_MASK 0x0c |
| 12 | #define CS4398_DEM_NONE 0x00 |
| 13 | #define CS4398_DEM_44100 0x04 |
| 14 | #define CS4398_DEM_48000 0x08 |
| 15 | #define CS4398_DEM_32000 0x0c |
| 16 | #define CS4398_DIF_MASK 0x70 |
| 17 | #define CS4398_DIF_LJUST 0x00 |
| 18 | #define CS4398_DIF_I2S 0x10 |
| 19 | #define CS4398_DIF_RJUST_16 0x20 |
| 20 | #define CS4398_DIF_RJUST_24 0x30 |
| 21 | #define CS4398_DIF_RJUST_20 0x40 |
| 22 | #define CS4398_DIF_RJUST_18 0x50 |
| 23 | #define CS4398_DSD_SRC 0x80 |
| 24 | /* register 3 */ |
| 25 | #define CS4398_ATAPI_MASK 0x1f |
| 26 | #define CS4398_ATAPI_B_MUTE 0x00 |
| 27 | #define CS4398_ATAPI_B_R 0x01 |
| 28 | #define CS4398_ATAPI_B_L 0x02 |
| 29 | #define CS4398_ATAPI_B_LR 0x03 |
| 30 | #define CS4398_ATAPI_A_MUTE 0x00 |
| 31 | #define CS4398_ATAPI_A_R 0x04 |
| 32 | #define CS4398_ATAPI_A_L 0x08 |
| 33 | #define CS4398_ATAPI_A_LR 0x0c |
| 34 | #define CS4398_ATAPI_MIX_LR_VOL 0x10 |
| 35 | #define CS4398_INVERT_B 0x20 |
| 36 | #define CS4398_INVERT_A 0x40 |
| 37 | #define CS4398_VOL_B_EQ_A 0x80 |
| 38 | /* register 4 */ |
| 39 | #define CS4398_MUTEP_MASK 0x03 |
| 40 | #define CS4398_MUTEP_AUTO 0x00 |
| 41 | #define CS4398_MUTEP_LOW 0x02 |
| 42 | #define CS4398_MUTEP_HIGH 0x03 |
| 43 | #define CS4398_MUTE_B 0x08 |
| 44 | #define CS4398_MUTE_A 0x10 |
| 45 | #define CS4398_MUTEC_A_EQ_B 0x20 |
| 46 | #define CS4398_DAMUTE 0x40 |
| 47 | #define CS4398_PAMUTE 0x80 |
| 48 | /* register 5 */ |
| 49 | #define CS4398_VOL_A_MASK 0xff |
| 50 | /* register 6 */ |
| 51 | #define CS4398_VOL_B_MASK 0xff |
| 52 | /* register 7 */ |
| 53 | #define CS4398_DIR_DSD 0x01 |
| 54 | #define CS4398_FILT_SEL 0x04 |
| 55 | #define CS4398_RMP_DN 0x10 |
| 56 | #define CS4398_RMP_UP 0x20 |
| 57 | #define CS4398_ZERO_CROSS 0x40 |
| 58 | #define CS4398_SOFT_RAMP 0x80 |
| 59 | /* register 8 */ |
| 60 | #define CS4398_MCLKDIV3 0x08 |
| 61 | #define CS4398_MCLKDIV2 0x10 |
| 62 | #define CS4398_FREEZE 0x20 |
| 63 | #define CS4398_CPEN 0x40 |
| 64 | #define CS4398_PDN 0x80 |
| 65 | /* register 9 */ |
| 66 | #define CS4398_DSD_PM_EN 0x01 |
| 67 | #define CS4398_DSD_PM_MODE 0x02 |
| 68 | #define CS4398_INVALID_DSD 0x04 |
| 69 | #define CS4398_STATIC_DSD 0x08 |