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review.evervolv.com / android_kernel_oneplus_msm8996 / ec05fcf679fe97994b5355ebf1d7d8cb0020eacf / . / arch / arm / boot / dts / kirkwood.dtsi
blob: 2c738d9dc82a17143b1578c3867dbf87e304cef0 [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]4 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]5 interrupt-parent = <&intc>;
6
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 };
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]11 intc: interrupt-controller {
12 compatible = "marvell,orion-intc", "marvell,intc";
13 interrupt-controller;
14 #interrupt-cells = <1>;
15 reg = <0xf1020204 0x04>,
16 <0xf1020214 0x04>;
17 };
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]18
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]19 ocp@f1000000 {
20 compatible = "simple-bus";
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]21 ranges = <0x00000000 0xf1000000 0x4000000
22 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]23 #address-cells = <1>;
24 #size-cells = <1>;
25
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]26 core_clk: core-clocks@10030 {
27 compatible = "marvell,kirkwood-core-clock";
28 reg = <0x10030 0x4>;
29 #clock-cells = <1>;
30 };
31
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]32 gpio0: gpio@10100 {
33 compatible = "marvell,orion-gpio";
34 #gpio-cells = <2>;
35 gpio-controller;
36 reg = <0x10100 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]37 ngpios = <32>;
38 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]39 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]40 interrupts = <35>, <36>, <37>, <38>;
41 };
42
43 gpio1: gpio@10140 {
44 compatible = "marvell,orion-gpio";
45 #gpio-cells = <2>;
46 gpio-controller;
47 reg = <0x10140 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]48 ngpios = <18>;
49 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]50 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]51 interrupts = <39>, <40>, <41>;
52 };
53
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]54 serial@12000 {
55 compatible = "ns16550a";
56 reg = <0x12000 0x100>;
57 reg-shift = <2>;
58 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]59 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]60 /* set clock-frequency in board dts */
61 status = "disabled";
62 };
63
64 serial@12100 {
65 compatible = "ns16550a";
66 reg = <0x12100 0x100>;
67 reg-shift = <2>;
68 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]69 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]70 /* set clock-frequency in board dts */
71 status = "disabled";
72 };
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]73
74 rtc@10300 {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]75 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]76 reg = <0x10300 0x20>;
77 interrupts = <53>;
78 };
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]79
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]80 spi@10600 {
81 compatible = "marvell,orion-spi";
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <0>;
85 interrupts = <23>;
86 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]87 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]88 status = "disabled";
89 };
90
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]91 gate_clk: clock-gating-control@2011c {
92 compatible = "marvell,kirkwood-gating-clock";
93 reg = <0x2011c 0x4>;
94 clocks = <&core_clk 0>;
95 #clock-cells = <1>;
96 };
97
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]98 wdt@20300 {
99 compatible = "marvell,orion-wdt";
100 reg = <0x20300 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]101 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]102 status = "okay";
103 };
104
Andrew Lunnc896ed02012-11-18 11:44:57 +0100[diff] [blame]105 xor@60800 {
106 compatible = "marvell,orion-xor";
107 reg = <0x60800 0x100
108 0x60A00 0x100>;
109 status = "okay";
110 clocks = <&gate_clk 8>;
111
112 xor00 {
113 interrupts = <5>;
114 dmacap,memcpy;
115 dmacap,xor;
116 };
117 xor01 {
118 interrupts = <6>;
119 dmacap,memcpy;
120 dmacap,xor;
121 dmacap,memset;
122 };
123 };
124
125 xor@60900 {
126 compatible = "marvell,orion-xor";
127 reg = <0x60900 0x100
128 0xd0B00 0x100>;
129 status = "okay";
130 clocks = <&gate_clk 16>;
131
132 xor00 {
133 interrupts = <7>;
134 dmacap,memcpy;
135 dmacap,xor;
136 };
137 xor01 {
138 interrupts = <8>;
139 dmacap,memcpy;
140 dmacap,xor;
141 dmacap,memset;
142 };
143 };
144
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]145 ehci@50000 {
146 compatible = "marvell,orion-ehci";
147 reg = <0x50000 0x1000>;
148 interrupts = <19>;
Andrew Lunn53dfa8e2013-01-06 11:10:34 +0100[diff] [blame]149 clocks = <&gate_clk 3>;
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]150 status = "okay";
151 };
152
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]153 sata@80000 {
154 compatible = "marvell,orion-sata";
155 reg = <0x80000 0x5000>;
156 interrupts = <21>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]157 clocks = <&gate_clk 14>, <&gate_clk 15>;
158 clock-names = "0", "1";
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]159 status = "disabled";
160 };
161
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]162 nand@3000000 {
163 #address-cells = <1>;
164 #size-cells = <1>;
165 cle = <0>;
166 ale = <1>;
167 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]168 compatible = "marvell,orion-nand";
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]169 reg = <0x3000000 0x400>;
170 chip-delay = <25>;
171 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]172 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]173 status = "disabled";
174 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]175
176 i2c@11000 {
177 compatible = "marvell,mv64xxx-i2c";
178 reg = <0x11000 0x20>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 interrupts = <29>;
182 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]183 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]184 status = "disabled";
185 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]186
187 crypto@30000 {
188 compatible = "marvell,orion-crypto";
189 reg = <0x30000 0x10000>,
190 <0xf5000000 0x800>;
191 reg-names = "regs", "sram";
192 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]193 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]194 status = "okay";
195 };
Thomas Petazzoniec05fcf2012-12-21 15:49:10 +0100[diff] [blame^]196
197 mvsdio@90000 {
198 compatible = "marvell,orion-sdio";
199 reg = <0x90000 0x200>;
200 interrupts = <28>;
201 clocks = <&gate_clk 4>;
202 status = "disabled";
203 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]204 };
205};