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Hong Xucce783c2012-04-17 14:26:29 +08001/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 gpio0 = &pioA;
24 gpio1 = &pioB;
25 gpio2 = &pioC;
26 gpio3 = &pioD;
27 tcb0 = &tcb0;
28 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020029 i2c0 = &i2c0;
30 i2c1 = &i2c1;
Hong Xucce783c2012-04-17 14:26:29 +080031 };
32 cpus {
33 cpu@0 {
34 compatible = "arm,arm926ejs";
35 };
36 };
37
38 memory {
39 reg = <0x20000000 0x10000000>;
40 };
41
42 ahb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 apb {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020055 #interrupt-cells = <3>;
Hong Xucce783c2012-04-17 14:26:29 +080056 compatible = "atmel,at91rm9200-aic";
57 interrupt-controller;
58 reg = <0xfffff000 0x200>;
59 };
60
61 ramc0: ramc@ffffe800 {
62 compatible = "atmel,at91sam9g45-ddramc";
63 reg = <0xffffe800 0x200>;
64 };
65
66 pmc: pmc@fffffc00 {
67 compatible = "atmel,at91rm9200-pmc";
68 reg = <0xfffffc00 0x100>;
69 };
70
71 rstc@fffffe00 {
72 compatible = "atmel,at91sam9g45-rstc";
73 reg = <0xfffffe00 0x10>;
74 };
75
76 pit: timer@fffffe30 {
77 compatible = "atmel,at91sam9260-pit";
78 reg = <0xfffffe30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020079 interrupts = <1 4 7>;
Hong Xucce783c2012-04-17 14:26:29 +080080 };
81
82 shdwc@fffffe10 {
83 compatible = "atmel,at91sam9x5-shdwc";
84 reg = <0xfffffe10 0x10>;
85 };
86
87 tcb0: timer@f8008000 {
88 compatible = "atmel,at91sam9x5-tcb";
89 reg = <0xf8008000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020090 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +080091 };
92
93 tcb1: timer@f800c000 {
94 compatible = "atmel,at91sam9x5-tcb";
95 reg = <0xf800c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020096 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +080097 };
98
99 dma: dma-controller@ffffec00 {
100 compatible = "atmel,at91sam9g45-dma";
101 reg = <0xffffec00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200102 interrupts = <20 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800103 };
104
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800105 pinctrl@fffff400 {
106 #address-cells = <1>;
107 #size-cells = <1>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800108 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800109 ranges = <0xfffff400 0xfffff400 0x800>;
Hong Xucce783c2012-04-17 14:26:29 +0800110
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800111 atmel,mux-mask = <
112 /* A B C */
113 0xffffffff 0xffe07983 0x00000000 /* pioA */
114 0x00040000 0x00047e0f 0x00000000 /* pioB */
115 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
116 0x003fffff 0x003f8000 0x00000000 /* pioD */
117 >;
118
119 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800120 dbgu {
121 pinctrl_dbgu: dbgu-0 {
122 atmel,pins =
123 <0 9 0x1 0x0 /* PA9 periph A */
124 0 10 0x1 0x1>; /* PA10 periph with pullup */
125 };
126 };
127
128 uart0 {
129 pinctrl_uart0: uart0-0 {
130 atmel,pins =
131 <0 1 0x1 0x1 /* PA1 periph A with pullup */
132 0 0 0x1 0x0>; /* PA0 periph A */
133 };
134
135 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
136 atmel,pins =
137 <0 2 0x1 0x0 /* PA2 periph A */
138 0 3 0x1 0x0>; /* PA3 periph A */
139 };
140 };
141
142 uart1 {
143 pinctrl_uart1: uart1-0 {
144 atmel,pins =
145 <0 6 0x1 0x1 /* PA6 periph A with pullup */
146 0 5 0x1 0x0>; /* PA5 periph A */
147 };
148 };
149
150 uart2 {
151 pinctrl_uart2: uart2-0 {
152 atmel,pins =
153 <0 8 0x1 0x1 /* PA8 periph A with pullup */
154 0 7 0x1 0x0>; /* PA7 periph A */
155 };
156
157 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
158 atmel,pins =
159 <1 0 0x2 0x0 /* PB0 periph B */
160 1 1 0x2 0x0>; /* PB1 periph B */
161 };
162 };
163
164 uart3 {
165 pinctrl_uart3: uart3-0 {
166 atmel,pins =
167 <2 23 0x2 0x1 /* PC23 periph B with pullup */
168 2 22 0x2 0x0>; /* PC22 periph B */
169 };
170
171 pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
172 atmel,pins =
173 <2 24 0x2 0x0 /* PC24 periph B */
174 2 25 0x2 0x0>; /* PC25 periph B */
175 };
176 };
177
178 usart0 {
179 pinctrl_usart0: usart0-0 {
180 atmel,pins =
181 <2 9 0x3 0x1 /* PC9 periph C with pullup */
182 2 8 0x3 0x0>; /* PC8 periph C */
183 };
184 };
185
186 usart1 {
187 pinctrl_usart1: usart1-0 {
188 atmel,pins =
189 <2 16 0x3 0x1 /* PC17 periph C with pullup */
190 2 17 0x3 0x0>; /* PC16 periph C */
191 };
192 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800193
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800194 pioA: gpio@fffff400 {
195 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
196 reg = <0xfffff400 0x200>;
197 interrupts = <2 4 1>;
198 #gpio-cells = <2>;
199 gpio-controller;
200 interrupt-controller;
201 #interrupt-cells = <2>;
202 };
Hong Xucce783c2012-04-17 14:26:29 +0800203
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800204 pioB: gpio@fffff600 {
205 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
206 reg = <0xfffff600 0x200>;
207 interrupts = <2 4 1>;
208 #gpio-cells = <2>;
209 gpio-controller;
210 interrupt-controller;
211 #interrupt-cells = <2>;
212 };
Hong Xucce783c2012-04-17 14:26:29 +0800213
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800214 pioC: gpio@fffff800 {
215 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
216 reg = <0xfffff800 0x200>;
217 interrupts = <3 4 1>;
218 #gpio-cells = <2>;
219 gpio-controller;
220 interrupt-controller;
221 #interrupt-cells = <2>;
222 };
223
224 pioD: gpio@fffffa00 {
225 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
226 reg = <0xfffffa00 0x200>;
227 interrupts = <3 4 1>;
228 #gpio-cells = <2>;
229 gpio-controller;
230 interrupt-controller;
231 #interrupt-cells = <2>;
232 };
Hong Xucce783c2012-04-17 14:26:29 +0800233 };
234
235 dbgu: serial@fffff200 {
236 compatible = "atmel,at91sam9260-usart";
237 reg = <0xfffff200 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200238 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_dbgu>;
Hong Xucce783c2012-04-17 14:26:29 +0800241 status = "disabled";
242 };
243
244 usart0: serial@f801c000 {
245 compatible = "atmel,at91sam9260-usart";
246 reg = <0xf801c000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200247 interrupts = <5 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800248 atmel,use-dma-rx;
249 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_uart0>;
Hong Xucce783c2012-04-17 14:26:29 +0800252 status = "disabled";
253 };
254
255 usart1: serial@f8020000 {
256 compatible = "atmel,at91sam9260-usart";
257 reg = <0xf8020000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200258 interrupts = <6 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800259 atmel,use-dma-rx;
260 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_uart1>;
Hong Xucce783c2012-04-17 14:26:29 +0800263 status = "disabled";
264 };
265
266 usart2: serial@f8024000 {
267 compatible = "atmel,at91sam9260-usart";
268 reg = <0xf8024000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200269 interrupts = <7 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800270 atmel,use-dma-rx;
271 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_uart2>;
Hong Xucce783c2012-04-17 14:26:29 +0800274 status = "disabled";
275 };
276
277 usart3: serial@f8028000 {
278 compatible = "atmel,at91sam9260-usart";
279 reg = <0xf8028000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200280 interrupts = <8 4 5>;
Hong Xucce783c2012-04-17 14:26:29 +0800281 atmel,use-dma-rx;
282 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_uart3>;
Hong Xucce783c2012-04-17 14:26:29 +0800285 status = "disabled";
286 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200287
288 i2c0: i2c@f8010000 {
289 compatible = "atmel,at91sam9x5-i2c";
290 reg = <0xf8010000 0x100>;
291 interrupts = <9 4 6>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 status = "disabled";
295 };
296
297 i2c1: i2c@f8014000 {
298 compatible = "atmel,at91sam9x5-i2c";
299 reg = <0xf8014000 0x100>;
300 interrupts = <10 4 6>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 status = "disabled";
304 };
Hong Xucce783c2012-04-17 14:26:29 +0800305 };
306
307 nand0: nand@40000000 {
308 compatible = "atmel,at91rm9200-nand";
309 #address-cells = <1>;
310 #size-cells = <1>;
311 reg = < 0x40000000 0x10000000
312 0xffffe000 0x00000600
313 0xffffe600 0x00000200
314 0x00100000 0x00100000
315 >;
316 atmel,nand-addr-offset = <21>;
317 atmel,nand-cmd-offset = <22>;
318 gpios = <&pioD 5 0
319 &pioD 4 0
320 0
321 >;
322 status = "disabled";
323 };
324
325 usb0: ohci@00500000 {
326 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
327 reg = <0x00500000 0x00100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200328 interrupts = <22 4 2>;
Hong Xucce783c2012-04-17 14:26:29 +0800329 status = "disabled";
330 };
331 };
332
333 i2c@0 {
334 compatible = "i2c-gpio";
335 gpios = <&pioA 30 0 /* sda */
336 &pioA 31 0 /* scl */
337 >;
338 i2c-gpio,sda-open-drain;
339 i2c-gpio,scl-open-drain;
340 i2c-gpio,delay-us = <2>; /* ~100 kHz */
341 #address-cells = <1>;
342 #size-cells = <0>;
343 status = "disabled";
344 };
345};