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review.evervolv.com / android_kernel_oneplus_msm8996 / ed39097c2ad97688d2734600ca20b7d66c311b92 / . / arch / arm / boot / dts / tegra30.dtsi
blob: 1f7f49aabe6b21d8cc53a3618ed978a6218273dd [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame^]7 host1x {
8 compatible = "nvidia,tegra30-host1x", "simple-bus";
9 reg = <0x50000000 0x00024000>;
10 interrupts = <0 65 0x04 /* mpcore syncpt */
11 0 67 0x04>; /* mpcore general */
12
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 ranges = <0x54000000 0x54000000 0x04000000>;
17
18 mpe {
19 compatible = "nvidia,tegra30-mpe";
20 reg = <0x54040000 0x00040000>;
21 interrupts = <0 68 0x04>;
22 };
23
24 vi {
25 compatible = "nvidia,tegra30-vi";
26 reg = <0x54080000 0x00040000>;
27 interrupts = <0 69 0x04>;
28 };
29
30 epp {
31 compatible = "nvidia,tegra30-epp";
32 reg = <0x540c0000 0x00040000>;
33 interrupts = <0 70 0x04>;
34 };
35
36 isp {
37 compatible = "nvidia,tegra30-isp";
38 reg = <0x54100000 0x00040000>;
39 interrupts = <0 71 0x04>;
40 };
41
42 gr2d {
43 compatible = "nvidia,tegra30-gr2d";
44 reg = <0x54140000 0x00040000>;
45 interrupts = <0 72 0x04>;
46 };
47
48 gr3d {
49 compatible = "nvidia,tegra30-gr3d";
50 reg = <0x54180000 0x00040000>;
51 };
52
53 dc@54200000 {
54 compatible = "nvidia,tegra30-dc";
55 reg = <0x54200000 0x00040000>;
56 interrupts = <0 73 0x04>;
57
58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra30-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <0 74 0x04>;
67
68 rgb {
69 status = "disabled";
70 };
71 };
72
73 hdmi {
74 compatible = "nvidia,tegra30-hdmi";
75 reg = <0x54280000 0x00040000>;
76 interrupts = <0 75 0x04>;
77 status = "disabled";
78 };
79
80 tvo {
81 compatible = "nvidia,tegra30-tvo";
82 reg = <0x542c0000 0x00040000>;
83 interrupts = <0 76 0x04>;
84 status = "disabled";
85 };
86
87 dsi {
88 compatible = "nvidia,tegra30-dsi";
89 reg = <0x54300000 0x00040000>;
90 status = "disabled";
91 };
92 };
93
Joseph Lo5ab134a2012-10-29 18:25:45 +0800[diff] [blame]94 cache-controller@50043000 {
95 compatible = "arm,pl310-cache";
96 reg = <0x50043000 0x1000>;
97 arm,data-latency = <6 6 2>;
98 arm,tag-latency = <5 5 2>;
99 cache-unified;
100 cache-level = <2>;
101 };
102
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]103 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]104 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]105 reg = <0x50041000 0x1000
106 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]107 interrupt-controller;
108 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]109 };
110
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]111 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]112 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
113 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]114 interrupts = <0 104 0x04
115 0 105 0x04
116 0 106 0x04
117 0 107 0x04
118 0 108 0x04
119 0 109 0x04
120 0 110 0x04
121 0 111 0x04
122 0 112 0x04
123 0 113 0x04
124 0 114 0x04
125 0 115 0x04
126 0 116 0x04
127 0 117 0x04
128 0 118 0x04
129 0 119 0x04
130 0 128 0x04
131 0 129 0x04
132 0 130 0x04
133 0 131 0x04
134 0 132 0x04
135 0 133 0x04
136 0 134 0x04
137 0 135 0x04
138 0 136 0x04
139 0 137 0x04
140 0 138 0x04
141 0 139 0x04
142 0 140 0x04
143 0 141 0x04
144 0 142 0x04
145 0 143 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]146 };
147
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]148 ahb: ahb {
149 compatible = "nvidia,tegra30-ahb";
150 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
151 };
152
153 gpio: gpio {
154 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
155 reg = <0x6000d000 0x1000>;
156 interrupts = <0 32 0x04
157 0 33 0x04
158 0 34 0x04
159 0 35 0x04
160 0 55 0x04
161 0 87 0x04
162 0 89 0x04
163 0 125 0x04>;
164 #gpio-cells = <2>;
165 gpio-controller;
166 #interrupt-cells = <2>;
167 interrupt-controller;
168 };
169
170 pinmux: pinmux {
171 compatible = "nvidia,tegra30-pinmux";
172 reg = <0x70000868 0xd0 /* Pad control registers */
173 0x70003000 0x3e0>; /* Mux registers */
174 };
175
176 serial@70006000 {
177 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
178 reg = <0x70006000 0x40>;
179 reg-shift = <2>;
180 interrupts = <0 36 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]181 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]182 };
183
184 serial@70006040 {
185 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
186 reg = <0x70006040 0x40>;
187 reg-shift = <2>;
188 interrupts = <0 37 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]189 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]190 };
191
192 serial@70006200 {
193 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
194 reg = <0x70006200 0x100>;
195 reg-shift = <2>;
196 interrupts = <0 46 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]197 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]198 };
199
200 serial@70006300 {
201 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
202 reg = <0x70006300 0x100>;
203 reg-shift = <2>;
204 interrupts = <0 90 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]205 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]206 };
207
208 serial@70006400 {
209 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
210 reg = <0x70006400 0x100>;
211 reg-shift = <2>;
212 interrupts = <0 91 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]213 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]214 };
215
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]216 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]217 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
218 reg = <0x7000a000 0x100>;
219 #pwm-cells = <2>;
220 };
221
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]222 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]223 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]224 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]225 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]226 #address-cells = <1>;
227 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]228 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]229 };
230
231 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]232 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]233 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]234 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]235 #address-cells = <1>;
236 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]237 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]238 };
239
240 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]241 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]242 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]243 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]244 #address-cells = <1>;
245 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]246 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]247 };
248
249 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]250 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
251 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]252 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]253 #address-cells = <1>;
254 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]255 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]256 };
257
258 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]259 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]260 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]261 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]262 #address-cells = <1>;
263 #size-cells = <0>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]264 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]265 };
266
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]267 spi@7000d400 {
268 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
269 reg = <0x7000d400 0x200>;
270 interrupts = <0 59 0x04>;
271 nvidia,dma-request-selector = <&apbdma 15>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 status = "disabled";
275 };
276
277 spi@7000d600 {
278 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
279 reg = <0x7000d600 0x200>;
280 interrupts = <0 82 0x04>;
281 nvidia,dma-request-selector = <&apbdma 16>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 status = "disabled";
285 };
286
287 spi@7000d800 {
288 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
289 reg = <0x7000d480 0x200>;
290 interrupts = <0 83 0x04>;
291 nvidia,dma-request-selector = <&apbdma 17>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 status = "disabled";
295 };
296
297 spi@7000da00 {
298 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
299 reg = <0x7000da00 0x200>;
300 interrupts = <0 93 0x04>;
301 nvidia,dma-request-selector = <&apbdma 18>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 status = "disabled";
305 };
306
307 spi@7000dc00 {
308 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
309 reg = <0x7000dc00 0x200>;
310 interrupts = <0 94 0x04>;
311 nvidia,dma-request-selector = <&apbdma 27>;
312 #address-cells = <1>;
313 #size-cells = <0>;
314 status = "disabled";
315 };
316
317 spi@7000de00 {
318 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
319 reg = <0x7000de00 0x200>;
320 interrupts = <0 79 0x04>;
321 nvidia,dma-request-selector = <&apbdma 28>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 status = "disabled";
325 };
326
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]327 pmc {
328 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
329 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]330 };
331
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]332 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]333 compatible = "nvidia,tegra30-mc";
334 reg = <0x7000f000 0x010
335 0x7000f03c 0x1b4
336 0x7000f200 0x028
337 0x7000f284 0x17c>;
338 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]339 };
340
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]341 smmu {
342 compatible = "nvidia,tegra30-smmu";
343 reg = <0x7000f010 0x02c
344 0x7000f1f0 0x010
345 0x7000f228 0x05c>;
346 nvidia,#asids = <4>; /* # of ASIDs */
347 dma-window = <0 0x40000000>; /* IOVA start & length */
348 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]349 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]350
351 ahub {
352 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]353 reg = <0x70080000 0x200
354 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]355 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]356 nvidia,dma-request-selector = <&apbdma 1>;
357
358 ranges;
359 #address-cells = <1>;
360 #size-cells = <1>;
361
362 tegra_i2s0: i2s@70080300 {
363 compatible = "nvidia,tegra30-i2s";
364 reg = <0x70080300 0x100>;
365 nvidia,ahub-cif-ids = <4 4>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]366 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]367 };
368
369 tegra_i2s1: i2s@70080400 {
370 compatible = "nvidia,tegra30-i2s";
371 reg = <0x70080400 0x100>;
372 nvidia,ahub-cif-ids = <5 5>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]373 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]374 };
375
376 tegra_i2s2: i2s@70080500 {
377 compatible = "nvidia,tegra30-i2s";
378 reg = <0x70080500 0x100>;
379 nvidia,ahub-cif-ids = <6 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]380 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]381 };
382
383 tegra_i2s3: i2s@70080600 {
384 compatible = "nvidia,tegra30-i2s";
385 reg = <0x70080600 0x100>;
386 nvidia,ahub-cif-ids = <7 7>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]387 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]388 };
389
390 tegra_i2s4: i2s@70080700 {
391 compatible = "nvidia,tegra30-i2s";
392 reg = <0x70080700 0x100>;
393 nvidia,ahub-cif-ids = <8 8>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]394 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]395 };
396 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]397
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]398 sdhci@78000000 {
399 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
400 reg = <0x78000000 0x200>;
401 interrupts = <0 14 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]402 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]403 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]404
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]405 sdhci@78000200 {
406 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
407 reg = <0x78000200 0x200>;
408 interrupts = <0 15 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]409 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]410 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]411
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]412 sdhci@78000400 {
413 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
414 reg = <0x78000400 0x200>;
415 interrupts = <0 19 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]416 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]417 };
418
419 sdhci@78000600 {
420 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
421 reg = <0x78000600 0x200>;
422 interrupts = <0 31 0x04>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]423 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]424 };
425
426 pmu {
427 compatible = "arm,cortex-a9-pmu";
428 interrupts = <0 144 0x04
429 0 145 0x04
430 0 146 0x04
431 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]432 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]433};