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review.evervolv.com / android_kernel_oneplus_msm8996 / ed73c63ad9ac7cb5b6cb58802a4948adebe39d99 / . / arch / arm / boot / dts / imx51.dtsi
blob: 32b85a836fb5cf992130ce5b2f9d506b93d9d1bd [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx51-pinfunc.h"
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]25 };
26
27 tzic: tz-interrupt-controller@e0000000 {
28 compatible = "fsl,imx51-tzic", "fsl,tzic";
29 interrupt-controller;
30 #interrupt-cells = <1>;
31 reg = <0xe0000000 0x4000>;
32 };
33
34 clocks {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 ckil {
39 compatible = "fsl,imx-ckil", "fixed-clock";
40 clock-frequency = <32768>;
41 };
42
43 ckih1 {
44 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>;
46 };
47
48 ckih2 {
49 compatible = "fsl,imx-ckih2", "fixed-clock";
50 clock-frequency = <0>;
51 };
52
53 osc {
54 compatible = "fsl,imx-osc", "fixed-clock";
55 clock-frequency = <24000000>;
56 };
57 };
58
59 soc {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "simple-bus";
63 interrupt-parent = <&tzic>;
64 ranges;
65
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]66 ipu: ipu@40000000 {
67 #crtc-cells = <1>;
68 compatible = "fsl,imx51-ipu";
69 reg = <0x40000000 0x20000000>;
70 interrupts = <11 10>;
71 };
72
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]73 aips@70000000 { /* AIPS1 */
74 compatible = "fsl,aips-bus", "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <1>;
77 reg = <0x70000000 0x10000000>;
78 ranges;
79
80 spba@70000000 {
81 compatible = "fsl,spba-bus", "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 reg = <0x70000000 0x40000>;
85 ranges;
86
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]87 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]88 compatible = "fsl,imx51-esdhc";
89 reg = <0x70004000 0x4000>;
90 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]91 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
92 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]93 status = "disabled";
94 };
95
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]96 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]97 compatible = "fsl,imx51-esdhc";
98 reg = <0x70008000 0x4000>;
99 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]100 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
101 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]102 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]103 status = "disabled";
104 };
105
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]106 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]107 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
108 reg = <0x7000c000 0x4000>;
109 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]110 clocks = <&clks 32>, <&clks 33>;
111 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]112 status = "disabled";
113 };
114
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]115 ecspi1: ecspi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,imx51-ecspi";
119 reg = <0x70010000 0x4000>;
120 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]121 clocks = <&clks 51>, <&clks 52>;
122 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]123 status = "disabled";
124 };
125
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]126 ssi2: ssi@70014000 {
127 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
128 reg = <0x70014000 0x4000>;
129 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]130 clocks = <&clks 49>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]131 fsl,fifo-depth = <15>;
132 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
133 status = "disabled";
134 };
135
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]136 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]137 compatible = "fsl,imx51-esdhc";
138 reg = <0x70020000 0x4000>;
139 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]140 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
141 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]142 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]143 status = "disabled";
144 };
145
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]146 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]147 compatible = "fsl,imx51-esdhc";
148 reg = <0x70024000 0x4000>;
149 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]150 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
151 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]152 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]153 status = "disabled";
154 };
155 };
156
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]157 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]158 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
159 reg = <0x73f80000 0x0200>;
160 interrupts = <18>;
161 status = "disabled";
162 };
163
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]164 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]165 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
166 reg = <0x73f80200 0x0200>;
167 interrupts = <14>;
168 status = "disabled";
169 };
170
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]171 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]172 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
173 reg = <0x73f80400 0x0200>;
174 interrupts = <16>;
175 status = "disabled";
176 };
177
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]178 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]179 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
180 reg = <0x73f80600 0x0200>;
181 interrupts = <17>;
182 status = "disabled";
183 };
184
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]185 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]186 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]187 reg = <0x73f84000 0x4000>;
188 interrupts = <50 51>;
189 gpio-controller;
190 #gpio-cells = <2>;
191 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]192 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]193 };
194
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]195 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]196 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]197 reg = <0x73f88000 0x4000>;
198 interrupts = <52 53>;
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]202 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]203 };
204
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]205 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]206 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]207 reg = <0x73f8c000 0x4000>;
208 interrupts = <54 55>;
209 gpio-controller;
210 #gpio-cells = <2>;
211 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]212 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]213 };
214
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]215 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]216 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]217 reg = <0x73f90000 0x4000>;
218 interrupts = <56 57>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]222 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]223 };
224
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]225 kpp: kpp@73f94000 {
226 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
227 reg = <0x73f94000 0x4000>;
228 interrupts = <60>;
229 clocks = <&clks 0>;
230 status = "disabled";
231 };
232
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]233 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]234 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
235 reg = <0x73f98000 0x4000>;
236 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]237 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]238 };
239
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]240 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]241 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
242 reg = <0x73f9c000 0x4000>;
243 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]244 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]245 status = "disabled";
246 };
247
Sascha Hauered73c632013-03-14 13:08:59 +0100[diff] [blame^]248 gpt: timer@73fa0000 {
249 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
250 reg = <0x73fa0000 0x4000>;
251 interrupts = <39>;
252 clocks = <&clks 36>, <&clks 41>;
253 clock-names = "ipg", "per";
254 };
255
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]256 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]257 compatible = "fsl,imx51-iomuxc";
258 reg = <0x73fa8000 0x4000>;
259
260 audmux {
261 pinctrl_audmux_1: audmuxgrp-1 {
262 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]263 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
264 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
265 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
266 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]267 >;
268 };
269 };
270
271 fec {
272 pinctrl_fec_1: fecgrp-1 {
273 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]274 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
275 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
276 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
277 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
278 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
279 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
280 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
281 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
282 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
283 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
284 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
285 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
286 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
287 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
288 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
289 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
290 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]291 >;
292 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]293
294 pinctrl_fec_2: fecgrp-2 {
295 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]296 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
297 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
298 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
299 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
300 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
301 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
302 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
303 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
304 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
305 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
306 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
307 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
308 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
309 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
310 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
311 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
312 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
313 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]314 >;
315 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]316 };
317
318 ecspi1 {
319 pinctrl_ecspi1_1: ecspi1grp-1 {
320 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]321 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
322 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
323 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]324 >;
325 };
326 };
327
Gwenhael Goavec-Meroua15ac4a2013-03-09 14:59:08 +0100[diff] [blame]328 ecspi2 {
329 pinctrl_ecspi2_1: ecspi2grp-1 {
330 fsl,pins = <
331 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
332 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
333 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
334 >;
335 };
336 };
337
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]338 esdhc1 {
339 pinctrl_esdhc1_1: esdhc1grp-1 {
340 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]341 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
342 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
343 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
344 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
345 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
346 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]347 >;
348 };
349 };
350
351 esdhc2 {
352 pinctrl_esdhc2_1: esdhc2grp-1 {
353 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]354 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
355 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
356 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
357 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
358 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
359 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]360 >;
361 };
362 };
363
364 i2c2 {
365 pinctrl_i2c2_1: i2c2grp-1 {
366 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]367 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
368 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]369 >;
370 };
Gwenhael Goavec-Merou52c9aa92013-03-09 15:04:19 +0100[diff] [blame]371
372 pinctrl_i2c2_2: i2c2grp-2 {
373 fsl,pins = <
374 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
375 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
376 >;
377 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]378 };
379
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]380 ipu_disp1 {
381 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
382 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]383 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
384 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
385 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
386 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
387 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
388 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
389 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
390 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
391 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
392 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
393 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
394 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
395 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
396 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
397 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
398 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
399 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
400 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
401 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
402 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
403 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
404 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
405 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
406 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
407 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
408 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]409 >;
410 };
411 };
412
413 ipu_disp2 {
414 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
415 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]416 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
417 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
418 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
419 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
420 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
421 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
422 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
423 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
424 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
425 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
426 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
427 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
428 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
429 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
430 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
431 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
432 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
433 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
434 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
435 MX51_PAD_DI_GP4__DI2_PIN15 0x5
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]436 >;
437 };
438 };
439
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]440 uart1 {
441 pinctrl_uart1_1: uart1grp-1 {
442 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]443 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
444 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
445 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
446 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]447 >;
448 };
449 };
450
451 uart2 {
452 pinctrl_uart2_1: uart2grp-1 {
453 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]454 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
455 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]456 >;
457 };
458 };
459
460 uart3 {
461 pinctrl_uart3_1: uart3grp-1 {
462 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]463 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
464 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
465 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
466 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]467 >;
468 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]469
470 pinctrl_uart3_2: uart3grp-2 {
471 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]472 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
473 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]474 >;
475 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]476 };
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]477
478 kpp {
479 pinctrl_kpp_1: kppgrp-1 {
480 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]481 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
482 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
483 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
484 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
485 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
486 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
487 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
488 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
Liu Ying60125552013-01-03 20:37:33 +0800[diff] [blame]489 >;
490 };
491 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]492 };
493
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]494 pwm1: pwm@73fb4000 {
495 #pwm-cells = <2>;
496 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
497 reg = <0x73fb4000 0x4000>;
498 clocks = <&clks 37>, <&clks 38>;
499 clock-names = "ipg", "per";
500 interrupts = <61>;
501 };
502
503 pwm2: pwm@73fb8000 {
504 #pwm-cells = <2>;
505 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
506 reg = <0x73fb8000 0x4000>;
507 clocks = <&clks 39>, <&clks 40>;
508 clock-names = "ipg", "per";
509 interrupts = <94>;
510 };
511
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]512 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]513 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
514 reg = <0x73fbc000 0x4000>;
515 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]516 clocks = <&clks 28>, <&clks 29>;
517 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]518 status = "disabled";
519 };
520
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]521 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]522 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
523 reg = <0x73fc0000 0x4000>;
524 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]525 clocks = <&clks 30>, <&clks 31>;
526 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]527 status = "disabled";
528 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]529
530 clks: ccm@73fd4000{
531 compatible = "fsl,imx51-ccm";
532 reg = <0x73fd4000 0x4000>;
533 interrupts = <0 71 0x04 0 72 0x04>;
534 #clock-cells = <1>;
535 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]536 };
537
538 aips@80000000 { /* AIPS2 */
539 compatible = "fsl,aips-bus", "simple-bus";
540 #address-cells = <1>;
541 #size-cells = <1>;
542 reg = <0x80000000 0x10000000>;
543 ranges;
544
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]545 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]546 #address-cells = <1>;
547 #size-cells = <0>;
548 compatible = "fsl,imx51-ecspi";
549 reg = <0x83fac000 0x4000>;
550 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]551 clocks = <&clks 53>, <&clks 54>;
552 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]553 status = "disabled";
554 };
555
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]556 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]557 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
558 reg = <0x83fb0000 0x4000>;
559 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]560 clocks = <&clks 56>, <&clks 56>;
561 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]562 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]563 };
564
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]565 cspi: cspi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]566 #address-cells = <1>;
567 #size-cells = <0>;
568 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
569 reg = <0x83fc0000 0x4000>;
570 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]571 clocks = <&clks 55>, <&clks 0>;
572 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]573 status = "disabled";
574 };
575
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]576 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]577 #address-cells = <1>;
578 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]579 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]580 reg = <0x83fc4000 0x4000>;
581 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]582 clocks = <&clks 35>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]583 status = "disabled";
584 };
585
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]586 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]587 #address-cells = <1>;
588 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]589 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]590 reg = <0x83fc8000 0x4000>;
591 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]592 clocks = <&clks 34>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]593 status = "disabled";
594 };
595
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]596 ssi1: ssi@83fcc000 {
597 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
598 reg = <0x83fcc000 0x4000>;
599 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]600 clocks = <&clks 48>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]601 fsl,fifo-depth = <15>;
602 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
603 status = "disabled";
604 };
605
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]606 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]607 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
608 reg = <0x83fd0000 0x4000>;
609 status = "disabled";
610 };
611
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]612 nfc: nand@83fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]613 compatible = "fsl,imx51-nand";
614 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
615 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]616 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]617 status = "disabled";
618 };
619
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]620 ssi3: ssi@83fe8000 {
621 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
622 reg = <0x83fe8000 0x4000>;
623 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]624 clocks = <&clks 50>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]625 fsl,fifo-depth = <15>;
626 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
627 status = "disabled";
628 };
629
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]630 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]631 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
632 reg = <0x83fec000 0x4000>;
633 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]634 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
635 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]636 status = "disabled";
637 };
638 };
639 };
640};