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review.evervolv.com / android_kernel_oneplus_msm8996 / ed8a2798f6cff0dc68ca7d5800279525aa310fd0 / . / arch / m68k / include / asm / m532xsim.h
blob: 29b66e21413a7170177e74129165325e6090e96f [file] [log] [blame]
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]1/****************************************************************************/
2
3/*
4 * m532xsim.h -- ColdFire 5329 registers
5 */
6
7/****************************************************************************/
8#ifndef m532xsim_h
9#define m532xsim_h
10/****************************************************************************/
11
Greg Ungerer733f31b2010-11-02 17:40:37 +1000[diff] [blame]12#define CPU_NAME "COLDFIRE(m532x)"
13#define CPU_INSTR_PER_JIFFY 3
Greg Ungererce3de782011-03-09 14:19:08 +1000[diff] [blame]14#define MCF_BUSCLK (MCF_CLK / 3)
Greg Ungerer7fc82b62010-11-02 17:13:27 +1000[diff] [blame]15
Greg Ungerer278c2cb2010-11-09 10:19:45 +1000[diff] [blame]16#include <asm/m53xxacr.h>
17
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]18#define MCF_REG32(x) (*(volatile unsigned long *)(x))
19#define MCF_REG16(x) (*(volatile unsigned short *)(x))
20#define MCF_REG08(x) (*(volatile unsigned char *)(x))
21
22#define MCFINT_VECBASE 64
23#define MCFINT_UART0 26 /* Interrupt number for UART0 */
24#define MCFINT_UART1 27 /* Interrupt number for UART1 */
Greg Ungerere2545b62009-02-12 16:02:05 +1000[diff] [blame]25#define MCFINT_UART2 28 /* Interrupt number for UART2 */
Steven King91d60412010-01-22 12:43:03 -0800[diff] [blame]26#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
Greg Ungerer50469542011-12-24 10:23:01 +1000[diff] [blame]27#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
28#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
29#define MCFINT_FECENTC0 42 /* Interrupt number for FEC */
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]30
Greg Ungerer35b7cf22011-12-24 00:41:07 +1000[diff] [blame]31#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
32#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
33#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
34
Greg Ungerer50469542011-12-24 10:23:01 +1000[diff] [blame]35#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
36#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
37#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
38
Greg Ungerered8a2792011-12-24 12:44:45 +1000[diff] [blame^]39#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
40
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]41#define MCF_WTM_WCR MCF_REG16(0xFC098000)
42
43/*
44 * Define the 532x SIM register set addresses.
45 */
46#define MCFSIM_IPRL 0xFC048004
47#define MCFSIM_IPRH 0xFC048000
48#define MCFSIM_IPR MCFSIM_IPRL
49#define MCFSIM_IMRL 0xFC04800C
50#define MCFSIM_IMRH 0xFC048008
51#define MCFSIM_IMR MCFSIM_IMRL
52#define MCFSIM_ICR0 0xFC048040
53#define MCFSIM_ICR1 0xFC048041
54#define MCFSIM_ICR2 0xFC048042
55#define MCFSIM_ICR3 0xFC048043
56#define MCFSIM_ICR4 0xFC048044
57#define MCFSIM_ICR5 0xFC048045
58#define MCFSIM_ICR6 0xFC048046
59#define MCFSIM_ICR7 0xFC048047
60#define MCFSIM_ICR8 0xFC048048
61#define MCFSIM_ICR9 0xFC048049
62#define MCFSIM_ICR10 0xFC04804A
63#define MCFSIM_ICR11 0xFC04804B
64
65/*
66 * Some symbol defines for the above...
67 */
68#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
69#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
70#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
71#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
72#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
73#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
74#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
75#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
76#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
77
78
Greg Ungerer277c5e32009-04-29 12:07:13 +1000[diff] [blame]79#define MCFINTC0_SIMR 0xFC04801C
80#define MCFINTC0_CIMR 0xFC04801D
81#define MCFINTC0_ICR0 0xFC048040
82#define MCFINTC1_SIMR 0xFC04C01C
83#define MCFINTC1_CIMR 0xFC04C01D
84#define MCFINTC1_ICR0 0xFC04C040
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]85
86#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
87#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
88
Greg Ungererf6a66272009-05-19 15:00:01 +1000[diff] [blame]89/*
90 * Define system peripheral IRQ usage.
91 */
92#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
93#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]94
95/*
Greg Ungerer57015422010-11-03 12:50:30 +1000[diff] [blame]96 * UART module.
97 */
Greg Ungerer35b7cf22011-12-24 00:41:07 +1000[diff] [blame]98#define MCFUART_BASE0 0xFC060000 /* Base address of UART1 */
99#define MCFUART_BASE1 0xFC064000 /* Base address of UART2 */
100#define MCFUART_BASE2 0xFC068000 /* Base address of UART3 */
Greg Ungerer57015422010-11-03 12:50:30 +1000[diff] [blame]101
Greg Ungerer58f0ac92011-03-09 09:57:14 +1000[diff] [blame]102/*
Greg Ungerer50469542011-12-24 10:23:01 +1000[diff] [blame]103 * FEC module.
104 */
105#define MCFFEC_BASE0 0xFC030000 /* Base address of FEC0 */
106#define MCFFEC_SIZE0 0x800 /* Size of FEC0 region */
107
108/*
Greg Ungerered8a2792011-12-24 12:44:45 +1000[diff] [blame^]109 * QSPI module.
110 */
111#define MCFQSPI_BASE 0xFC058000 /* Base address of QSPI */
112#define MCFQSPI_SIZE 0x40 /* Size of QSPI region */
113
114#define MCFQSPI_CS0 84
115#define MCFQSPI_CS1 85
116#define MCFQSPI_CS2 86
117
118/*
Greg Ungerer58f0ac92011-03-09 09:57:14 +1000[diff] [blame]119 * Timer module.
120 */
121#define MCFTIMER_BASE1 0xFC070000 /* Base address of TIMER1 */
122#define MCFTIMER_BASE2 0xFC074000 /* Base address of TIMER2 */
123#define MCFTIMER_BASE3 0xFC078000 /* Base address of TIMER3 */
124#define MCFTIMER_BASE4 0xFC07C000 /* Base address of TIMER4 */
125
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]126/*********************************************************************
127 *
Greg Ungerer384feb92009-04-30 22:03:43 +1000[diff] [blame]128 * Reset Controller Module
129 *
130 *********************************************************************/
131
132#define MCF_RCR 0xFC0A0000
133#define MCF_RSR 0xFC0A0001
134
135#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
136#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
137
138/*********************************************************************
139 *
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]140 * Inter-IC (I2C) Module
141 *
142 *********************************************************************/
143
144/* Read/Write access macros for general use */
145#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
146#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
147#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
148#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
149#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
150
151/* Bit level definitions and macros */
152#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
153
154#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
155
156#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
157#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
158#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
159#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
160#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
161#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
162
163#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
164#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
165#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
166#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
167#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
168#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
169#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
170
171#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
172
173
174/*
175 * The M5329EVB board needs a help getting its devices initialized
176 * at kernel start time if dBUG doesn't set it up (for example
177 * it is not used), so we need to do it manually.
178 */
179#ifdef __ASSEMBLER__
180.macro m5329EVB_setup
181 movel #0xFC098000, %a7
182 movel #0x0, (%a7)
183#define CORE_SRAM 0x80000000
184#define CORE_SRAM_SIZE 0x8000
185 movel #CORE_SRAM, %d0
186 addl #0x221, %d0
187 movec %d0,%RAMBAR1
188 movel #CORE_SRAM, %sp
189 addl #CORE_SRAM_SIZE, %sp
190 jsr sysinit
191.endm
192#define PLATFORM_SETUP m5329EVB_setup
193
194#endif /* __ASSEMBLER__ */
195
196/*********************************************************************
197 *
198 * Chip Configuration Module (CCM)
199 *
200 *********************************************************************/
201
202/* Register read/write macros */
203#define MCF_CCM_CCR MCF_REG16(0xFC0A0004)
204#define MCF_CCM_RCON MCF_REG16(0xFC0A0008)
205#define MCF_CCM_CIR MCF_REG16(0xFC0A000A)
206#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010)
207#define MCF_CCM_CDR MCF_REG16(0xFC0A0012)
208#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014)
209#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016)
210
211/* Bit definitions and macros for MCF_CCM_CCR */
212#define MCF_CCM_CCR_RESERVED (0x0001)
213#define MCF_CCM_CCR_PLL_MODE (0x0003)
214#define MCF_CCM_CCR_OSC_MODE (0x0005)
215#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
216#define MCF_CCM_CCR_LOAD (0x0021)
217#define MCF_CCM_CCR_LIMP (0x0041)
218#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
219
220/* Bit definitions and macros for MCF_CCM_RCON */
221#define MCF_CCM_RCON_RESERVED (0x0001)
222#define MCF_CCM_RCON_PLL_MODE (0x0003)
223#define MCF_CCM_RCON_OSC_MODE (0x0005)
224#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
225#define MCF_CCM_RCON_LOAD (0x0021)
226#define MCF_CCM_RCON_LIMP (0x0041)
227#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
228
229/* Bit definitions and macros for MCF_CCM_CIR */
230#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0)
231#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
232
233/* Bit definitions and macros for MCF_CCM_MISCCR */
234#define MCF_CCM_MISCCR_USBSRC (0x0001)
235#define MCF_CCM_MISCCR_USBDIV (0x0002)
236#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
237#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
238#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
239#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
240#define MCF_CCM_MISCCR_LCD_CHEN (0x0100)
241#define MCF_CCM_MISCCR_LIMP (0x1000)
242#define MCF_CCM_MISCCR_PLL_LOCK (0x2000)
243
244/* Bit definitions and macros for MCF_CCM_CDR */
245#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0)
246#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
247
248/* Bit definitions and macros for MCF_CCM_UHCSR */
249#define MCF_CCM_UHCSR_XPDE (0x0001)
250#define MCF_CCM_UHCSR_UHMIE (0x0002)
251#define MCF_CCM_UHCSR_WKUP (0x0004)
252#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
253
254/* Bit definitions and macros for MCF_CCM_UOCSR */
255#define MCF_CCM_UOCSR_XPDE (0x0001)
256#define MCF_CCM_UOCSR_UOMIE (0x0002)
257#define MCF_CCM_UOCSR_WKUP (0x0004)
258#define MCF_CCM_UOCSR_PWRFLT (0x0008)
259#define MCF_CCM_UOCSR_SEND (0x0010)
260#define MCF_CCM_UOCSR_VVLD (0x0020)
261#define MCF_CCM_UOCSR_BVLD (0x0040)
262#define MCF_CCM_UOCSR_AVLD (0x0080)
263#define MCF_CCM_UOCSR_DPPU (0x0100)
264#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
265#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
266#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
267#define MCF_CCM_UOCSR_DMPD (0x1000)
268#define MCF_CCM_UOCSR_DPPD (0x2000)
269#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
270
271/*********************************************************************
272 *
273 * DMA Timers (DTIM)
274 *
275 *********************************************************************/
276
277/* Register read/write macros */
278#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000)
279#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002)
280#define MCF_DTIM0_DTER MCF_REG08(0xFC070003)
281#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004)
282#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008)
283#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C)
284#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000)
285#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002)
286#define MCF_DTIM1_DTER MCF_REG08(0xFC074003)
287#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004)
288#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008)
289#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C)
290#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000)
291#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002)
292#define MCF_DTIM2_DTER MCF_REG08(0xFC078003)
293#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004)
294#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008)
295#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C)
296#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000)
297#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002)
298#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003)
299#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004)
300#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008)
301#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C)
302#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000))
303#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000))
304#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000))
305#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000))
306#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000))
307#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000))
308
309/* Bit definitions and macros for MCF_DTIM_DTMR */
310#define MCF_DTIM_DTMR_RST (0x0001)
311#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1)
312#define MCF_DTIM_DTMR_FRR (0x0008)
313#define MCF_DTIM_DTMR_ORRI (0x0010)
314#define MCF_DTIM_DTMR_OM (0x0020)
315#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6)
316#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8)
317#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
318#define MCF_DTIM_DTMR_CE_FALL (0x0080)
319#define MCF_DTIM_DTMR_CE_RISE (0x0040)
320#define MCF_DTIM_DTMR_CE_NONE (0x0000)
321#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
322#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
323#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
324#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
325
326/* Bit definitions and macros for MCF_DTIM_DTXMR */
327#define MCF_DTIM_DTXMR_MODE16 (0x01)
328#define MCF_DTIM_DTXMR_DMAEN (0x80)
329
330/* Bit definitions and macros for MCF_DTIM_DTER */
331#define MCF_DTIM_DTER_CAP (0x01)
332#define MCF_DTIM_DTER_REF (0x02)
333
334/* Bit definitions and macros for MCF_DTIM_DTRR */
335#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
336
337/* Bit definitions and macros for MCF_DTIM_DTCR */
338#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
339
340/* Bit definitions and macros for MCF_DTIM_DTCN */
341#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
342
343/*********************************************************************
344 *
345 * FlexBus Chip Selects (FBCS)
346 *
347 *********************************************************************/
348
349/* Register read/write macros */
350#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000)
351#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004)
352#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008)
353#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C)
354#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010)
355#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014)
356#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018)
357#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C)
358#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020)
359#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024)
360#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028)
361#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C)
362#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030)
363#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034)
364#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038)
365#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C)
366#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040)
367#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044)
368#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
369#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
370#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
371
372/* Bit definitions and macros for MCF_FBCS_CSAR */
373#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
374
375/* Bit definitions and macros for MCF_FBCS_CSMR */
376#define MCF_FBCS_CSMR_V (0x00000001)
377#define MCF_FBCS_CSMR_WP (0x00000100)
378#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16)
379#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
380#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
381#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
382#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
383#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
384#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
385#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
386#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
387#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
388#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
389#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
390#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
391#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
392#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
393#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
394#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
395#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
396#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
397#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
398
399/* Bit definitions and macros for MCF_FBCS_CSCR */
400#define MCF_FBCS_CSCR_BSTW (0x00000008)
401#define MCF_FBCS_CSCR_BSTR (0x00000010)
402#define MCF_FBCS_CSCR_BEM (0x00000020)
403#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6)
404#define MCF_FBCS_CSCR_AA (0x00000100)
405#define MCF_FBCS_CSCR_SBM (0x00000200)
406#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10)
407#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
408#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
409#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20)
410#define MCF_FBCS_CSCR_SWSEN (0x00800000)
411#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
412#define MCF_FBCS_CSCR_PS_8 (0x0040)
413#define MCF_FBCS_CSCR_PS_16 (0x0080)
414#define MCF_FBCS_CSCR_PS_32 (0x0000)
415
416/*********************************************************************
417 *
418 * General Purpose I/O (GPIO)
419 *
420 *********************************************************************/
421
422/* Register read/write macros */
sfking@fdwdc.com7846fe82009-06-19 18:11:10 -0700[diff] [blame]423#define MCFGPIO_PODR_FECH (0xFC0A4000)
424#define MCFGPIO_PODR_FECL (0xFC0A4001)
425#define MCFGPIO_PODR_SSI (0xFC0A4002)
426#define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
427#define MCFGPIO_PODR_BE (0xFC0A4004)
428#define MCFGPIO_PODR_CS (0xFC0A4005)
429#define MCFGPIO_PODR_PWM (0xFC0A4006)
430#define MCFGPIO_PODR_FECI2C (0xFC0A4007)
431#define MCFGPIO_PODR_UART (0xFC0A4009)
432#define MCFGPIO_PODR_QSPI (0xFC0A400A)
433#define MCFGPIO_PODR_TIMER (0xFC0A400B)
434#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
435#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
436#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
437#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
438#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
439#define MCFGPIO_PDDR_FECH (0xFC0A4014)
440#define MCFGPIO_PDDR_FECL (0xFC0A4015)
441#define MCFGPIO_PDDR_SSI (0xFC0A4016)
442#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
443#define MCFGPIO_PDDR_BE (0xFC0A4018)
444#define MCFGPIO_PDDR_CS (0xFC0A4019)
445#define MCFGPIO_PDDR_PWM (0xFC0A401A)
446#define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
447#define MCFGPIO_PDDR_UART (0xFC0A401C)
448#define MCFGPIO_PDDR_QSPI (0xFC0A401E)
449#define MCFGPIO_PDDR_TIMER (0xFC0A401F)
450#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
451#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
452#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
453#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
454#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
455#define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
456#define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
457#define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
458#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
459#define MCFGPIO_PPDSDR_BE (0xFC0A402C)
460#define MCFGPIO_PPDSDR_CS (0xFC0A402D)
461#define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
462#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
463#define MCFGPIO_PPDSDR_UART (0xFC0A4031)
464#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
465#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
466#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
467#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
468#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
469#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
470#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
471#define MCFGPIO_PCLRR_FECH (0xFC0A403C)
472#define MCFGPIO_PCLRR_FECL (0xFC0A403D)
473#define MCFGPIO_PCLRR_SSI (0xFC0A403E)
474#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
475#define MCFGPIO_PCLRR_BE (0xFC0A4040)
476#define MCFGPIO_PCLRR_CS (0xFC0A4041)
477#define MCFGPIO_PCLRR_PWM (0xFC0A4042)
478#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
479#define MCFGPIO_PCLRR_UART (0xFC0A4045)
480#define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
481#define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
482#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
483#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
484#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
485#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
486#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]487#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050)
488#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051)
489#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052)
490#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053)
491#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054)
492#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055)
493#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056)
494#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058)
495#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A)
496#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C)
497#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D)
498#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E)
499#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060)
500#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064)
501#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065)
502#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068)
503#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069)
504#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A)
505#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B)
506#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C)
507#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D)
508#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E)
509#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F)
510#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070)
511#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071)
512#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072)
513
514/* Bit definitions and macros for MCF_GPIO_PODR_FECH */
515#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01)
516#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02)
517#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04)
518#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08)
519#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10)
520#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20)
521#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40)
522#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80)
523
524/* Bit definitions and macros for MCF_GPIO_PODR_FECL */
525#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01)
526#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02)
527#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04)
528#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08)
529#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10)
530#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20)
531#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40)
532#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80)
533
534/* Bit definitions and macros for MCF_GPIO_PODR_SSI */
535#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01)
536#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02)
537#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04)
538#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08)
539#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10)
540
541/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */
542#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01)
543#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02)
544#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04)
545#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08)
546
547/* Bit definitions and macros for MCF_GPIO_PODR_BE */
548#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01)
549#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02)
550#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04)
551#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08)
552
553/* Bit definitions and macros for MCF_GPIO_PODR_CS */
554#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02)
555#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04)
556#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08)
557#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10)
558#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20)
559
560/* Bit definitions and macros for MCF_GPIO_PODR_PWM */
561#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04)
562#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08)
563#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10)
564#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20)
565
566/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
567#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01)
568#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02)
569#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04)
570#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08)
571
572/* Bit definitions and macros for MCF_GPIO_PODR_UART */
573#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01)
574#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02)
575#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04)
576#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08)
577#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10)
578#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20)
579#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40)
580#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80)
581
582/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */
583#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01)
584#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02)
585#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04)
586#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08)
587#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10)
588#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20)
589
590/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */
591#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01)
592#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02)
593#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04)
594#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08)
595
596/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */
597#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01)
598#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02)
599
600/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */
601#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01)
602#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02)
603#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04)
604#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08)
605#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10)
606#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20)
607#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40)
608#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80)
609
610/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */
611#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01)
612#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02)
613#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04)
614#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08)
615#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10)
616#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20)
617#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40)
618#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80)
619
620/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */
621#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01)
622
623/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */
624#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01)
625#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02)
626#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04)
627#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08)
628#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10)
629#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20)
630#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40)
631#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80)
632
633/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */
634#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01)
635#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02)
636#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04)
637#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08)
638#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10)
639#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20)
640#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40)
641#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80)
642
643/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */
644#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01)
645#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02)
646#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04)
647#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08)
648#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10)
649#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20)
650#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40)
651#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80)
652
653/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */
654#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01)
655#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02)
656#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04)
657#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08)
658#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10)
659
660/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */
661#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01)
662#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02)
663#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04)
664#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08)
665
666/* Bit definitions and macros for MCF_GPIO_PDDR_BE */
667#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01)
668#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02)
669#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04)
670#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08)
671
672/* Bit definitions and macros for MCF_GPIO_PDDR_CS */
673#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02)
674#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04)
675#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08)
676#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10)
677#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20)
678
679/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */
680#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04)
681#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08)
682#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10)
683#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20)
684
685/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
686#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01)
687#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02)
688#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04)
689#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08)
690
691/* Bit definitions and macros for MCF_GPIO_PDDR_UART */
692#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01)
693#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02)
694#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04)
695#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08)
696#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10)
697#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20)
698#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40)
699#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80)
700
701/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */
702#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01)
703#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02)
704#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04)
705#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08)
706#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10)
707#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20)
708
709/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */
710#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01)
711#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02)
712#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04)
713#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08)
714
715/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */
716#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01)
717#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02)
718
719/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */
720#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01)
721#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02)
722#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04)
723#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08)
724#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10)
725#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20)
726#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40)
727#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80)
728
729/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */
730#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01)
731#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02)
732#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04)
733#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08)
734#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10)
735#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20)
736#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40)
737#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80)
738
739/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */
740#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01)
741
742/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */
743#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01)
744#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02)
745#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04)
746#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08)
747#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10)
748#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20)
749#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40)
750#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80)
751
752/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */
753#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01)
754#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02)
755#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04)
756#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08)
757#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10)
758#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20)
759#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40)
760#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80)
761
762/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */
763#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01)
764#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02)
765#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04)
766#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08)
767#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10)
768#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20)
769#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40)
770#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80)
771
772/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */
773#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01)
774#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02)
775#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04)
776#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08)
777#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10)
778
779/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */
780#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01)
781#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02)
782#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04)
783#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08)
784
785/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */
786#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01)
787#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02)
788#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04)
789#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08)
790
791/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */
792#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02)
793#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04)
794#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08)
795#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10)
796#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20)
797
798/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */
799#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04)
800#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08)
801#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10)
802#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20)
803
804/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
805#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01)
806#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02)
807#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04)
808#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08)
809
810/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */
811#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01)
812#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02)
813#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04)
814#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08)
815#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10)
816#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20)
817#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40)
818#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80)
819
820/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */
821#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01)
822#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02)
823#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04)
824#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08)
825#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10)
826#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20)
827
828/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */
829#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01)
830#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02)
831#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04)
832#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08)
833
834/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */
835#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01)
836#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02)
837
838/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */
839#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01)
840#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02)
841#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04)
842#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08)
843#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10)
844#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20)
845#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40)
846#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80)
847
848/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */
849#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01)
850#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02)
851#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04)
852#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08)
853#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10)
854#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20)
855#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40)
856#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80)
857
858/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */
859#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01)
860
861/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */
862#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01)
863#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02)
864#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04)
865#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08)
866#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10)
867#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20)
868#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40)
869#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80)
870
871/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */
872#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01)
873#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02)
874#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04)
875#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08)
876#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10)
877#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20)
878#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40)
879#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80)
880
881/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */
882#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01)
883#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02)
884#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04)
885#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08)
886#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10)
887#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20)
888#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40)
889#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80)
890
891/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */
892#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01)
893#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02)
894#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04)
895#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08)
896#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10)
897
898/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */
899#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01)
900#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02)
901#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04)
902#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08)
903
904/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */
905#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01)
906#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02)
907#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04)
908#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08)
909
910/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */
911#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02)
912#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04)
913#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08)
914#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10)
915#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20)
916
917/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */
918#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04)
919#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08)
920#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10)
921#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20)
922
923/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
924#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01)
925#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02)
926#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04)
927#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08)
928
929/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */
930#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01)
931#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02)
932#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04)
933#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08)
934#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10)
935#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20)
936#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40)
937#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80)
938
939/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */
940#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01)
941#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02)
942#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04)
943#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08)
944#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10)
945#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20)
946
947/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */
948#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01)
949#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02)
950#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04)
951#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08)
952
953/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */
954#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01)
955#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02)
956
957/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */
958#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01)
959#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02)
960#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04)
961#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08)
962#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10)
963#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20)
964#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40)
965#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80)
966
967/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */
968#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01)
969#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02)
970#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04)
971#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08)
972#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10)
973#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20)
974#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40)
975#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80)
976
977/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */
978#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
979
980/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */
981#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01)
982#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02)
983#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04)
984#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08)
985#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10)
986#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20)
987#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40)
988#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80)
989
990/* Bit definitions and macros for MCF_GPIO_PAR_FEC */
991#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0)
992#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2)
993#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00)
994#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04)
995#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C)
996#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00)
997#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01)
998#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03)
999
1000/* Bit definitions and macros for MCF_GPIO_PAR_PWM */
1001#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0)
1002#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2)
1003#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10)
1004#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20)
1005
1006/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */
1007#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3)
1008#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20)
1009#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40)
1010#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80)
1011#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00)
1012#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80)
1013#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00)
1014#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40)
1015#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00)
1016#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20)
1017#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00)
1018#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10)
1019#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18)
1020
1021/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */
1022#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0)
1023#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2)
1024#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4)
1025#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6)
1026#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00)
1027#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40)
1028#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80)
1029#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0)
1030#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00)
1031#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10)
1032#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20)
1033#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30)
1034#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00)
1035#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
1036#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C)
1037#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00)
1038#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
1039#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03)
1040
1041/* Bit definitions and macros for MCF_GPIO_PAR_BE */
1042#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01)
1043#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02)
1044#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04)
1045#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08)
1046
1047/* Bit definitions and macros for MCF_GPIO_PAR_CS */
1048#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02)
1049#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
1050#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08)
1051#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10)
1052#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20)
1053#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00)
1054#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01)
1055#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03)
1056
1057/* Bit definitions and macros for MCF_GPIO_PAR_SSI */
1058#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080)
1059#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8)
1060#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10)
1061#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12)
1062#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14)
1063
1064/* Bit definitions and macros for MCF_GPIO_PAR_UART */
1065#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001)
1066#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002)
1067#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004)
1068#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008)
1069#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4)
1070#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6)
1071#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8)
1072#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10)
1073#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000)
1074#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800)
1075#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400)
1076#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00)
1077#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000)
1078#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200)
1079#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100)
1080#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300)
1081#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000)
1082#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080)
1083#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040)
1084#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0)
1085#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000)
1086#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020)
1087#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010)
1088#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030)
1089
1090/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */
1091#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4)
1092#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6)
1093#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8)
1094#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10)
1095#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12)
1096#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14)
1097
1098/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */
1099#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0)
1100#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2)
1101#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4)
1102#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6)
1103#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00)
1104#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80)
1105#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40)
1106#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0)
1107#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00)
1108#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20)
1109#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10)
1110#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30)
1111#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00)
1112#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08)
1113#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04)
1114#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C)
1115#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00)
1116#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02)
1117#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01)
1118#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03)
1119
1120/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */
1121#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0)
1122#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2)
1123#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4)
1124#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6)
1125
1126/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */
1127#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001)
1128#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002)
1129#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004)
1130#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008)
1131#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010)
1132#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020)
1133#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040)
1134#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080)
1135#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100)
1136
1137/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */
1138#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4)
1139#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6)
1140#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8)
1141#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10)
1142#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12)
1143
1144/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */
1145#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0)
1146#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2)
1147#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4)
1148
1149/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */
1150#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0)
1151#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2)
1152#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4)
1153
1154/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */
1155#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0)
1156
1157/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */
1158#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0)
1159
1160/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */
1161#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0)
1162
1163/* Bit definitions and macros for MCF_GPIO_DSCR_UART */
1164#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0)
1165#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2)
1166
1167/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */
1168#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0)
1169
1170/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */
1171#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0)
1172
1173/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */
1174#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0)
1175
1176/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */
1177#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0)
1178
1179/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */
1180#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0)
1181
1182/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */
1183#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0)
1184
1185/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
1186#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
1187
sfking@fdwdc.com7846fe82009-06-19 18:11:10 -0700[diff] [blame]1188/*
1189 * Generic GPIO support
1190 */
1191#define MCFGPIO_PODR MCFGPIO_PODR_FECH
1192#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
1193#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
1194#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
1195#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
1196
1197#define MCFGPIO_PIN_MAX 136
1198#define MCFGPIO_IRQ_MAX 8
1199#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
1200
1201
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]1202/*********************************************************************
1203 *
1204 * Interrupt Controller (INTC)
1205 *
1206 *********************************************************************/
1207
1208/* Register read/write macros */
1209#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
1210#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
1211#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
1212#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
1213#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
1214#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
1215#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
1216#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
1217#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
1218#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
1219#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
1220#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040)
1221#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
1222#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
1223#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
1224#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
1225#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
1226#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
1227#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
1228#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
1229#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
1230#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
1231#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
1232#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
1233#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
1234#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
1235#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
1236#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
1237#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
1238#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
1239#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
1240#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
1241#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
1242#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
1243#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
1244#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
1245#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
1246#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
1247#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
1248#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
1249#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
1250#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
1251#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
1252#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
1253#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
1254#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
1255#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
1256#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
1257#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
1258#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
1259#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
1260#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
1261#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
1262#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
1263#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
1264#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
1265#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
1266#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
1267#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
1268#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
1269#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
1270#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
1271#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
1272#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
1273#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
1274#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
1275#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
1276#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
1277#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
1278#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
1279#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
1280#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
1281#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
1282#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
1283#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
1284#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001))
1285#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
1286#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
1287#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
1288#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
1289#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
1290#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
1291#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
1292#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
1293#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004))
1294#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
1295#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
1296#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
1297#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
1298#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
1299#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
1300#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
1301#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
1302#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
1303#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
1304#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
1305#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040)
1306#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
1307#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
1308#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
1309#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
1310#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
1311#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
1312#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
1313#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
1314#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
1315#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
1316#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
1317#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
1318#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
1319#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
1320#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
1321#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
1322#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
1323#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
1324#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
1325#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
1326#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
1327#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
1328#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
1329#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
1330#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
1331#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
1332#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
1333#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
1334#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
1335#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
1336#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
1337#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
1338#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
1339#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
1340#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
1341#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
1342#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
1343#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
1344#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
1345#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
1346#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
1347#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
1348#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
1349#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
1350#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
1351#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
1352#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
1353#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
1354#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
1355#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
1356#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
1357#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
1358#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
1359#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
1360#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
1361#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
1362#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
1363#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
1364#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
1365#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
1366#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
1367#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
1368#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
1369#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001))
1370#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
1371#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
1372#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
1373#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
1374#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
1375#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
1376#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8)
1377#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
1378#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004))
1379#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
1380#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
1381#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
1382#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
1383#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
1384#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
1385#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
1386#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
1387#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
1388#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
1389#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
1390#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000))
1391#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
1392#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
1393#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
1394#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
1395#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
1396#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
1397#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
1398#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
1399#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
1400#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
1401#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
1402#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
1403#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
1404#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
1405#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
1406#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
1407#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
1408#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
1409#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
1410#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
1411#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
1412#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
1413#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
1414#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
1415#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
1416#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
1417#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
1418#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
1419#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
1420#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
1421#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
1422#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
1423#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
1424#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
1425#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
1426#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
1427#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
1428#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
1429#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
1430#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
1431#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
1432#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
1433#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
1434#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
1435#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
1436#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
1437#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
1438#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
1439#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
1440#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
1441#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
1442#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
1443#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
1444#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
1445#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
1446#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
1447#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
1448#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
1449#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
1450#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
1451#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
1452#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
1453#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
1454#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
1455#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
1456#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
1457#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
1458#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
1459#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
1460#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
1461#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
1462
1463/* Bit definitions and macros for MCF_INTC_IPRH */
1464#define MCF_INTC_IPRH_INT32 (0x00000001)
1465#define MCF_INTC_IPRH_INT33 (0x00000002)
1466#define MCF_INTC_IPRH_INT34 (0x00000004)
1467#define MCF_INTC_IPRH_INT35 (0x00000008)
1468#define MCF_INTC_IPRH_INT36 (0x00000010)
1469#define MCF_INTC_IPRH_INT37 (0x00000020)
1470#define MCF_INTC_IPRH_INT38 (0x00000040)
1471#define MCF_INTC_IPRH_INT39 (0x00000080)
1472#define MCF_INTC_IPRH_INT40 (0x00000100)
1473#define MCF_INTC_IPRH_INT41 (0x00000200)
1474#define MCF_INTC_IPRH_INT42 (0x00000400)
1475#define MCF_INTC_IPRH_INT43 (0x00000800)
1476#define MCF_INTC_IPRH_INT44 (0x00001000)
1477#define MCF_INTC_IPRH_INT45 (0x00002000)
1478#define MCF_INTC_IPRH_INT46 (0x00004000)
1479#define MCF_INTC_IPRH_INT47 (0x00008000)
1480#define MCF_INTC_IPRH_INT48 (0x00010000)
1481#define MCF_INTC_IPRH_INT49 (0x00020000)
1482#define MCF_INTC_IPRH_INT50 (0x00040000)
1483#define MCF_INTC_IPRH_INT51 (0x00080000)
1484#define MCF_INTC_IPRH_INT52 (0x00100000)
1485#define MCF_INTC_IPRH_INT53 (0x00200000)
1486#define MCF_INTC_IPRH_INT54 (0x00400000)
1487#define MCF_INTC_IPRH_INT55 (0x00800000)
1488#define MCF_INTC_IPRH_INT56 (0x01000000)
1489#define MCF_INTC_IPRH_INT57 (0x02000000)
1490#define MCF_INTC_IPRH_INT58 (0x04000000)
1491#define MCF_INTC_IPRH_INT59 (0x08000000)
1492#define MCF_INTC_IPRH_INT60 (0x10000000)
1493#define MCF_INTC_IPRH_INT61 (0x20000000)
1494#define MCF_INTC_IPRH_INT62 (0x40000000)
1495#define MCF_INTC_IPRH_INT63 (0x80000000)
1496
1497/* Bit definitions and macros for MCF_INTC_IPRL */
1498#define MCF_INTC_IPRL_INT0 (0x00000001)
1499#define MCF_INTC_IPRL_INT1 (0x00000002)
1500#define MCF_INTC_IPRL_INT2 (0x00000004)
1501#define MCF_INTC_IPRL_INT3 (0x00000008)
1502#define MCF_INTC_IPRL_INT4 (0x00000010)
1503#define MCF_INTC_IPRL_INT5 (0x00000020)
1504#define MCF_INTC_IPRL_INT6 (0x00000040)
1505#define MCF_INTC_IPRL_INT7 (0x00000080)
1506#define MCF_INTC_IPRL_INT8 (0x00000100)
1507#define MCF_INTC_IPRL_INT9 (0x00000200)
1508#define MCF_INTC_IPRL_INT10 (0x00000400)
1509#define MCF_INTC_IPRL_INT11 (0x00000800)
1510#define MCF_INTC_IPRL_INT12 (0x00001000)
1511#define MCF_INTC_IPRL_INT13 (0x00002000)
1512#define MCF_INTC_IPRL_INT14 (0x00004000)
1513#define MCF_INTC_IPRL_INT15 (0x00008000)
1514#define MCF_INTC_IPRL_INT16 (0x00010000)
1515#define MCF_INTC_IPRL_INT17 (0x00020000)
1516#define MCF_INTC_IPRL_INT18 (0x00040000)
1517#define MCF_INTC_IPRL_INT19 (0x00080000)
1518#define MCF_INTC_IPRL_INT20 (0x00100000)
1519#define MCF_INTC_IPRL_INT21 (0x00200000)
1520#define MCF_INTC_IPRL_INT22 (0x00400000)
1521#define MCF_INTC_IPRL_INT23 (0x00800000)
1522#define MCF_INTC_IPRL_INT24 (0x01000000)
1523#define MCF_INTC_IPRL_INT25 (0x02000000)
1524#define MCF_INTC_IPRL_INT26 (0x04000000)
1525#define MCF_INTC_IPRL_INT27 (0x08000000)
1526#define MCF_INTC_IPRL_INT28 (0x10000000)
1527#define MCF_INTC_IPRL_INT29 (0x20000000)
1528#define MCF_INTC_IPRL_INT30 (0x40000000)
1529#define MCF_INTC_IPRL_INT31 (0x80000000)
1530
1531/* Bit definitions and macros for MCF_INTC_IMRH */
1532#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
1533#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
1534#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
1535#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
1536#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
1537#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
1538#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
1539#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
1540#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
1541#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
1542#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
1543#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
1544#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
1545#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
1546#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
1547#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
1548#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
1549#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
1550#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
1551#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
1552#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
1553#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
1554#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
1555#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
1556#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
1557#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
1558#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
1559#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
1560#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
1561#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
1562#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
1563#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
1564
1565/* Bit definitions and macros for MCF_INTC_IMRL */
1566#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
1567#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
1568#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
1569#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
1570#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
1571#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
1572#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
1573#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
1574#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
1575#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
1576#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
1577#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
1578#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
1579#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
1580#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
1581#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
1582#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
1583#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
1584#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
1585#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
1586#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
1587#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
1588#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
1589#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
1590#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
1591#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
1592#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
1593#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
1594#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
1595#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
1596#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
1597#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
1598
1599/* Bit definitions and macros for MCF_INTC_INTFRCH */
1600#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
1601#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
1602#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
1603#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
1604#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
1605#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
1606#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
1607#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
1608#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
1609#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
1610#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
1611#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
1612#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
1613#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
1614#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
1615#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
1616#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
1617#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
1618#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
1619#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
1620#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
1621#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
1622#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
1623#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
1624#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
1625#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
1626#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
1627#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
1628#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
1629#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
1630#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
1631#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
1632
1633/* Bit definitions and macros for MCF_INTC_INTFRCL */
1634#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
1635#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
1636#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
1637#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
1638#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
1639#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
1640#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
1641#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
1642#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
1643#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
1644#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
1645#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
1646#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
1647#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
1648#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
1649#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
1650#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
1651#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
1652#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
1653#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
1654#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
1655#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
1656#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
1657#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
1658#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
1659#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
1660#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
1661#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
1662#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
1663#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
1664#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
1665#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
1666
1667/* Bit definitions and macros for MCF_INTC_ICONFIG */
1668#define MCF_INTC_ICONFIG_EMASK (0x0020)
1669#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
1670#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
1671#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
1672#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
1673#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
1674#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
1675#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
1676
1677/* Bit definitions and macros for MCF_INTC_SIMR */
1678#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0)
1679
1680/* Bit definitions and macros for MCF_INTC_CIMR */
1681#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0)
1682
1683/* Bit definitions and macros for MCF_INTC_CLMASK */
1684#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0)
1685
1686/* Bit definitions and macros for MCF_INTC_SLMASK */
1687#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0)
1688
1689/* Bit definitions and macros for MCF_INTC_ICR */
1690#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0)
1691
1692/* Bit definitions and macros for MCF_INTC_SWIACK */
1693#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
1694
1695/* Bit definitions and macros for MCF_INTC_LIACK */
1696#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
1697
1698/********************************************************************/
1699/*********************************************************************
1700*
1701* LCD Controller (LCDC)
1702*
1703*********************************************************************/
1704
1705/* Register read/write macros */
1706#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000)
1707#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004)
1708#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008)
1709#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C)
1710#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010)
1711#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014)
1712#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018)
1713#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C)
1714#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020)
1715#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024)
1716#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028)
1717#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C)
1718#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030)
1719#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034)
1720#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038)
1721#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C)
1722#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040)
1723#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050)
1724#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054)
1725#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058)
1726#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C)
1727#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060)
1728#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064)
1729#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068)
1730#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800)
1731#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00)
1732
1733/* Bit definitions and macros for MCF_LCDC_LSSAR */
1734#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
1735
1736/* Bit definitions and macros for MCF_LCDC_LSR */
1737#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
1738#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
1739
1740/* Bit definitions and macros for MCF_LCDC_LVPWR */
1741#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
1742
1743/* Bit definitions and macros for MCF_LCDC_LCPR */
1744#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
1745#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
1746#define MCF_LCDC_LCPR_OP (0x10000000)
1747#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
1748#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000)
1749#define MCF_LCDC_LCPR_CC_OR (0x40000000)
1750#define MCF_LCDC_LCPR_CC_XOR (0x80000000)
1751#define MCF_LCDC_LCPR_CC_AND (0xC0000000)
1752#define MCF_LCDC_LCPR_OP_ON (0x10000000)
1753#define MCF_LCDC_LCPR_OP_OFF (0x00000000)
1754
1755/* Bit definitions and macros for MCF_LCDC_LCWHBR */
1756#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
1757#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
1758#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
1759#define MCF_LCDC_LCWHBR_BK_EN (0x80000000)
1760#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000)
1761#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000)
1762
1763/* Bit definitions and macros for MCF_LCDC_LCCMR */
1764#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
1765#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
1766#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
1767
1768/* Bit definitions and macros for MCF_LCDC_LPCR */
1769#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
1770#define MCF_LCDC_LPCR_SHARP (0x00000040)
1771#define MCF_LCDC_LPCR_SCLKSEL (0x00000080)
1772#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
1773#define MCF_LCDC_LPCR_ACDSEL (0x00008000)
1774#define MCF_LCDC_LPCR_REV_VS (0x00010000)
1775#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000)
1776#define MCF_LCDC_LPCR_ENDSEL (0x00040000)
1777#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000)
1778#define MCF_LCDC_LPCR_OEPOL (0x00100000)
1779#define MCF_LCDC_LPCR_CLKPOL (0x00200000)
1780#define MCF_LCDC_LPCR_LPPOL (0x00400000)
1781#define MCF_LCDC_LPCR_FLM (0x00800000)
1782#define MCF_LCDC_LPCR_PIXPOL (0x01000000)
1783#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
1784#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
1785#define MCF_LCDC_LPCR_COLOR (0x40000000)
1786#define MCF_LCDC_LPCR_TFT (0x80000000)
1787#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000)
1788#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000)
1789#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000)
1790#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000)
1791#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000)
1792#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000)
1793#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000)
1794#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000)
1795#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000)
1796#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000)
1797#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000)
1798#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000)
1799#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000)
1800#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000)
1801
1802#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
1803
1804/* Bit definitions and macros for MCF_LCDC_LHCR */
1805#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
1806#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
1807#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
1808
1809/* Bit definitions and macros for MCF_LCDC_LVCR */
1810#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
1811#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
1812#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
1813
1814/* Bit definitions and macros for MCF_LCDC_LPOR */
1815#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
1816
1817/* Bit definitions and macros for MCF_LCDC_LPCCR */
1818#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
1819#define MCF_LCDC_LPCCR_CC_EN (0x00000100)
1820#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
1821#define MCF_LCDC_LPCCR_LDMSK (0x00008000)
1822#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
1823#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
1824#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
1825#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
1826
1827/* Bit definitions and macros for MCF_LCDC_LDCR */
1828#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
1829#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
1830#define MCF_LCDC_LDCR_BURST (0x80000000)
1831
1832/* Bit definitions and macros for MCF_LCDC_LRMCR */
1833#define MCF_LCDC_LRMCR_SEL_REF (0x00000001)
1834
1835/* Bit definitions and macros for MCF_LCDC_LICR */
1836#define MCF_LCDC_LICR_INTCON (0x00000001)
1837#define MCF_LCDC_LICR_INTSYN (0x00000004)
1838#define MCF_LCDC_LICR_GW_INT_CON (0x00000010)
1839
1840/* Bit definitions and macros for MCF_LCDC_LIER */
1841#define MCF_LCDC_LIER_BOF_EN (0x00000001)
1842#define MCF_LCDC_LIER_EOF_EN (0x00000002)
1843#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004)
1844#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008)
1845#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010)
1846#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020)
1847#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040)
1848#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
1849
1850/* Bit definitions and macros for MCF_LCDC_LISR */
1851#define MCF_LCDC_LISR_BOF (0x00000001)
1852#define MCF_LCDC_LISR_EOF (0x00000002)
1853#define MCF_LCDC_LISR_ERR_RES (0x00000004)
1854#define MCF_LCDC_LISR_UDR_ERR (0x00000008)
1855#define MCF_LCDC_LISR_GW_BOF (0x00000010)
1856#define MCF_LCDC_LISR_GW_EOF (0x00000020)
1857#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040)
1858#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080)
1859
1860/* Bit definitions and macros for MCF_LCDC_LGWSAR */
1861#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
1862
1863/* Bit definitions and macros for MCF_LCDC_LGWSR */
1864#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
1865#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
1866
1867/* Bit definitions and macros for MCF_LCDC_LGWVPWR */
1868#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
1869
1870/* Bit definitions and macros for MCF_LCDC_LGWPOR */
1871#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
1872
1873/* Bit definitions and macros for MCF_LCDC_LGWPR */
1874#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
1875#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
1876
1877/* Bit definitions and macros for MCF_LCDC_LGWCR */
1878#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
1879#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
1880#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
1881#define MCF_LCDC_LGWCR_GW_RVS (0x00200000)
1882#define MCF_LCDC_LGWCR_GWE (0x00400000)
1883#define MCF_LCDC_LGWCR_GWCKE (0x00800000)
1884#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
1885
1886/* Bit definitions and macros for MCF_LCDC_LGWDCR */
1887#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
1888#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
1889#define MCF_LCDC_LGWDCR_GWBT (0x80000000)
1890
1891/* Bit definitions and macros for MCF_LCDC_LSCR */
1892#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26)
1893#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16)
1894#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8)
1895#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4)
1896#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0)
1897
1898/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */
1899#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1900
1901/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */
1902#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0)
1903
1904/*********************************************************************
1905 *
1906 * Phase Locked Loop (PLL)
1907 *
1908 *********************************************************************/
1909
1910/* Register read/write macros */
1911#define MCF_PLL_PODR MCF_REG08(0xFC0C0000)
1912#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004)
1913#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008)
1914#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C)
1915
1916/* Bit definitions and macros for MCF_PLL_PODR */
1917#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0)
1918#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
1919
1920/* Bit definitions and macros for MCF_PLL_PLLCR */
1921#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0)
1922#define MCF_PLL_PLLCR_DITHEN (0x80)
1923
1924/* Bit definitions and macros for MCF_PLL_PMDR */
1925#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0)
1926
1927/* Bit definitions and macros for MCF_PLL_PFDR */
1928#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0)
1929
1930/*********************************************************************
1931 *
1932 * System Control Module Registers (SCM)
1933 *
1934 *********************************************************************/
1935
1936/* Register read/write macros */
1937#define MCF_SCM_MPR MCF_REG32(0xFC000000)
1938#define MCF_SCM_PACRA MCF_REG32(0xFC000020)
1939#define MCF_SCM_PACRB MCF_REG32(0xFC000024)
1940#define MCF_SCM_PACRC MCF_REG32(0xFC000028)
1941#define MCF_SCM_PACRD MCF_REG32(0xFC00002C)
1942#define MCF_SCM_PACRE MCF_REG32(0xFC000040)
1943#define MCF_SCM_PACRF MCF_REG32(0xFC000044)
1944
1945#define MCF_SCM_BCR MCF_REG32(0xFC040024)
1946
1947/*********************************************************************
1948 *
1949 * SDRAM Controller (SDRAMC)
1950 *
1951 *********************************************************************/
1952
1953/* Register read/write macros */
1954#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000)
1955#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004)
1956#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008)
1957#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C)
1958#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080)
1959#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100)
1960#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110)
1961#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114)
1962#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118)
1963#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C)
1964#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004))
1965
1966/* Bit definitions and macros for MCF_SDRAMC_SDMR */
1967#define MCF_SDRAMC_SDMR_CMD (0x00010000)
1968#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
1969#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
1970#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
1971#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
1972
1973/* Bit definitions and macros for MCF_SDRAMC_SDCR */
1974#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
1975#define MCF_SDRAMC_SDCR_IREF (0x00000004)
1976#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
1977#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12)
1978#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
1979#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000)
1980#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
1981#define MCF_SDRAMC_SDCR_REF (0x10000000)
1982#define MCF_SDRAMC_SDCR_DDR (0x20000000)
1983#define MCF_SDRAMC_SDCR_CKE (0x40000000)
1984#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
1985#define MCF_SDRAMC_SDCR_PS_16 (0x00002000)
1986#define MCF_SDRAMC_SDCR_PS_32 (0x00000000)
1987
1988/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
1989#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
1990#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
1991#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
1992#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
1993#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
1994#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
1995#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
1996
1997/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
1998#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
1999#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
2000#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
2001#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
2002
2003/* Device Errata - LIMP mode work around */
2004#define MCF_SDRAMC_REFRESH (0x40000000)
2005
2006/* Bit definitions and macros for MCF_SDRAMC_SDDS */
2007#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0)
2008#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
2009#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
2010#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
2011#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
2012
2013/* Bit definitions and macros for MCF_SDRAMC_SDCS */
2014#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0)
2015#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
2016#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
2017#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
2018#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
2019#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
2020#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
2021#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
2022#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
2023#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
2024#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
2025#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
2026#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
2027#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
2028#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
2029#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
2030#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
2031
2032/*********************************************************************
2033 *
2034 * FlexCAN module registers
2035 *
2036 *********************************************************************/
2037#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800)
2038#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00)
2039#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04)
2040#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08)
2041#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10)
2042#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14)
2043#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18)
2044#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C)
2045#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20)
2046#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28)
2047#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30)
2048
2049#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0)
2050#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4)
2051#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1)
2052
2053/*
2054 * FlexCAN Module Configuration Register
2055 */
2056#define CANMCR_MDIS (0x80000000)
2057#define CANMCR_FRZ (0x40000000)
2058#define CANMCR_HALT (0x10000000)
2059#define CANMCR_SOFTRST (0x02000000)
2060#define CANMCR_FRZACK (0x01000000)
2061#define CANMCR_SUPV (0x00800000)
2062#define CANMCR_MAXMB(x) ((x)&0x0F)
2063
2064/*
2065 * FlexCAN Control Register
2066 */
2067#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
2068#define CANCTRL_RJW(x) (((x)&0x03)<<22)
2069#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
2070#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
2071#define CANCTRL_BOFFMSK (0x00008000)
2072#define CANCTRL_ERRMSK (0x00004000)
2073#define CANCTRL_CLKSRC (0x00002000)
2074#define CANCTRL_LPB (0x00001000)
2075#define CANCTRL_SAMP (0x00000080)
2076#define CANCTRL_BOFFREC (0x00000040)
2077#define CANCTRL_TSYNC (0x00000020)
2078#define CANCTRL_LBUF (0x00000010)
2079#define CANCTRL_LOM (0x00000008)
2080#define CANCTRL_PROPSEG(x) ((x)&0x07)
2081
2082/*
2083 * FlexCAN Error Counter Register
2084 */
2085#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
2086#define ERRCNT_TXECTR(x) ((x)&0xFF)
2087
2088/*
2089 * FlexCAN Error and Status Register
2090 */
2091#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
2092#define ERRSTAT_ACKERR (0x00002000)
2093#define ERRSTAT_CRCERR (0x00001000)
2094#define ERRSTAT_FRMERR (0x00000800)
2095#define ERRSTAT_STFERR (0x00000400)
2096#define ERRSTAT_TXWRN (0x00000200)
2097#define ERRSTAT_RXWRN (0x00000100)
2098#define ERRSTAT_IDLE (0x00000080)
2099#define ERRSTAT_TXRX (0x00000040)
2100#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
2101#define ERRSTAT_BOFFINT (0x00000004)
2102#define ERRSTAT_ERRINT (0x00000002)
2103
2104/*
2105 * Interrupt Mask Register
2106 */
2107#define IMASK_BUF15M (0x8000)
2108#define IMASK_BUF14M (0x4000)
2109#define IMASK_BUF13M (0x2000)
2110#define IMASK_BUF12M (0x1000)
2111#define IMASK_BUF11M (0x0800)
2112#define IMASK_BUF10M (0x0400)
2113#define IMASK_BUF9M (0x0200)
2114#define IMASK_BUF8M (0x0100)
2115#define IMASK_BUF7M (0x0080)
2116#define IMASK_BUF6M (0x0040)
2117#define IMASK_BUF5M (0x0020)
2118#define IMASK_BUF4M (0x0010)
2119#define IMASK_BUF3M (0x0008)
2120#define IMASK_BUF2M (0x0004)
2121#define IMASK_BUF1M (0x0002)
2122#define IMASK_BUF0M (0x0001)
2123#define IMASK_BUFnM(x) (0x1<<(x))
2124#define IMASK_BUFF_ENABLE_ALL (0x1111)
2125#define IMASK_BUFF_DISABLE_ALL (0x0000)
2126
2127/*
2128 * Interrupt Flag Register
2129 */
2130#define IFLAG_BUF15M (0x8000)
2131#define IFLAG_BUF14M (0x4000)
2132#define IFLAG_BUF13M (0x2000)
2133#define IFLAG_BUF12M (0x1000)
2134#define IFLAG_BUF11M (0x0800)
2135#define IFLAG_BUF10M (0x0400)
2136#define IFLAG_BUF9M (0x0200)
2137#define IFLAG_BUF8M (0x0100)
2138#define IFLAG_BUF7M (0x0080)
2139#define IFLAG_BUF6M (0x0040)
2140#define IFLAG_BUF5M (0x0020)
2141#define IFLAG_BUF4M (0x0010)
2142#define IFLAG_BUF3M (0x0008)
2143#define IFLAG_BUF2M (0x0004)
2144#define IFLAG_BUF1M (0x0002)
2145#define IFLAG_BUF0M (0x0001)
2146#define IFLAG_BUFF_SET_ALL (0xFFFF)
2147#define IFLAG_BUFF_CLEAR_ALL (0x0000)
2148#define IFLAG_BUFnM(x) (0x1<<(x))
2149
2150/*
2151 * Message Buffers
2152 */
2153#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
2154#define MB_CNT_SRR (0x00400000)
2155#define MB_CNT_IDE (0x00200000)
2156#define MB_CNT_RTR (0x00100000)
2157#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16)
2158#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
2159#define MB_ID_STD(x) (((x)&0x07FF)<<18)
2160#define MB_ID_EXT(x) ((x)&0x3FFFF)
2161
2162/*********************************************************************
2163 *
2164 * Edge Port Module (EPORT)
2165 *
2166 *********************************************************************/
2167
2168/* Register read/write macros */
sfking@fdwdc.com7846fe82009-06-19 18:11:10 -0700[diff] [blame]2169#define MCFEPORT_EPPAR (0xFC094000)
2170#define MCFEPORT_EPDDR (0xFC094002)
2171#define MCFEPORT_EPIER (0xFC094003)
2172#define MCFEPORT_EPDR (0xFC094004)
2173#define MCFEPORT_EPPDR (0xFC094005)
2174#define MCFEPORT_EPFR (0xFC094006)
Greg Ungerer7c99df62006-06-26 10:33:10 +1000[diff] [blame]2175
2176/* Bit definitions and macros for MCF_EPORT_EPPAR */
2177#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
2178#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
2179#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
2180#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
2181#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
2182#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
2183#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
2184#define MCF_EPORT_EPPAR_LEVEL (0)
2185#define MCF_EPORT_EPPAR_RISING (1)
2186#define MCF_EPORT_EPPAR_FALLING (2)
2187#define MCF_EPORT_EPPAR_BOTH (3)
2188#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
2189#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
2190#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
2191#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
2192#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
2193#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
2194#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
2195#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
2196#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
2197#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
2198#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
2199#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
2200#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
2201#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
2202#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
2203#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
2204#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
2205#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
2206#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
2207#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
2208#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
2209#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
2210#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
2211#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
2212#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
2213#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
2214#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
2215#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
2216
2217/* Bit definitions and macros for MCF_EPORT_EPDDR */
2218#define MCF_EPORT_EPDDR_EPDD1 (0x02)
2219#define MCF_EPORT_EPDDR_EPDD2 (0x04)
2220#define MCF_EPORT_EPDDR_EPDD3 (0x08)
2221#define MCF_EPORT_EPDDR_EPDD4 (0x10)
2222#define MCF_EPORT_EPDDR_EPDD5 (0x20)
2223#define MCF_EPORT_EPDDR_EPDD6 (0x40)
2224#define MCF_EPORT_EPDDR_EPDD7 (0x80)
2225
2226/* Bit definitions and macros for MCF_EPORT_EPIER */
2227#define MCF_EPORT_EPIER_EPIE1 (0x02)
2228#define MCF_EPORT_EPIER_EPIE2 (0x04)
2229#define MCF_EPORT_EPIER_EPIE3 (0x08)
2230#define MCF_EPORT_EPIER_EPIE4 (0x10)
2231#define MCF_EPORT_EPIER_EPIE5 (0x20)
2232#define MCF_EPORT_EPIER_EPIE6 (0x40)
2233#define MCF_EPORT_EPIER_EPIE7 (0x80)
2234
2235/* Bit definitions and macros for MCF_EPORT_EPDR */
2236#define MCF_EPORT_EPDR_EPD1 (0x02)
2237#define MCF_EPORT_EPDR_EPD2 (0x04)
2238#define MCF_EPORT_EPDR_EPD3 (0x08)
2239#define MCF_EPORT_EPDR_EPD4 (0x10)
2240#define MCF_EPORT_EPDR_EPD5 (0x20)
2241#define MCF_EPORT_EPDR_EPD6 (0x40)
2242#define MCF_EPORT_EPDR_EPD7 (0x80)
2243
2244/* Bit definitions and macros for MCF_EPORT_EPPDR */
2245#define MCF_EPORT_EPPDR_EPPD1 (0x02)
2246#define MCF_EPORT_EPPDR_EPPD2 (0x04)
2247#define MCF_EPORT_EPPDR_EPPD3 (0x08)
2248#define MCF_EPORT_EPPDR_EPPD4 (0x10)
2249#define MCF_EPORT_EPPDR_EPPD5 (0x20)
2250#define MCF_EPORT_EPPDR_EPPD6 (0x40)
2251#define MCF_EPORT_EPPDR_EPPD7 (0x80)
2252
2253/* Bit definitions and macros for MCF_EPORT_EPFR */
2254#define MCF_EPORT_EPFR_EPF1 (0x02)
2255#define MCF_EPORT_EPFR_EPF2 (0x04)
2256#define MCF_EPORT_EPFR_EPF3 (0x08)
2257#define MCF_EPORT_EPFR_EPF4 (0x10)
2258#define MCF_EPORT_EPFR_EPF5 (0x20)
2259#define MCF_EPORT_EPFR_EPF6 (0x40)
2260#define MCF_EPORT_EPFR_EPF7 (0x80)
2261
2262/********************************************************************/
2263#endif /* m532xsim_h */