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Sathya Perla6b7c5b92009-03-11 23:32:03 -07001/*
Ajit Khaparde294aedc2010-02-19 13:54:58 +00002 * Copyright (C) 2005 - 2010 ServerEngines
Sathya Perla6b7c5b92009-03-11 23:32:03 -07003 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
54 MCC_STATUS_SUCCESS = 0x0,
55/* The client does not have sufficient privileges to execute the command */
56 MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
57/* A parameter in the command was invalid. */
58 MCC_STATUS_INVALID_PARAMETER = 0x2,
59/* There are insufficient chip resources to execute the command */
60 MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
61/* The command is completing because the queue was getting flushed */
62 MCC_STATUS_QUEUE_FLUSHING = 0x4,
63/* The command is completing with a DMA error */
Sathya Perlab31c50a2009-09-17 10:30:13 -070064 MCC_STATUS_DMA_FAILED = 0x5,
Ajit Khaparde49643842009-10-05 02:22:05 +000065 MCC_STATUS_NOT_SUPPORTED = 66
Sathya Perla6b7c5b92009-03-11 23:32:03 -070066};
67
68#define CQE_STATUS_COMPL_MASK 0xFFFF
69#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
70#define CQE_STATUS_EXTD_MASK 0xFFFF
Sathya Perlaf5209b42009-11-06 00:31:01 -080071#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -070072
Sathya Perlaefd2e402009-07-27 22:53:10 +000073struct be_mcc_compl {
Sathya Perla6b7c5b92009-03-11 23:32:03 -070074 u32 status; /* dword 0 */
75 u32 tag0; /* dword 1 */
76 u32 tag1; /* dword 2 */
77 u32 flags; /* dword 3 */
78};
79
Sathya Perlaa8f447b2009-06-18 00:10:27 +000080/* When the async bit of mcc_compl is set, the last 4 bytes of
81 * mcc_compl is interpreted as follows:
82 */
83#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
84#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
Somnath Koturcc4ce022010-10-21 07:11:14 -070085#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
86#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
Sathya Perlaa8f447b2009-06-18 00:10:27 +000087#define ASYNC_EVENT_CODE_LINK_STATE 0x1
Somnath Koturcc4ce022010-10-21 07:11:14 -070088#define ASYNC_EVENT_CODE_GRP_5 0x5
89#define ASYNC_EVENT_QOS_SPEED 0x1
90#define ASYNC_EVENT_COS_PRIORITY 0x2
Ajit Khaparde3968fa12011-02-20 11:41:53 +000091#define ASYNC_EVENT_PVID_STATE 0x3
Sathya Perlaa8f447b2009-06-18 00:10:27 +000092struct be_async_event_trailer {
93 u32 code;
94};
95
96enum {
97 ASYNC_EVENT_LINK_DOWN = 0x0,
98 ASYNC_EVENT_LINK_UP = 0x1
99};
100
101/* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
103 */
104struct be_async_event_link_state {
105 u8 physical_port;
106 u8 port_link_status;
107 u8 port_duplex;
108 u8 port_speed;
109 u8 port_fault;
110 u8 rsvd0[7];
111 struct be_async_event_trailer trailer;
112} __packed;
113
Somnath Koturcc4ce022010-10-21 07:11:14 -0700114/* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
116 */
117struct be_async_event_grp5_qos_link_speed {
118 u8 physical_port;
119 u8 rsvd[5];
120 u16 qos_link_speed;
121 u32 event_tag;
122 struct be_async_event_trailer trailer;
123} __packed;
124
125/* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
127 */
128struct be_async_event_grp5_cos_priority {
129 u8 physical_port;
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
132 u8 valid;
133 u8 rsvd0;
134 u8 event_tag;
135 struct be_async_event_trailer trailer;
136} __packed;
137
Ajit Khaparde3968fa12011-02-20 11:41:53 +0000138/* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
140 */
141struct be_async_event_grp5_pvid_state {
142 u8 enabled;
143 u8 rsvd0;
144 u16 tag;
145 u32 event_tag;
146 u32 rsvd1;
147 struct be_async_event_trailer trailer;
148} __packed;
149
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700150struct be_mcc_mailbox {
151 struct be_mcc_wrb wrb;
Sathya Perlaefd2e402009-07-27 22:53:10 +0000152 struct be_mcc_compl compl;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700153};
154
155#define CMD_SUBSYSTEM_COMMON 0x1
156#define CMD_SUBSYSTEM_ETH 0x3
Suresh Rff33a6e2009-12-03 16:15:52 -0800157#define CMD_SUBSYSTEM_LOWLEVEL 0xb
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700158
159#define OPCODE_COMMON_NTWK_MAC_QUERY 1
160#define OPCODE_COMMON_NTWK_MAC_SET 2
161#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
162#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
163#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
Sarveshwar Bandifa9a6fe2009-11-20 14:23:47 -0800164#define OPCODE_COMMON_READ_FLASHROM 6
Ajit Khaparde84517482009-09-04 03:12:16 +0000165#define OPCODE_COMMON_WRITE_FLASHROM 7
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700166#define OPCODE_COMMON_CQ_CREATE 12
167#define OPCODE_COMMON_EQ_CREATE 13
Somnath Koturcc4ce022010-10-21 07:11:14 -0700168#define OPCODE_COMMON_MCC_CREATE 21
Ajit Khapardee1d18732010-07-23 01:52:13 +0000169#define OPCODE_COMMON_SET_QOS 28
Somnath Koturcc4ce022010-10-21 07:11:14 -0700170#define OPCODE_COMMON_MCC_CREATE_EXT 90
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -0800171#define OPCODE_COMMON_SEEPROM_READ 30
Ajit Khaparde9e1453c2011-02-20 11:42:22 +0000172#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700173#define OPCODE_COMMON_NTWK_RX_FILTER 34
174#define OPCODE_COMMON_GET_FW_VERSION 35
175#define OPCODE_COMMON_SET_FLOW_CONTROL 36
176#define OPCODE_COMMON_GET_FLOW_CONTROL 37
177#define OPCODE_COMMON_SET_FRAME_SIZE 39
178#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
179#define OPCODE_COMMON_FIRMWARE_CONFIG 42
180#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
181#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
Sathya Perla5fb379e2009-06-18 00:02:59 +0000182#define OPCODE_COMMON_MCC_DESTROY 53
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700183#define OPCODE_COMMON_CQ_DESTROY 54
184#define OPCODE_COMMON_EQ_DESTROY 55
185#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
186#define OPCODE_COMMON_NTWK_PMAC_ADD 59
187#define OPCODE_COMMON_NTWK_PMAC_DEL 60
sarveshwarb14074ea2009-08-05 13:05:24 -0700188#define OPCODE_COMMON_FUNCTION_RESET 61
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -0700189#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
190#define OPCODE_COMMON_GET_BEACON_STATE 70
Sarveshwar Bandi0388f252009-10-28 04:15:20 -0700191#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
Ajit Khapardeee3cb622010-07-01 03:51:00 +0000192#define OPCODE_COMMON_GET_PHY_DETAILS 102
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000193#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700194
Sathya Perla3abcded2010-10-03 22:12:27 -0700195#define OPCODE_ETH_RSS_CONFIG 1
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700196#define OPCODE_ETH_ACPI_CONFIG 2
197#define OPCODE_ETH_PROMISCUOUS 3
198#define OPCODE_ETH_GET_STATISTICS 4
199#define OPCODE_ETH_TX_CREATE 7
200#define OPCODE_ETH_RX_CREATE 8
201#define OPCODE_ETH_TX_DESTROY 9
202#define OPCODE_ETH_RX_DESTROY 10
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +0000203#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700204
Suresh Rff33a6e2009-12-03 16:15:52 -0800205#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
206#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
Sarveshwar Bandifced9992009-12-23 04:41:44 +0000207#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
Suresh Rff33a6e2009-12-03 16:15:52 -0800208
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700209struct be_cmd_req_hdr {
210 u8 opcode; /* dword 0 */
211 u8 subsystem; /* dword 0 */
212 u8 port_number; /* dword 0 */
213 u8 domain; /* dword 0 */
214 u32 timeout; /* dword 1 */
215 u32 request_length; /* dword 2 */
Ajit Khaparde7b139c82010-01-27 21:56:44 +0000216 u8 version; /* dword 3 */
217 u8 rsvd[3]; /* dword 3 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700218};
219
220#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
221#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
222struct be_cmd_resp_hdr {
223 u32 info; /* dword 0 */
224 u32 status; /* dword 1 */
225 u32 response_length; /* dword 2 */
226 u32 actual_resp_len; /* dword 3 */
227};
228
229struct phys_addr {
230 u32 lo;
231 u32 hi;
232};
233
234/**************************
235 * BE Command definitions *
236 **************************/
237
238/* Pseudo amap definition in which each bit of the actual structure is defined
239 * as a byte: used to calculate offset/shift/mask of each field */
240struct amap_eq_context {
241 u8 cidx[13]; /* dword 0*/
242 u8 rsvd0[3]; /* dword 0*/
243 u8 epidx[13]; /* dword 0*/
244 u8 valid; /* dword 0*/
245 u8 rsvd1; /* dword 0*/
246 u8 size; /* dword 0*/
247 u8 pidx[13]; /* dword 1*/
248 u8 rsvd2[3]; /* dword 1*/
249 u8 pd[10]; /* dword 1*/
250 u8 count[3]; /* dword 1*/
251 u8 solevent; /* dword 1*/
252 u8 stalled; /* dword 1*/
253 u8 armed; /* dword 1*/
254 u8 rsvd3[4]; /* dword 2*/
255 u8 func[8]; /* dword 2*/
256 u8 rsvd4; /* dword 2*/
257 u8 delaymult[10]; /* dword 2*/
258 u8 rsvd5[2]; /* dword 2*/
259 u8 phase[2]; /* dword 2*/
260 u8 nodelay; /* dword 2*/
261 u8 rsvd6[4]; /* dword 2*/
262 u8 rsvd7[32]; /* dword 3*/
263} __packed;
264
265struct be_cmd_req_eq_create {
266 struct be_cmd_req_hdr hdr;
267 u16 num_pages; /* sword */
268 u16 rsvd0; /* sword */
269 u8 context[sizeof(struct amap_eq_context) / 8];
270 struct phys_addr pages[8];
271} __packed;
272
273struct be_cmd_resp_eq_create {
274 struct be_cmd_resp_hdr resp_hdr;
275 u16 eq_id; /* sword */
276 u16 rsvd0; /* sword */
277} __packed;
278
279/******************** Mac query ***************************/
280enum {
281 MAC_ADDRESS_TYPE_STORAGE = 0x0,
282 MAC_ADDRESS_TYPE_NETWORK = 0x1,
283 MAC_ADDRESS_TYPE_PD = 0x2,
284 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
285};
286
287struct mac_addr {
288 u16 size_of_struct;
289 u8 addr[ETH_ALEN];
290} __packed;
291
292struct be_cmd_req_mac_query {
293 struct be_cmd_req_hdr hdr;
294 u8 type;
295 u8 permanent;
296 u16 if_id;
297} __packed;
298
299struct be_cmd_resp_mac_query {
300 struct be_cmd_resp_hdr hdr;
301 struct mac_addr mac;
302};
303
304/******************** PMac Add ***************************/
305struct be_cmd_req_pmac_add {
306 struct be_cmd_req_hdr hdr;
307 u32 if_id;
308 u8 mac_address[ETH_ALEN];
309 u8 rsvd0[2];
310} __packed;
311
312struct be_cmd_resp_pmac_add {
313 struct be_cmd_resp_hdr hdr;
314 u32 pmac_id;
315};
316
317/******************** PMac Del ***************************/
318struct be_cmd_req_pmac_del {
319 struct be_cmd_req_hdr hdr;
320 u32 if_id;
321 u32 pmac_id;
322};
323
324/******************** Create CQ ***************************/
325/* Pseudo amap definition in which each bit of the actual structure is defined
326 * as a byte: used to calculate offset/shift/mask of each field */
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000327struct amap_cq_context_be {
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700328 u8 cidx[11]; /* dword 0*/
329 u8 rsvd0; /* dword 0*/
330 u8 coalescwm[2]; /* dword 0*/
331 u8 nodelay; /* dword 0*/
332 u8 epidx[11]; /* dword 0*/
333 u8 rsvd1; /* dword 0*/
334 u8 count[2]; /* dword 0*/
335 u8 valid; /* dword 0*/
336 u8 solevent; /* dword 0*/
337 u8 eventable; /* dword 0*/
338 u8 pidx[11]; /* dword 1*/
339 u8 rsvd2; /* dword 1*/
340 u8 pd[10]; /* dword 1*/
341 u8 eqid[8]; /* dword 1*/
342 u8 stalled; /* dword 1*/
343 u8 armed; /* dword 1*/
344 u8 rsvd3[4]; /* dword 2*/
345 u8 func[8]; /* dword 2*/
346 u8 rsvd4[20]; /* dword 2*/
347 u8 rsvd5[32]; /* dword 3*/
348} __packed;
349
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000350struct amap_cq_context_lancer {
351 u8 rsvd0[12]; /* dword 0*/
352 u8 coalescwm[2]; /* dword 0*/
353 u8 nodelay; /* dword 0*/
354 u8 rsvd1[12]; /* dword 0*/
355 u8 count[2]; /* dword 0*/
356 u8 valid; /* dword 0*/
357 u8 rsvd2; /* dword 0*/
358 u8 eventable; /* dword 0*/
359 u8 eqid[16]; /* dword 1*/
360 u8 rsvd3[15]; /* dword 1*/
361 u8 armed; /* dword 1*/
362 u8 rsvd4[32]; /* dword 2*/
363 u8 rsvd5[32]; /* dword 3*/
364} __packed;
365
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700366struct be_cmd_req_cq_create {
367 struct be_cmd_req_hdr hdr;
368 u16 num_pages;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000369 u8 page_size;
370 u8 rsvd0;
371 u8 context[sizeof(struct amap_cq_context_be) / 8];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700372 struct phys_addr pages[8];
373} __packed;
374
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000375
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700376struct be_cmd_resp_cq_create {
377 struct be_cmd_resp_hdr hdr;
378 u16 cq_id;
379 u16 rsvd0;
380} __packed;
381
Sathya Perla5fb379e2009-06-18 00:02:59 +0000382/******************** Create MCCQ ***************************/
383/* Pseudo amap definition in which each bit of the actual structure is defined
384 * as a byte: used to calculate offset/shift/mask of each field */
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000385struct amap_mcc_context_be {
Sathya Perla5fb379e2009-06-18 00:02:59 +0000386 u8 con_index[14];
387 u8 rsvd0[2];
388 u8 ring_size[4];
389 u8 fetch_wrb;
390 u8 fetch_r2t;
391 u8 cq_id[10];
392 u8 prod_index[14];
393 u8 fid[8];
394 u8 pdid[9];
395 u8 valid;
396 u8 rsvd1[32];
397 u8 rsvd2[32];
398} __packed;
399
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000400struct amap_mcc_context_lancer {
401 u8 async_cq_id[16];
402 u8 ring_size[4];
403 u8 rsvd0[12];
404 u8 rsvd1[31];
405 u8 valid;
406 u8 async_cq_valid[1];
407 u8 rsvd2[31];
408 u8 rsvd3[32];
409} __packed;
410
Sathya Perla5fb379e2009-06-18 00:02:59 +0000411struct be_cmd_req_mcc_create {
412 struct be_cmd_req_hdr hdr;
413 u16 num_pages;
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000414 u16 cq_id;
Somnath Koturcc4ce022010-10-21 07:11:14 -0700415 u32 async_event_bitmap[1];
Sathya Perlafe6d2a32010-11-21 23:25:50 +0000416 u8 context[sizeof(struct amap_mcc_context_be) / 8];
Sathya Perla5fb379e2009-06-18 00:02:59 +0000417 struct phys_addr pages[8];
418} __packed;
419
420struct be_cmd_resp_mcc_create {
421 struct be_cmd_resp_hdr hdr;
422 u16 id;
423 u16 rsvd0;
424} __packed;
425
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700426/******************** Create TxQ ***************************/
427#define BE_ETH_TX_RING_TYPE_STANDARD 2
428#define BE_ULP1_NUM 1
429
430/* Pseudo amap definition in which each bit of the actual structure is defined
431 * as a byte: used to calculate offset/shift/mask of each field */
432struct amap_tx_context {
Padmanabh Ratnakar8b7756c2011-03-07 03:08:52 +0000433 u8 if_id[16]; /* dword 0 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700434 u8 tx_ring_size[4]; /* dword 0 */
435 u8 rsvd1[26]; /* dword 0 */
436 u8 pci_func_id[8]; /* dword 1 */
437 u8 rsvd2[9]; /* dword 1 */
438 u8 ctx_valid; /* dword 1 */
439 u8 cq_id_send[16]; /* dword 2 */
440 u8 rsvd3[16]; /* dword 2 */
441 u8 rsvd4[32]; /* dword 3 */
442 u8 rsvd5[32]; /* dword 4 */
443 u8 rsvd6[32]; /* dword 5 */
444 u8 rsvd7[32]; /* dword 6 */
445 u8 rsvd8[32]; /* dword 7 */
446 u8 rsvd9[32]; /* dword 8 */
447 u8 rsvd10[32]; /* dword 9 */
448 u8 rsvd11[32]; /* dword 10 */
449 u8 rsvd12[32]; /* dword 11 */
450 u8 rsvd13[32]; /* dword 12 */
451 u8 rsvd14[32]; /* dword 13 */
452 u8 rsvd15[32]; /* dword 14 */
453 u8 rsvd16[32]; /* dword 15 */
454} __packed;
455
456struct be_cmd_req_eth_tx_create {
457 struct be_cmd_req_hdr hdr;
458 u8 num_pages;
459 u8 ulp_num;
460 u8 type;
461 u8 bound_port;
462 u8 context[sizeof(struct amap_tx_context) / 8];
463 struct phys_addr pages[8];
464} __packed;
465
466struct be_cmd_resp_eth_tx_create {
467 struct be_cmd_resp_hdr hdr;
468 u16 cid;
469 u16 rsvd0;
470} __packed;
471
472/******************** Create RxQ ***************************/
473struct be_cmd_req_eth_rx_create {
474 struct be_cmd_req_hdr hdr;
475 u16 cq_id;
476 u8 frag_size;
477 u8 num_pages;
478 struct phys_addr pages[2];
479 u32 interface_id;
480 u16 max_frame_size;
481 u16 rsvd0;
482 u32 rss_queue;
483} __packed;
484
485struct be_cmd_resp_eth_rx_create {
486 struct be_cmd_resp_hdr hdr;
487 u16 id;
Sathya Perla3abcded2010-10-03 22:12:27 -0700488 u8 rss_id;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700489 u8 rsvd0;
490} __packed;
491
492/******************** Q Destroy ***************************/
493/* Type of Queue to be destroyed */
494enum {
495 QTYPE_EQ = 1,
496 QTYPE_CQ,
497 QTYPE_TXQ,
Sathya Perla5fb379e2009-06-18 00:02:59 +0000498 QTYPE_RXQ,
499 QTYPE_MCCQ
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700500};
501
502struct be_cmd_req_q_destroy {
503 struct be_cmd_req_hdr hdr;
504 u16 id;
505 u16 bypass_flush; /* valid only for rx q destroy */
506} __packed;
507
508/************ I/f Create (it's actually I/f Config Create)**********/
509
510/* Capability flags for the i/f */
511enum be_if_flags {
512 BE_IF_FLAGS_RSS = 0x4,
513 BE_IF_FLAGS_PROMISCUOUS = 0x8,
514 BE_IF_FLAGS_BROADCAST = 0x10,
515 BE_IF_FLAGS_UNTAGGED = 0x20,
516 BE_IF_FLAGS_ULP = 0x40,
517 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
518 BE_IF_FLAGS_VLAN = 0x100,
519 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
520 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
Padmanabh Ratnakarf21b5382011-03-07 03:09:36 +0000521 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
522 BE_IF_FLAGS_MULTICAST = 0x1000
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700523};
524
525/* An RX interface is an object with one or more MAC addresses and
526 * filtering capabilities. */
527struct be_cmd_req_if_create {
528 struct be_cmd_req_hdr hdr;
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200529 u32 version; /* ignore currently */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700530 u32 capability_flags;
531 u32 enable_flags;
532 u8 mac_addr[ETH_ALEN];
533 u8 rsvd0;
534 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
535 u32 vlan_tag; /* not used currently */
536} __packed;
537
538struct be_cmd_resp_if_create {
539 struct be_cmd_resp_hdr hdr;
540 u32 interface_id;
541 u32 pmac_id;
542};
543
544/****** I/f Destroy(it's actually I/f Config Destroy )**********/
545struct be_cmd_req_if_destroy {
546 struct be_cmd_req_hdr hdr;
547 u32 interface_id;
548};
549
550/*************** HW Stats Get **********************************/
551struct be_port_rxf_stats {
552 u32 rx_bytes_lsd; /* dword 0*/
553 u32 rx_bytes_msd; /* dword 1*/
554 u32 rx_total_frames; /* dword 2*/
555 u32 rx_unicast_frames; /* dword 3*/
556 u32 rx_multicast_frames; /* dword 4*/
557 u32 rx_broadcast_frames; /* dword 5*/
558 u32 rx_crc_errors; /* dword 6*/
559 u32 rx_alignment_symbol_errors; /* dword 7*/
560 u32 rx_pause_frames; /* dword 8*/
561 u32 rx_control_frames; /* dword 9*/
562 u32 rx_in_range_errors; /* dword 10*/
563 u32 rx_out_range_errors; /* dword 11*/
564 u32 rx_frame_too_long; /* dword 12*/
565 u32 rx_address_match_errors; /* dword 13*/
566 u32 rx_vlan_mismatch; /* dword 14*/
567 u32 rx_dropped_too_small; /* dword 15*/
568 u32 rx_dropped_too_short; /* dword 16*/
569 u32 rx_dropped_header_too_small; /* dword 17*/
570 u32 rx_dropped_tcp_length; /* dword 18*/
571 u32 rx_dropped_runt; /* dword 19*/
572 u32 rx_64_byte_packets; /* dword 20*/
573 u32 rx_65_127_byte_packets; /* dword 21*/
574 u32 rx_128_256_byte_packets; /* dword 22*/
575 u32 rx_256_511_byte_packets; /* dword 23*/
576 u32 rx_512_1023_byte_packets; /* dword 24*/
577 u32 rx_1024_1518_byte_packets; /* dword 25*/
578 u32 rx_1519_2047_byte_packets; /* dword 26*/
579 u32 rx_2048_4095_byte_packets; /* dword 27*/
580 u32 rx_4096_8191_byte_packets; /* dword 28*/
581 u32 rx_8192_9216_byte_packets; /* dword 29*/
582 u32 rx_ip_checksum_errs; /* dword 30*/
583 u32 rx_tcp_checksum_errs; /* dword 31*/
584 u32 rx_udp_checksum_errs; /* dword 32*/
585 u32 rx_non_rss_packets; /* dword 33*/
586 u32 rx_ipv4_packets; /* dword 34*/
587 u32 rx_ipv6_packets; /* dword 35*/
588 u32 rx_ipv4_bytes_lsd; /* dword 36*/
589 u32 rx_ipv4_bytes_msd; /* dword 37*/
590 u32 rx_ipv6_bytes_lsd; /* dword 38*/
591 u32 rx_ipv6_bytes_msd; /* dword 39*/
592 u32 rx_chute1_packets; /* dword 40*/
593 u32 rx_chute2_packets; /* dword 41*/
594 u32 rx_chute3_packets; /* dword 42*/
595 u32 rx_management_packets; /* dword 43*/
596 u32 rx_switched_unicast_packets; /* dword 44*/
597 u32 rx_switched_multicast_packets; /* dword 45*/
598 u32 rx_switched_broadcast_packets; /* dword 46*/
599 u32 tx_bytes_lsd; /* dword 47*/
600 u32 tx_bytes_msd; /* dword 48*/
601 u32 tx_unicastframes; /* dword 49*/
602 u32 tx_multicastframes; /* dword 50*/
603 u32 tx_broadcastframes; /* dword 51*/
604 u32 tx_pauseframes; /* dword 52*/
605 u32 tx_controlframes; /* dword 53*/
606 u32 tx_64_byte_packets; /* dword 54*/
607 u32 tx_65_127_byte_packets; /* dword 55*/
608 u32 tx_128_256_byte_packets; /* dword 56*/
609 u32 tx_256_511_byte_packets; /* dword 57*/
610 u32 tx_512_1023_byte_packets; /* dword 58*/
611 u32 tx_1024_1518_byte_packets; /* dword 59*/
612 u32 tx_1519_2047_byte_packets; /* dword 60*/
613 u32 tx_2048_4095_byte_packets; /* dword 61*/
614 u32 tx_4096_8191_byte_packets; /* dword 62*/
615 u32 tx_8192_9216_byte_packets; /* dword 63*/
616 u32 rx_fifo_overflow; /* dword 64*/
617 u32 rx_input_fifo_overflow; /* dword 65*/
618};
619
620struct be_rxf_stats {
621 struct be_port_rxf_stats port[2];
622 u32 rx_drops_no_pbuf; /* dword 132*/
623 u32 rx_drops_no_txpb; /* dword 133*/
624 u32 rx_drops_no_erx_descr; /* dword 134*/
625 u32 rx_drops_no_tpre_descr; /* dword 135*/
626 u32 management_rx_port_packets; /* dword 136*/
627 u32 management_rx_port_bytes; /* dword 137*/
628 u32 management_rx_port_pause_frames; /* dword 138*/
629 u32 management_rx_port_errors; /* dword 139*/
630 u32 management_tx_port_packets; /* dword 140*/
631 u32 management_tx_port_bytes; /* dword 141*/
632 u32 management_tx_port_pause; /* dword 142*/
633 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
634 u32 rx_drops_too_many_frags; /* dword 144*/
635 u32 rx_drops_invalid_ring; /* dword 145*/
636 u32 forwarded_packets; /* dword 146*/
637 u32 rx_drops_mtu; /* dword 147*/
Ajit Khapardef6c4bf32011-02-20 11:41:04 +0000638 u32 rsvd0[7];
639 u32 port0_jabber_events;
640 u32 port1_jabber_events;
641 u32 rsvd1[6];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700642};
643
644struct be_erx_stats {
645 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
646 u32 debug_wdma_sent_hold; /* dword 44*/
647 u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
648 u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
649 u32 debug_pmem_pbuf_dealloc; /* dword 47*/
650};
651
Ajit Khapardef6c4bf32011-02-20 11:41:04 +0000652struct be_pmem_stats {
653 u32 eth_red_drops;
654 u32 rsvd[4];
655};
656
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700657struct be_hw_stats {
658 struct be_rxf_stats rxf;
659 u32 rsvd[48];
660 struct be_erx_stats erx;
Ajit Khapardef6c4bf32011-02-20 11:41:04 +0000661 struct be_pmem_stats pmem;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700662};
663
664struct be_cmd_req_get_stats {
665 struct be_cmd_req_hdr hdr;
666 u8 rsvd[sizeof(struct be_hw_stats)];
667};
668
669struct be_cmd_resp_get_stats {
670 struct be_cmd_resp_hdr hdr;
671 struct be_hw_stats hw_stats;
672};
673
Ajit Khaparde609ff3b2011-02-20 11:42:07 +0000674struct be_cmd_req_get_cntl_addnl_attribs {
675 struct be_cmd_req_hdr hdr;
676 u8 rsvd[8];
677};
678
679struct be_cmd_resp_get_cntl_addnl_attribs {
680 struct be_cmd_resp_hdr hdr;
681 u16 ipl_file_number;
682 u8 ipl_file_version;
683 u8 rsvd0;
684 u8 on_die_temperature; /* in degrees centigrade*/
685 u8 rsvd1[3];
686};
687
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700688struct be_cmd_req_vlan_config {
689 struct be_cmd_req_hdr hdr;
690 u8 interface_id;
691 u8 promiscuous;
692 u8 untagged;
693 u8 num_vlan;
694 u16 normal_vlan[64];
695} __packed;
696
697struct be_cmd_req_promiscuous_config {
698 struct be_cmd_req_hdr hdr;
699 u8 port0_promiscuous;
700 u8 port1_promiscuous;
701 u16 rsvd0;
702} __packed;
703
Sathya Perlae7b909a2009-11-22 22:01:10 +0000704/******************** Multicast MAC Config *******************/
705#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700706struct macaddr {
707 u8 byte[ETH_ALEN];
708};
709
710struct be_cmd_req_mcast_mac_config {
711 struct be_cmd_req_hdr hdr;
712 u16 num_mac;
713 u8 promiscuous;
714 u8 interface_id;
Sathya Perlae7b909a2009-11-22 22:01:10 +0000715 struct macaddr mac[BE_MAX_MC];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700716} __packed;
717
718static inline struct be_hw_stats *
719hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
720{
721 return &cmd->hw_stats;
722}
723
724/******************** Link Status Query *******************/
725struct be_cmd_req_link_status {
726 struct be_cmd_req_hdr hdr;
727 u32 rsvd;
728};
729
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700730enum {
731 PHY_LINK_DUPLEX_NONE = 0x0,
732 PHY_LINK_DUPLEX_HALF = 0x1,
733 PHY_LINK_DUPLEX_FULL = 0x2
734};
735
736enum {
737 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
738 PHY_LINK_SPEED_10MBPS = 0x1,
739 PHY_LINK_SPEED_100MBPS = 0x2,
740 PHY_LINK_SPEED_1GBPS = 0x3,
741 PHY_LINK_SPEED_10GBPS = 0x4
742};
743
744struct be_cmd_resp_link_status {
745 struct be_cmd_resp_hdr hdr;
746 u8 physical_port;
747 u8 mac_duplex;
748 u8 mac_speed;
749 u8 mac_fault;
750 u8 mgmt_mac_duplex;
751 u8 mgmt_mac_speed;
Sarveshwar Bandi0388f252009-10-28 04:15:20 -0700752 u16 link_speed;
753 u32 rsvd0;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700754} __packed;
755
Sarveshwar Bandi0388f252009-10-28 04:15:20 -0700756/******************** Port Identification ***************************/
757/* Identifies the type of port attached to NIC */
758struct be_cmd_req_port_type {
759 struct be_cmd_req_hdr hdr;
760 u32 page_num;
761 u32 port;
762};
763
764enum {
765 TR_PAGE_A0 = 0xa0,
766 TR_PAGE_A2 = 0xa2
767};
768
769struct be_cmd_resp_port_type {
770 struct be_cmd_resp_hdr hdr;
771 u32 page_num;
772 u32 port;
773 struct data {
774 u8 identifier;
775 u8 identifier_ext;
776 u8 connector;
777 u8 transceiver[8];
778 u8 rsvd0[3];
779 u8 length_km;
780 u8 length_hm;
781 u8 length_om1;
782 u8 length_om2;
783 u8 length_cu;
784 u8 length_cu_m;
785 u8 vendor_name[16];
786 u8 rsvd;
787 u8 vendor_oui[3];
788 u8 vendor_pn[16];
789 u8 vendor_rev[4];
790 } data;
791};
792
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700793/******************** Get FW Version *******************/
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700794struct be_cmd_req_get_fw_version {
795 struct be_cmd_req_hdr hdr;
796 u8 rsvd0[FW_VER_LEN];
797 u8 rsvd1[FW_VER_LEN];
798} __packed;
799
800struct be_cmd_resp_get_fw_version {
801 struct be_cmd_resp_hdr hdr;
802 u8 firmware_version_string[FW_VER_LEN];
803 u8 fw_on_flash_version_string[FW_VER_LEN];
804} __packed;
805
806/******************** Set Flow Contrl *******************/
807struct be_cmd_req_set_flow_control {
808 struct be_cmd_req_hdr hdr;
809 u16 tx_flow_control;
810 u16 rx_flow_control;
811} __packed;
812
813/******************** Get Flow Contrl *******************/
814struct be_cmd_req_get_flow_control {
815 struct be_cmd_req_hdr hdr;
816 u32 rsvd;
817};
818
819struct be_cmd_resp_get_flow_control {
820 struct be_cmd_resp_hdr hdr;
821 u16 tx_flow_control;
822 u16 rx_flow_control;
823} __packed;
824
825/******************** Modify EQ Delay *******************/
826struct be_cmd_req_modify_eq_delay {
827 struct be_cmd_req_hdr hdr;
828 u32 num_eq;
829 struct {
830 u32 eq_id;
831 u32 phase;
832 u32 delay_multiplier;
833 } delay[8];
834} __packed;
835
836struct be_cmd_resp_modify_eq_delay {
837 struct be_cmd_resp_hdr hdr;
838 u32 rsvd0;
839} __packed;
840
841/******************** Get FW Config *******************/
Sathya Perla3abcded2010-10-03 22:12:27 -0700842#define BE_FUNCTION_CAPS_RSS 0x2
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700843struct be_cmd_req_query_fw_cfg {
844 struct be_cmd_req_hdr hdr;
Sathya Perla3abcded2010-10-03 22:12:27 -0700845 u32 rsvd[31];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700846};
847
848struct be_cmd_resp_query_fw_cfg {
849 struct be_cmd_resp_hdr hdr;
850 u32 be_config_number;
851 u32 asic_revision;
852 u32 phys_port;
Ajit Khaparde3486be22010-07-23 02:04:54 +0000853 u32 function_mode;
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700854 u32 rsvd[26];
Sathya Perla3abcded2010-10-03 22:12:27 -0700855 u32 function_caps;
856};
857
858/******************** RSS Config *******************/
859/* RSS types */
860#define RSS_ENABLE_NONE 0x0
861#define RSS_ENABLE_IPV4 0x1
862#define RSS_ENABLE_TCP_IPV4 0x2
863#define RSS_ENABLE_IPV6 0x4
864#define RSS_ENABLE_TCP_IPV6 0x8
865
866struct be_cmd_req_rss_config {
867 struct be_cmd_req_hdr hdr;
868 u32 if_id;
869 u16 enable_rss;
870 u16 cpu_table_size_log2;
871 u32 hash[10];
872 u8 cpu_table[128];
873 u8 flush;
874 u8 rsvd0[3];
Sathya Perla6b7c5b92009-03-11 23:32:03 -0700875};
876
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -0700877/******************** Port Beacon ***************************/
878
879#define BEACON_STATE_ENABLED 0x1
880#define BEACON_STATE_DISABLED 0x0
881
882struct be_cmd_req_enable_disable_beacon {
883 struct be_cmd_req_hdr hdr;
884 u8 port_num;
885 u8 beacon_state;
886 u8 beacon_duration;
887 u8 status_duration;
888} __packed;
889
890struct be_cmd_resp_enable_disable_beacon {
891 struct be_cmd_resp_hdr resp_hdr;
892 u32 rsvd0;
893} __packed;
894
895struct be_cmd_req_get_beacon_state {
896 struct be_cmd_req_hdr hdr;
897 u8 port_num;
898 u8 rsvd0;
899 u16 rsvd1;
900} __packed;
901
902struct be_cmd_resp_get_beacon_state {
903 struct be_cmd_resp_hdr resp_hdr;
904 u8 beacon_state;
905 u8 rsvd0[3];
906} __packed;
907
Ajit Khaparde84517482009-09-04 03:12:16 +0000908/****************** Firmware Flash ******************/
909struct flashrom_params {
910 u32 op_code;
911 u32 op_type;
912 u32 data_buf_size;
913 u32 offset;
914 u8 data_buf[4];
915};
916
917struct be_cmd_write_flashrom {
918 struct be_cmd_req_hdr hdr;
919 struct flashrom_params params;
920};
921
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +0000922/************************ WOL *******************************/
923struct be_cmd_req_acpi_wol_magic_config{
924 struct be_cmd_req_hdr hdr;
925 u32 rsvd0[145];
926 u8 magic_mac[6];
927 u8 rsvd2[2];
928} __packed;
929
Suresh Rff33a6e2009-12-03 16:15:52 -0800930/********************** LoopBack test *********************/
931struct be_cmd_req_loopback_test {
932 struct be_cmd_req_hdr hdr;
933 u32 loopback_type;
934 u32 num_pkts;
935 u64 pattern;
936 u32 src_port;
937 u32 dest_port;
938 u32 pkt_size;
939};
940
941struct be_cmd_resp_loopback_test {
942 struct be_cmd_resp_hdr resp_hdr;
943 u32 status;
944 u32 num_txfer;
945 u32 num_rx;
946 u32 miscomp_off;
947 u32 ticks_compl;
948};
949
Sarveshwar Bandifced9992009-12-23 04:41:44 +0000950struct be_cmd_req_set_lmode {
951 struct be_cmd_req_hdr hdr;
952 u8 src_port;
953 u8 dest_port;
954 u8 loopback_type;
955 u8 loopback_state;
956};
957
958struct be_cmd_resp_set_lmode {
959 struct be_cmd_resp_hdr resp_hdr;
960 u8 rsvd0[4];
961};
962
Suresh Rff33a6e2009-12-03 16:15:52 -0800963/********************** DDR DMA test *********************/
964struct be_cmd_req_ddrdma_test {
965 struct be_cmd_req_hdr hdr;
966 u64 pattern;
967 u32 byte_count;
968 u32 rsvd0;
969 u8 snd_buff[4096];
970 u8 rsvd1[4096];
971};
972
973struct be_cmd_resp_ddrdma_test {
974 struct be_cmd_resp_hdr hdr;
975 u64 pattern;
976 u32 byte_cnt;
977 u32 snd_err;
978 u8 rsvd0[4096];
979 u8 rcv_buff[4096];
980};
981
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -0800982/*********************** SEEPROM Read ***********************/
983
984#define BE_READ_SEEPROM_LEN 1024
985struct be_cmd_req_seeprom_read {
986 struct be_cmd_req_hdr hdr;
987 u8 rsvd0[BE_READ_SEEPROM_LEN];
988};
989
990struct be_cmd_resp_seeprom_read {
991 struct be_cmd_req_hdr hdr;
992 u8 seeprom_data[BE_READ_SEEPROM_LEN];
993};
994
Ajit Khapardeee3cb622010-07-01 03:51:00 +0000995enum {
996 PHY_TYPE_CX4_10GB = 0,
997 PHY_TYPE_XFP_10GB,
998 PHY_TYPE_SFP_1GB,
999 PHY_TYPE_SFP_PLUS_10GB,
1000 PHY_TYPE_KR_10GB,
1001 PHY_TYPE_KX4_10GB,
1002 PHY_TYPE_BASET_10GB,
1003 PHY_TYPE_BASET_1GB,
1004 PHY_TYPE_DISABLED = 255
1005};
1006
1007struct be_cmd_req_get_phy_info {
1008 struct be_cmd_req_hdr hdr;
1009 u8 rsvd0[24];
1010};
1011struct be_cmd_resp_get_phy_info {
1012 struct be_cmd_req_hdr hdr;
1013 u16 phy_type;
1014 u16 interface_type;
1015 u32 misc_params;
1016 u32 future_use[4];
1017};
1018
Ajit Khapardee1d18732010-07-23 01:52:13 +00001019/*********************** Set QOS ***********************/
1020
1021#define BE_QOS_BITS_NIC 1
1022
1023struct be_cmd_req_set_qos {
1024 struct be_cmd_req_hdr hdr;
1025 u32 valid_bits;
1026 u32 max_bps_nic;
1027 u32 rsvd[7];
1028};
1029
1030struct be_cmd_resp_set_qos {
1031 struct be_cmd_resp_hdr hdr;
1032 u32 rsvd;
1033};
1034
Ajit Khaparde9e1453c2011-02-20 11:42:22 +00001035/*********************** Controller Attributes ***********************/
1036struct be_cmd_req_cntl_attribs {
1037 struct be_cmd_req_hdr hdr;
1038};
1039
1040struct be_cmd_resp_cntl_attribs {
1041 struct be_cmd_resp_hdr hdr;
1042 struct mgmt_controller_attrib attribs;
1043};
1044
Sathya Perla8788fdc2009-07-27 22:52:03 +00001045extern int be_pci_fnum_get(struct be_adapter *adapter);
1046extern int be_cmd_POST(struct be_adapter *adapter);
1047extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001048 u8 type, bool permanent, u32 if_handle);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001049extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
Ajit Khapardef8617e02011-02-11 13:36:37 +00001050 u32 if_id, u32 *pmac_id, u32 domain);
1051extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1052 u32 pmac_id, u32 domain);
Sathya Perla73d540f2009-10-14 20:20:42 +00001053extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1054 u32 en_flags, u8 *mac, bool pmac_invalid,
Sarveshwar Bandiba343c72010-03-31 02:56:12 +00001055 u32 *if_handle, u32 *pmac_id, u32 domain);
Ajit Khaparde658681f2011-02-11 13:34:46 +00001056extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1057 u32 domain);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001058extern int be_cmd_eq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001059 struct be_queue_info *eq, int eq_delay);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001060extern int be_cmd_cq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001061 struct be_queue_info *cq, struct be_queue_info *eq,
1062 bool sol_evts, bool no_delay,
1063 int num_cqe_dma_coalesce);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001064extern int be_cmd_mccq_create(struct be_adapter *adapter,
Sathya Perla5fb379e2009-06-18 00:02:59 +00001065 struct be_queue_info *mccq,
1066 struct be_queue_info *cq);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001067extern int be_cmd_txq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001068 struct be_queue_info *txq,
1069 struct be_queue_info *cq);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001070extern int be_cmd_rxq_create(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001071 struct be_queue_info *rxq, u16 cq_id,
1072 u16 frag_size, u16 max_frame_size, u32 if_id,
Sathya Perla3abcded2010-10-03 22:12:27 -07001073 u32 rss, u8 *rss_id);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001074extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001075 int type);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001076extern int be_cmd_link_status_query(struct be_adapter *adapter,
Sarveshwar Bandi0388f252009-10-28 04:15:20 -07001077 bool *link_up, u8 *mac_speed, u16 *link_speed);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001078extern int be_cmd_reset(struct be_adapter *adapter);
1079extern int be_cmd_get_stats(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001080 struct be_dma_mem *nonemb_cmd);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001081extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001082
Sathya Perla8788fdc2009-07-27 22:52:03 +00001083extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1084extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001085 u16 *vtag_array, u32 num, bool untagged,
1086 bool promiscuous);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001087extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001088 u8 port_num, bool en);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001089extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
Jiri Pirko0ddf4772010-02-20 00:13:58 +00001090 struct net_device *netdev, struct be_dma_mem *mem);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001091extern int be_cmd_set_flow_control(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001092 u32 tx_fc, u32 rx_fc);
Sathya Perla8788fdc2009-07-27 22:52:03 +00001093extern int be_cmd_get_flow_control(struct be_adapter *adapter,
Sathya Perla6b7c5b92009-03-11 23:32:03 -07001094 u32 *tx_fc, u32 *rx_fc);
Ajit Khapardedcb9b562009-09-30 21:58:22 -07001095extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
Sathya Perla3abcded2010-10-03 22:12:27 -07001096 u32 *port_num, u32 *function_mode, u32 *function_caps);
sarveshwarb14074ea2009-08-05 13:05:24 -07001097extern int be_cmd_reset_function(struct be_adapter *adapter);
Sathya Perla3abcded2010-10-03 22:12:27 -07001098extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1099 u16 table_size);
Sathya Perlaf31e50a2010-03-02 03:56:39 -08001100extern int be_process_mcc(struct be_adapter *adapter, int *status);
Sarveshwar Bandifad9ab22009-10-12 04:23:15 -07001101extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1102 u8 port_num, u8 beacon, u8 status, u8 state);
1103extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1104 u8 port_num, u32 *state);
Ajit Khaparde84517482009-09-04 03:12:16 +00001105extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1106 struct be_dma_mem *cmd, u32 flash_oper,
1107 u32 flash_opcode, u32 buf_size);
Ajit Khaparde3f0d4562010-02-09 01:30:35 +00001108int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1109 int offset);
Ajit Khaparde71d8d1b2009-12-03 06:16:59 +00001110extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1111 struct be_dma_mem *nonemb_cmd);
Sathya Perla2243e2e2009-11-22 22:02:03 +00001112extern int be_cmd_fw_init(struct be_adapter *adapter);
1113extern int be_cmd_fw_clean(struct be_adapter *adapter);
Sathya Perla7a1e9b22010-02-17 01:35:11 +00001114extern void be_async_mcc_enable(struct be_adapter *adapter);
1115extern void be_async_mcc_disable(struct be_adapter *adapter);
Suresh Rff33a6e2009-12-03 16:15:52 -08001116extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1117 u32 loopback_type, u32 pkt_size,
1118 u32 num_pkts, u64 pattern);
1119extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1120 u32 byte_cnt, struct be_dma_mem *cmd);
Sarveshwar Bandi368c0ca2010-01-08 00:07:27 -08001121extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1122 struct be_dma_mem *nonemb_cmd);
Sarveshwar Bandifced9992009-12-23 04:41:44 +00001123extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1124 u8 loopback_type, u8 enable);
Ajit Khapardeee3cb622010-07-01 03:51:00 +00001125extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1126 struct be_dma_mem *cmd);
Ajit Khapardee1d18732010-07-23 01:52:13 +00001127extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
Ajit Khaparded053de92010-09-03 06:23:30 +00001128extern void be_detect_dump_ue(struct be_adapter *adapter);
Ajit Khaparde609ff3b2011-02-20 11:42:07 +00001129extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
Ajit Khaparde9e1453c2011-02-20 11:42:22 +00001130extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
David S. Millerd4a66e72010-01-10 22:55:03 -08001131