Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 1 | Generic CPU0 cpufreq driver |
| 2 | |
| 3 | It is a generic cpufreq driver for CPU0 frequency management. It |
| 4 | supports both uniprocessor (UP) and symmetric multiprocessor (SMP) |
| 5 | systems which share clock and voltage across all CPUs. |
| 6 | |
| 7 | Both required and optional properties listed below must be defined |
| 8 | under node /cpus/cpu@0. |
| 9 | |
| 10 | Required properties: |
| 11 | - operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt |
| 12 | for details |
| 13 | |
| 14 | Optional properties: |
| 15 | - clock-latency: Specify the possible maximum transition latency for clock, |
| 16 | in unit of nanoseconds. |
| 17 | - voltage-tolerance: Specify the CPU voltage tolerance in percentage. |
| 18 | |
| 19 | Examples: |
| 20 | |
| 21 | cpus { |
| 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; |
| 24 | |
| 25 | cpu@0 { |
| 26 | compatible = "arm,cortex-a9"; |
| 27 | reg = <0>; |
| 28 | next-level-cache = <&L2>; |
| 29 | operating-points = < |
| 30 | /* kHz uV */ |
| 31 | 792000 1100000 |
| 32 | 396000 950000 |
| 33 | 198000 850000 |
| 34 | >; |
| 35 | transition-latency = <61036>; /* two CLK32 periods */ |
| 36 | }; |
| 37 | |
| 38 | cpu@1 { |
| 39 | compatible = "arm,cortex-a9"; |
| 40 | reg = <1>; |
| 41 | next-level-cache = <&L2>; |
| 42 | }; |
| 43 | |
| 44 | cpu@2 { |
| 45 | compatible = "arm,cortex-a9"; |
| 46 | reg = <2>; |
| 47 | next-level-cache = <&L2>; |
| 48 | }; |
| 49 | |
| 50 | cpu@3 { |
| 51 | compatible = "arm,cortex-a9"; |
| 52 | reg = <3>; |
| 53 | next-level-cache = <&L2>; |
| 54 | }; |
| 55 | }; |