Blame - drivers/gpu/drm/radeon/evergreend.h - android_kernel_oneplus_msm8996

2010-03-24 13:20:41 -0400

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/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Alex Deucher

*/

#ifndef EVERGREEND_H

#define EVERGREEND_H

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#define EVERGREEN_MAX_SH_GPRS 256

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#define EVERGREEN_MAX_TEMP_GPRS 16

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#define EVERGREEN_MAX_SH_THREADS 256

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#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096

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#define EVERGREEN_MAX_FRC_EOV_CNT 16384

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#define EVERGREEN_MAX_BACKENDS 8

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#define EVERGREEN_MAX_BACKENDS_MASK 0xFF

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#define EVERGREEN_MAX_SIMDS 16

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#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF

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#define EVERGREEN_MAX_PIPES 8

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#define EVERGREEN_MAX_PIPES_MASK 0xFF

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#define EVERGREEN_MAX_LDS_NUM 0xFFFF

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#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003

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#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003

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#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003

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#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001

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#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001

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#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002

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#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002

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/* pm registers */

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#define SMC_MSG 0x20c

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#define HOST_SMC_MSG(x) ((x) << 0)

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#define HOST_SMC_MSG_MASK (0xff << 0)

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#define HOST_SMC_MSG_SHIFT 0

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#define HOST_SMC_RESP(x) ((x) << 8)

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#define HOST_SMC_RESP_MASK (0xff << 8)

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#define HOST_SMC_RESP_SHIFT 8

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#define SMC_HOST_MSG(x) ((x) << 16)

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#define SMC_HOST_MSG_MASK (0xff << 16)

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#define SMC_HOST_MSG_SHIFT 16

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#define SMC_HOST_RESP(x) ((x) << 24)

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#define SMC_HOST_RESP_MASK (0xff << 24)

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#define SMC_HOST_RESP_SHIFT 24

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#define DCCG_DISP_SLOW_SELECT_REG 0x4fc

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#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)

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#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)

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#define DCCG_DISP1_SLOW_SELECT_SHIFT 0

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#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)

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#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)

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#define DCCG_DISP2_SLOW_SELECT_SHIFT 4

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#define CG_SPLL_FUNC_CNTL 0x600

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#define SPLL_RESET (1 << 0)

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#define SPLL_SLEEP (1 << 1)

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#define SPLL_BYPASS_EN (1 << 3)

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#define SPLL_REF_DIV(x) ((x) << 4)

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#define SPLL_REF_DIV_MASK (0x3f << 4)

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#define SPLL_PDIV_A(x) ((x) << 20)

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#define SPLL_PDIV_A_MASK (0x7f << 20)

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#define CG_SPLL_FUNC_CNTL_2 0x604

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#define SCLK_MUX_SEL(x) ((x) << 0)

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#define SCLK_MUX_SEL_MASK (0x1ff << 0)

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#define CG_SPLL_FUNC_CNTL_3 0x608

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#define SPLL_FB_DIV(x) ((x) << 0)

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#define SPLL_FB_DIV_MASK (0x3ffffff << 0)

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#define SPLL_DITHEN (1 << 28)

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#define MPLL_CNTL_MODE 0x61c

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# define SS_SSEN (1 << 24)

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# define SS_DSMODE_EN (1 << 25)

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#define MPLL_AD_FUNC_CNTL 0x624

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#define CLKF(x) ((x) << 0)

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#define CLKF_MASK (0x7f << 0)

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#define CLKR(x) ((x) << 7)

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#define CLKR_MASK (0x1f << 7)

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#define CLKFRAC(x) ((x) << 12)

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#define CLKFRAC_MASK (0x1f << 12)

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#define YCLK_POST_DIV(x) ((x) << 17)

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#define YCLK_POST_DIV_MASK (3 << 17)

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#define IBIAS(x) ((x) << 20)

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#define IBIAS_MASK (0x3ff << 20)

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#define RESET (1 << 30)

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#define PDNB (1 << 31)

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#define MPLL_AD_FUNC_CNTL_2 0x628

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#define BYPASS (1 << 19)

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#define BIAS_GEN_PDNB (1 << 24)

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#define RESET_EN (1 << 25)

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#define VCO_MODE (1 << 29)

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#define MPLL_DQ_FUNC_CNTL 0x62c

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#define MPLL_DQ_FUNC_CNTL_2 0x630

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#define GENERAL_PWRMGT 0x63c

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# define GLOBAL_PWRMGT_EN (1 << 0)

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# define STATIC_PM_EN (1 << 1)

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# define THERMAL_PROTECTION_DIS (1 << 2)

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# define THERMAL_PROTECTION_TYPE (1 << 3)

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# define ENABLE_GEN2PCIE (1 << 4)

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# define ENABLE_GEN2XSP (1 << 5)

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# define SW_SMIO_INDEX(x) ((x) << 6)

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# define SW_SMIO_INDEX_MASK (3 << 6)

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# define SW_SMIO_INDEX_SHIFT 6

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# define LOW_VOLT_D2_ACPI (1 << 8)

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# define LOW_VOLT_D3_ACPI (1 << 9)

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# define VOLT_PWRMGT_EN (1 << 10)

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# define BACKBIAS_PAD_EN (1 << 18)

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# define BACKBIAS_VALUE (1 << 19)

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# define DYN_SPREAD_SPECTRUM_EN (1 << 23)

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# define AC_DC_SW (1 << 24)

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#define SCLK_PWRMGT_CNTL 0x644

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# define SCLK_PWRMGT_OFF (1 << 0)

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# define SCLK_LOW_D1 (1 << 1)

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# define FIR_RESET (1 << 4)

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# define FIR_FORCE_TREND_SEL (1 << 5)

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# define FIR_TREND_MODE (1 << 6)

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# define DYN_GFX_CLK_OFF_EN (1 << 7)

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# define GFX_CLK_FORCE_ON (1 << 8)

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# define GFX_CLK_REQUEST_OFF (1 << 9)

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# define GFX_CLK_FORCE_OFF (1 << 10)

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# define GFX_CLK_OFF_ACPI_D1 (1 << 11)

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# define GFX_CLK_OFF_ACPI_D2 (1 << 12)

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# define GFX_CLK_OFF_ACPI_D3 (1 << 13)

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# define DYN_LIGHT_SLEEP_EN (1 << 14)

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#define MCLK_PWRMGT_CNTL 0x648

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# define DLL_SPEED(x) ((x) << 0)

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# define DLL_SPEED_MASK (0x1f << 0)

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# define MPLL_PWRMGT_OFF (1 << 5)

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# define DLL_READY (1 << 6)

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# define MC_INT_CNTL (1 << 7)

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# define MRDCKA0_PDNB (1 << 8)

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# define MRDCKA1_PDNB (1 << 9)

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# define MRDCKB0_PDNB (1 << 10)

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# define MRDCKB1_PDNB (1 << 11)

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# define MRDCKC0_PDNB (1 << 12)

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# define MRDCKC1_PDNB (1 << 13)

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# define MRDCKD0_PDNB (1 << 14)

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# define MRDCKD1_PDNB (1 << 15)

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# define MRDCKA0_RESET (1 << 16)

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# define MRDCKA1_RESET (1 << 17)

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# define MRDCKB0_RESET (1 << 18)

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# define MRDCKB1_RESET (1 << 19)

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# define MRDCKC0_RESET (1 << 20)

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# define MRDCKC1_RESET (1 << 21)

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# define MRDCKD0_RESET (1 << 22)

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# define MRDCKD1_RESET (1 << 23)

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# define DLL_READY_READ (1 << 24)

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# define USE_DISPLAY_GAP (1 << 25)

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# define USE_DISPLAY_URGENT_NORMAL (1 << 26)

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# define MPLL_TURNOFF_D2 (1 << 28)

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#define DLL_CNTL 0x64c

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# define MRDCKA0_BYPASS (1 << 24)

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# define MRDCKA1_BYPASS (1 << 25)

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# define MRDCKB0_BYPASS (1 << 26)

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# define MRDCKB1_BYPASS (1 << 27)

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# define MRDCKC0_BYPASS (1 << 28)

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# define MRDCKC1_BYPASS (1 << 29)

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# define MRDCKD0_BYPASS (1 << 30)

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# define MRDCKD1_BYPASS (1 << 31)

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#define CG_AT 0x6d4

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# define CG_R(x) ((x) << 0)

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# define CG_R_MASK (0xffff << 0)

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# define CG_L(x) ((x) << 16)

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# define CG_L_MASK (0xffff << 16)

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#define CG_DISPLAY_GAP_CNTL 0x714

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# define DISP1_GAP(x) ((x) << 0)

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# define DISP1_GAP_MASK (3 << 0)

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# define DISP2_GAP(x) ((x) << 2)

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# define DISP2_GAP_MASK (3 << 2)

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# define VBI_TIMER_COUNT(x) ((x) << 4)

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# define VBI_TIMER_COUNT_MASK (0x3fff << 4)

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# define VBI_TIMER_UNIT(x) ((x) << 20)

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# define VBI_TIMER_UNIT_MASK (7 << 20)

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# define DISP1_GAP_MCHG(x) ((x) << 24)

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# define DISP1_GAP_MCHG_MASK (3 << 24)

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# define DISP2_GAP_MCHG(x) ((x) << 26)

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# define DISP2_GAP_MCHG_MASK (3 << 26)

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#define CG_BIF_REQ_AND_RSP 0x7f4

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#define CG_CLIENT_REQ(x) ((x) << 0)

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#define CG_CLIENT_REQ_MASK (0xff << 0)

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#define CG_CLIENT_REQ_SHIFT 0

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#define CG_CLIENT_RESP(x) ((x) << 8)

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#define CG_CLIENT_RESP_MASK (0xff << 8)

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#define CG_CLIENT_RESP_SHIFT 8

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#define CLIENT_CG_REQ(x) ((x) << 16)

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#define CLIENT_CG_REQ_MASK (0xff << 16)

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#define CLIENT_CG_REQ_SHIFT 16

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#define CLIENT_CG_RESP(x) ((x) << 24)

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#define CLIENT_CG_RESP_MASK (0xff << 24)

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#define CLIENT_CG_RESP_SHIFT 24

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#define CG_SPLL_SPREAD_SPECTRUM 0x790

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#define SSEN (1 << 0)

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#define CG_SPLL_SPREAD_SPECTRUM_2 0x794

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#define MPLL_SS1 0x85c

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#define CLKV(x) ((x) << 0)

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#define CLKV_MASK (0x3ffffff << 0)

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#define MPLL_SS2 0x860

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#define CLKS(x) ((x) << 0)

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#define CLKS_MASK (0xfff << 0)

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#define CG_IND_ADDR 0x8f8

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#define CG_IND_DATA 0x8fc

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/* CGIND regs */

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#define CG_CGTT_LOCAL_0 0x00

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#define CG_CGTT_LOCAL_1 0x01

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#define CG_CGTT_LOCAL_2 0x02

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#define CG_CGTT_LOCAL_3 0x03

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#define CG_CGLS_TILE_0 0x20

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#define CG_CGLS_TILE_1 0x21

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#define CG_CGLS_TILE_2 0x22

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#define CG_CGLS_TILE_3 0x23

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#define CG_CGLS_TILE_4 0x24

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#define CG_CGLS_TILE_5 0x25

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#define CG_CGLS_TILE_6 0x26

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#define CG_CGLS_TILE_7 0x27

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#define CG_CGLS_TILE_8 0x28

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#define CG_CGLS_TILE_9 0x29

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#define CG_CGLS_TILE_10 0x2a

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#define CG_CGLS_TILE_11 0x2b

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#define VM_L2_CG 0x15c0

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#define MC_CONFIG 0x2000

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#define MC_CONFIG_MCD 0x20a0

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#define MC_CG_CONFIG_MCD 0x20a4

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#define MC_RD_ENABLE_MCD(x) ((x) << 8)

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#define MC_RD_ENABLE_MCD_MASK (7 << 8)

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#define MC_HUB_MISC_HUB_CG 0x20b8

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#define MC_HUB_MISC_VM_CG 0x20bc

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#define MC_HUB_MISC_SIP_CG 0x20c0

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#define MC_XPB_CLK_GAT 0x2478

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#define MC_CG_CONFIG 0x25bc

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#define MC_RD_ENABLE(x) ((x) << 4)

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#define MC_RD_ENABLE_MASK (3 << 4)

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#define MC_CITF_MISC_RD_CG 0x2648

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#define MC_CITF_MISC_WR_CG 0x264c

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#define MC_CITF_MISC_VM_CG 0x2650

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# define MEM_LS_ENABLE (1 << 19)

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#define MC_ARB_BURST_TIME 0x2808

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#define STATE0(x) ((x) << 0)

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#define STATE0_MASK (0x1f << 0)

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#define STATE1(x) ((x) << 5)

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#define STATE1_MASK (0x1f << 5)

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#define STATE2(x) ((x) << 10)

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#define STATE2_MASK (0x1f << 10)

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#define STATE3(x) ((x) << 15)

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#define STATE3_MASK (0x1f << 15)

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#define MC_SEQ_RAS_TIMING 0x28a0

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#define MC_SEQ_CAS_TIMING 0x28a4

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#define MC_SEQ_MISC_TIMING 0x28a8

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#define MC_SEQ_MISC_TIMING2 0x28ac

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#define MC_SEQ_RD_CTL_D0 0x28b4

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#define MC_SEQ_RD_CTL_D1 0x28b8

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#define MC_SEQ_WR_CTL_D0 0x28bc

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#define MC_SEQ_WR_CTL_D1 0x28c0

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#define MC_SEQ_STATUS_M 0x29f4

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# define PMG_PWRSTATE (1 << 16)

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#define MC_SEQ_MISC1 0x2a04

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#define MC_SEQ_RESERVE_M 0x2a08

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#define MC_PMG_CMD_EMRS 0x2a0c

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#define MC_SEQ_MISC3 0x2a2c

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#define MC_SEQ_MISC5 0x2a54

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#define MC_SEQ_MISC6 0x2a58

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#define MC_SEQ_MISC7 0x2a64

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#define MC_SEQ_CG 0x2a68

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#define CG_SEQ_REQ(x) ((x) << 0)

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#define CG_SEQ_REQ_MASK (0xff << 0)

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#define CG_SEQ_REQ_SHIFT 0

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#define CG_SEQ_RESP(x) ((x) << 8)

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#define CG_SEQ_RESP_MASK (0xff << 8)

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#define CG_SEQ_RESP_SHIFT 8

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#define SEQ_CG_REQ(x) ((x) << 16)

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#define SEQ_CG_REQ_MASK (0xff << 16)

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#define SEQ_CG_REQ_SHIFT 16

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#define SEQ_CG_RESP(x) ((x) << 24)

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#define SEQ_CG_RESP_MASK (0xff << 24)

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#define SEQ_CG_RESP_SHIFT 24

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#define MC_SEQ_RAS_TIMING_LP 0x2a6c

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#define MC_SEQ_CAS_TIMING_LP 0x2a70

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#define MC_SEQ_MISC_TIMING_LP 0x2a74

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#define MC_SEQ_MISC_TIMING2_LP 0x2a78

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#define MC_SEQ_WR_CTL_D0_LP 0x2a7c

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#define MC_SEQ_WR_CTL_D1_LP 0x2a80

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#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84

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#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88

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#define MC_PMG_CMD_MRS 0x2aac

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#define MC_SEQ_RD_CTL_D0_LP 0x2b1c

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#define MC_SEQ_RD_CTL_D1_LP 0x2b20

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#define MC_PMG_CMD_MRS1 0x2b44

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#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48

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#define CGTS_SM_CTRL_REG 0x9150

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2010-03-24 13:20:41 -0400

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/* Registers */

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2010-03-24 13:33:47 -0400

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#define RCU_IND_INDEX 0x100

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#define RCU_IND_DATA 0x104

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/* discrete uvd clocks */

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#define CG_UPLL_FUNC_CNTL 0x718

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# define UPLL_RESET_MASK 0x00000001

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# define UPLL_SLEEP_MASK 0x00000002

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# define UPLL_BYPASS_EN_MASK 0x00000004

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# define UPLL_CTLREQ_MASK 0x00000008

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2013-04-29 10:20:23 +0200

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# define UPLL_REF_DIV_MASK 0x003F0000

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# define UPLL_VCO_MODE_MASK 0x00000200

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# define UPLL_CTLACK_MASK 0x40000000

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# define UPLL_CTLACK2_MASK 0x80000000

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#define CG_UPLL_FUNC_CNTL_2 0x71c

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# define UPLL_PDIV_A(x) ((x) << 0)

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# define UPLL_PDIV_A_MASK 0x0000007F

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# define UPLL_PDIV_B(x) ((x) << 8)

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# define UPLL_PDIV_B_MASK 0x00007F00

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# define VCLK_SRC_SEL(x) ((x) << 20)

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# define VCLK_SRC_SEL_MASK 0x01F00000

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# define DCLK_SRC_SEL(x) ((x) << 25)

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# define DCLK_SRC_SEL_MASK 0x3E000000

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#define CG_UPLL_FUNC_CNTL_3 0x720

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# define UPLL_FB_DIV(x) ((x) << 0)

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# define UPLL_FB_DIV_MASK 0x01FFFFFF

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#define CG_UPLL_FUNC_CNTL_4 0x854

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# define UPLL_SPARE_ISPARE9 0x00020000

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#define CG_UPLL_SPREAD_SPECTRUM 0x79c

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# define SSEN_MASK 0x00000001

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2013-04-08 12:41:32 +0200

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/* fusion uvd clocks */

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#define CG_DCLK_CNTL 0x610

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# define DCLK_DIVIDER_MASK 0x7f

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# define DCLK_DIR_CNTL_EN (1 << 8)

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#define CG_DCLK_STATUS 0x614

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# define DCLK_STATUS (1 << 0)

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#define CG_VCLK_CNTL 0x618

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#define CG_VCLK_STATUS 0x61c

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#define CG_SCRATCH1 0x820

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Alex Deucher

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2013-04-12 13:52:52 -0400

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#define RLC_CNTL 0x3f00

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# define RLC_ENABLE (1 << 0)

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# define GFX_POWER_GATING_ENABLE (1 << 7)

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# define GFX_POWER_GATING_SRC (1 << 8)

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#define RLC_HB_BASE 0x3f10

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#define RLC_HB_CNTL 0x3f0c

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#define RLC_HB_RPTR 0x3f20

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#define RLC_HB_WPTR 0x3f1c

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#define RLC_HB_WPTR_LSB_ADDR 0x3f14

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#define RLC_HB_WPTR_MSB_ADDR 0x3f18

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#define RLC_MC_CNTL 0x3f44

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#define RLC_UCODE_CNTL 0x3f48

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#define RLC_UCODE_ADDR 0x3f2c

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#define RLC_UCODE_DATA 0x3f30

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/* new for TN */

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#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10

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#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20

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2010-03-24 13:33:47 -0400

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#define GRBM_GFX_INDEX 0x802C

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#define INSTANCE_INDEX(x) ((x) << 0)

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#define SE_INDEX(x) ((x) << 16)

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#define INSTANCE_BROADCAST_WRITES (1 << 30)

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#define SE_BROADCAST_WRITES (1 << 31)

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#define RLC_GFX_INDEX 0x3fC4

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#define CC_GC_SHADER_PIPE_CONFIG 0x8950

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#define WRITE_DIS (1 << 0)

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#define CC_RB_BACKEND_DISABLE 0x98F4

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#define BACKEND_DISABLE(x) ((x) << 16)

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#define GB_ADDR_CONFIG 0x98F8

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#define NUM_PIPES(x) ((x) << 0)

Alex Deucher

416a2bd

2012-05-31 19:00:25 -0400

[diff] [blame]

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#define NUM_PIPES_MASK 0x0000000f

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2010-03-24 13:33:47 -0400

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#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)

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#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)

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#define NUM_SHADER_ENGINES(x) ((x) << 12)

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#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)

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#define NUM_GPUS(x) ((x) << 20)

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#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)

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#define ROW_SIZE(x) ((x) << 28)

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#define GB_BACKEND_MAP 0x98FC

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#define DMIF_ADDR_CONFIG 0xBD4

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#define HDP_ADDR_CONFIG 0x2F48

Alex Deucher

f25a5c6

2011-05-19 11:07:57 -0400

[diff] [blame]

422

#define HDP_MISC_CNTL 0x2F4C

423

#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

424

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

425

#define CC_SYS_RB_BACKEND_DISABLE 0x3F88

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

426

#define GC_USER_RB_BACKEND_DISABLE 0x9B7C

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

427

428

#define CGTS_SYS_TCC_DISABLE 0x3F90

429

#define CGTS_TCC_DISABLE 0x9148

430

#define CGTS_USER_SYS_TCC_DISABLE 0x3F94

431

#define CGTS_USER_TCC_DISABLE 0x914C

432

433

#define CONFIG_MEMSIZE 0x5428

434

Alex Deucher

62444b7

2012-08-15 17:18:42 -0400

[diff] [blame]

435

#define BIF_FB_EN 0x5490

436

#define FB_READ_EN (1 << 0)

437

#define FB_WRITE_EN (1 << 1)

438

Alex Deucher

860fe2f

2012-11-08 10:08:04 -0500

[diff] [blame]

439

#define CP_STRMOUT_CNTL 0x84FC

440

441

#define CP_COHER_CNTL 0x85F0

442

#define CP_COHER_SIZE 0x85F4

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

443

#define CP_COHER_BASE 0x85F8

Jerome Glisse

440a7cd

2012-06-27 12:25:01 -0400

[diff] [blame]

444

#define CP_STALLED_STAT1 0x8674

445

#define CP_STALLED_STAT2 0x8678

446

#define CP_BUSY_STAT 0x867C

447

#define CP_STAT 0x8680

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

448

#define CP_ME_CNTL 0x86D8

449

#define CP_ME_HALT (1 << 28)

450

#define CP_PFP_HALT (1 << 26)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

451

#define CP_ME_RAM_DATA 0xC160

452

#define CP_ME_RAM_RADDR 0xC158

453

#define CP_ME_RAM_WADDR 0xC15C

454

#define CP_MEQ_THRESHOLDS 0x8764

455

#define STQ_SPLIT(x) ((x) << 0)

456

#define CP_PERFMON_CNTL 0x87FC

457

#define CP_PFP_UCODE_ADDR 0xC150

458

#define CP_PFP_UCODE_DATA 0xC154

459

#define CP_QUEUE_THRESHOLDS 0x8760

460

#define ROQ_IB1_START(x) ((x) << 0)

461

#define ROQ_IB2_START(x) ((x) << 8)

Alex Deucher

fe251e2

2010-03-24 13:36:43 -0400

[diff] [blame]

462

#define CP_RB_BASE 0xC100

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

463

#define CP_RB_CNTL 0xC104

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

464

#define RB_BUFSZ(x) ((x) << 0)

465

#define RB_BLKSZ(x) ((x) << 8)

466

#define RB_NO_UPDATE (1 << 27)

467

#define RB_RPTR_WR_ENA (1 << 31)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

468

#define BUF_SWAP_32BIT (2 << 16)

469

#define CP_RB_RPTR 0x8700

470

#define CP_RB_RPTR_ADDR 0xC10C

Alex Deucher

0f234f5f

2011-02-13 19:06:33 -0500

[diff] [blame]

471

#define RB_RPTR_SWAP(x) ((x) << 0)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

472

#define CP_RB_RPTR_ADDR_HI 0xC110

473

#define CP_RB_RPTR_WR 0xC108

474

#define CP_RB_WPTR 0xC114

475

#define CP_RB_WPTR_ADDR 0xC118

476

#define CP_RB_WPTR_ADDR_HI 0xC11C

477

#define CP_RB_WPTR_DELAY 0x8704

478

#define CP_SEM_WAIT_TIMER 0x85BC

Alex Deucher

11ef3f1

2012-01-20 14:47:43 -0500

[diff] [blame]

479

#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8

Alex Deucher

fe251e2

2010-03-24 13:36:43 -0400

[diff] [blame]

480

#define CP_DEBUG 0xC1FC

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

481

Alex Deucher

3a2a67a

2012-03-28 13:19:06 -0400

[diff] [blame]

482

/* Audio clocks */

483

#define DCCG_AUDIO_DTO_SOURCE 0x05ac

484

# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */

485

# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */

486

487

#define DCCG_AUDIO_DTO0_PHASE 0x05b0

488

#define DCCG_AUDIO_DTO0_MODULE 0x05b4

489

#define DCCG_AUDIO_DTO0_LOAD 0x05b8

490

#define DCCG_AUDIO_DTO0_CNTL 0x05bc

491

492

#define DCCG_AUDIO_DTO1_PHASE 0x05c0

493

#define DCCG_AUDIO_DTO1_MODULE 0x05c4

494

#define DCCG_AUDIO_DTO1_LOAD 0x05c8

495

#define DCCG_AUDIO_DTO1_CNTL 0x05cc

496

497

/* DCE 4.0 AFMT */

498

#define HDMI_CONTROL 0x7030

499

# define HDMI_KEEPOUT_MODE (1 << 0)

500

# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */

501

# define HDMI_ERROR_ACK (1 << 8)

502

# define HDMI_ERROR_MASK (1 << 9)

503

# define HDMI_DEEP_COLOR_ENABLE (1 << 24)

504

# define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28)

505

# define HDMI_24BIT_DEEP_COLOR 0

506

# define HDMI_30BIT_DEEP_COLOR 1

507

# define HDMI_36BIT_DEEP_COLOR 2

508

#define HDMI_STATUS 0x7034

509

# define HDMI_ACTIVE_AVMUTE (1 << 0)

510

# define HDMI_AUDIO_PACKET_ERROR (1 << 16)

511

# define HDMI_VBI_PACKET_ERROR (1 << 20)

512

#define HDMI_AUDIO_PACKET_CONTROL 0x7038

513

# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)

514

# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)

515

#define HDMI_ACR_PACKET_CONTROL 0x703c

516

# define HDMI_ACR_SEND (1 << 0)

517

# define HDMI_ACR_CONT (1 << 1)

518

# define HDMI_ACR_SELECT(x) (((x) & 3) << 4)

519

# define HDMI_ACR_HW 0

520

# define HDMI_ACR_32 1

521

# define HDMI_ACR_44 2

522

# define HDMI_ACR_48 3

523

# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */

524

# define HDMI_ACR_AUTO_SEND (1 << 12)

525

# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16)

526

# define HDMI_ACR_X1 1

527

# define HDMI_ACR_X2 2

528

# define HDMI_ACR_X4 4

529

# define HDMI_ACR_AUDIO_PRIORITY (1 << 31)

530

#define HDMI_VBI_PACKET_CONTROL 0x7040

531

# define HDMI_NULL_SEND (1 << 0)

532

# define HDMI_GC_SEND (1 << 4)

533

# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */

534

#define HDMI_INFOFRAME_CONTROL0 0x7044

535

# define HDMI_AVI_INFO_SEND (1 << 0)

536

# define HDMI_AVI_INFO_CONT (1 << 1)

537

# define HDMI_AUDIO_INFO_SEND (1 << 4)

538

# define HDMI_AUDIO_INFO_CONT (1 << 5)

539

# define HDMI_MPEG_INFO_SEND (1 << 8)

540

# define HDMI_MPEG_INFO_CONT (1 << 9)

541

#define HDMI_INFOFRAME_CONTROL1 0x7048

542

# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)

Rafał Miłecki

d3418ea

2013-04-18 09:23:12 -0400

[diff] [blame]

543

# define HDMI_AVI_INFO_LINE_MASK (0x3f << 0)

Alex Deucher

3a2a67a

2012-03-28 13:19:06 -0400

[diff] [blame]

544

# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)

545

# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)

546

#define HDMI_GENERIC_PACKET_CONTROL 0x704c

547

# define HDMI_GENERIC0_SEND (1 << 0)

548

# define HDMI_GENERIC0_CONT (1 << 1)

549

# define HDMI_GENERIC1_SEND (1 << 4)

550

# define HDMI_GENERIC1_CONT (1 << 5)

551

# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)

552

# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)

553

#define HDMI_GC 0x7058

554

# define HDMI_GC_AVMUTE (1 << 0)

555

# define HDMI_GC_AVMUTE_CONT (1 << 2)

556

#define AFMT_AUDIO_PACKET_CONTROL2 0x705c

557

# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)

558

# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)

559

# define AFMT_60958_CS_SOURCE (1 << 4)

560

# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)

561

# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)

562

#define AFMT_AVI_INFO0 0x7084

563

# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

564

# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)

565

# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)

566

# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)

567

# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)

568

# define AFMT_AVI_INFO_Y_RGB 0

569

# define AFMT_AVI_INFO_Y_YCBCR422 1

570

# define AFMT_AVI_INFO_Y_YCBCR444 2

571

# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)

572

# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)

573

# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)

574

# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)

575

# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)

576

# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)

577

# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)

578

# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)

579

# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)

580

# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)

581

#define AFMT_AVI_INFO1 0x7088

582

# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */

583

# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */

584

# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12)

585

# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14)

586

# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)

587

#define AFMT_AVI_INFO2 0x708c

588

# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)

589

# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)

590

#define AFMT_AVI_INFO3 0x7090

591

# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)

592

# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)

593

#define AFMT_MPEG_INFO0 0x7094

594

# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

595

# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)

596

# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)

597

# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)

598

#define AFMT_MPEG_INFO1 0x7098

599

# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)

600

# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)

601

# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)

602

#define AFMT_GENERIC0_HDR 0x709c

603

#define AFMT_GENERIC0_0 0x70a0

604

#define AFMT_GENERIC0_1 0x70a4

605

#define AFMT_GENERIC0_2 0x70a8

606

#define AFMT_GENERIC0_3 0x70ac

607

#define AFMT_GENERIC0_4 0x70b0

608

#define AFMT_GENERIC0_5 0x70b4

609

#define AFMT_GENERIC0_6 0x70b8

610

#define AFMT_GENERIC1_HDR 0x70bc

611

#define AFMT_GENERIC1_0 0x70c0

612

#define AFMT_GENERIC1_1 0x70c4

613

#define AFMT_GENERIC1_2 0x70c8

614

#define AFMT_GENERIC1_3 0x70cc

615

#define AFMT_GENERIC1_4 0x70d0

616

#define AFMT_GENERIC1_5 0x70d4

617

#define AFMT_GENERIC1_6 0x70d8

618

#define HDMI_ACR_32_0 0x70dc

619

# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)

620

#define HDMI_ACR_32_1 0x70e0

621

# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)

622

#define HDMI_ACR_44_0 0x70e4

623

# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)

624

#define HDMI_ACR_44_1 0x70e8

625

# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)

626

#define HDMI_ACR_48_0 0x70ec

627

# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)

628

#define HDMI_ACR_48_1 0x70f0

629

# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)

630

#define HDMI_ACR_STATUS_0 0x70f4

631

#define HDMI_ACR_STATUS_1 0x70f8

632

#define AFMT_AUDIO_INFO0 0x70fc

633

# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

634

# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)

635

# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11)

636

# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)

637

# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24)

638

#define AFMT_AUDIO_INFO1 0x7100

639

# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)

640

# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)

641

# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)

642

# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)

643

# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16)

644

#define AFMT_60958_0 0x7104

645

# define AFMT_60958_CS_A(x) (((x) & 1) << 0)

646

# define AFMT_60958_CS_B(x) (((x) & 1) << 1)

647

# define AFMT_60958_CS_C(x) (((x) & 1) << 2)

648

# define AFMT_60958_CS_D(x) (((x) & 3) << 3)

649

# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)

650

# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)

651

# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)

652

# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)

653

# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)

654

# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)

655

#define AFMT_60958_1 0x7108

656

# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)

657

# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)

658

# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)

659

# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)

660

# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)

661

#define AFMT_AUDIO_CRC_CONTROL 0x710c

662

# define AFMT_AUDIO_CRC_EN (1 << 0)

663

#define AFMT_RAMP_CONTROL0 0x7110

664

# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)

665

# define AFMT_RAMP_DATA_SIGN (1 << 31)

666

#define AFMT_RAMP_CONTROL1 0x7114

667

# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)

668

# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)

669

#define AFMT_RAMP_CONTROL2 0x7118

670

# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)

671

#define AFMT_RAMP_CONTROL3 0x711c

672

# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)

673

#define AFMT_60958_2 0x7120

674

# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)

675

# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)

676

# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)

677

# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)

678

# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)

679

# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)

680

#define AFMT_STATUS 0x7128

681

# define AFMT_AUDIO_ENABLE (1 << 4)

682

# define AFMT_AUDIO_HBR_ENABLE (1 << 8)

683

# define AFMT_AZ_FORMAT_WTRIG (1 << 28)

684

# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)

685

# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)

686

#define AFMT_AUDIO_PACKET_CONTROL 0x712c

687

# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)

688

# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */

689

# define AFMT_AUDIO_TEST_EN (1 << 12)

690

# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)

691

# define AFMT_60958_CS_UPDATE (1 << 26)

692

# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)

693

# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)

694

# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)

695

# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)

696

#define AFMT_VBI_PACKET_CONTROL 0x7130

697

# define AFMT_GENERIC0_UPDATE (1 << 2)

698

#define AFMT_INFOFRAME_CONTROL0 0x7134

699

# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */

700

# define AFMT_AUDIO_INFO_UPDATE (1 << 7)

701

# define AFMT_MPEG_INFO_UPDATE (1 << 10)

702

#define AFMT_GENERIC0_7 0x7138

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

703

Alex Deucher

1c4c3a9

2012-12-03 11:59:21 -0500

[diff] [blame]

704

/* DCE4/5 ELD audio interface */

705

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */

706

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */

707

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */

708

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */

709

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */

710

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */

711

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */

712

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */

713

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */

714

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */

715

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */

716

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */

717

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */

718

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */

719

# define MAX_CHANNELS(x) (((x) & 0x7) << 0)

720

/* max channels minus one. 7 = 8 channels */

721

# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)

722

# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)

723

# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */

724

/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO

* bit0 = 32 kHz

* bit1 = 44.1 kHz

* bit2 = 48 kHz

* bit3 = 88.2 kHz

* bit4 = 96 kHz

* bit5 = 176.4 kHz

* bit6 = 192 kHz

*/

#define AZ_HOT_PLUG_CONTROL 0x5e78

735

# define AZ_FORCE_CODEC_WAKE (1 << 0)

736

# define PIN0_JACK_DETECTION_ENABLE (1 << 4)

737

# define PIN1_JACK_DETECTION_ENABLE (1 << 5)

738

# define PIN2_JACK_DETECTION_ENABLE (1 << 6)

739

# define PIN3_JACK_DETECTION_ENABLE (1 << 7)

740

# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)

741

# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)

742

# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)

743

# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)

744

# define CODEC_HOT_PLUG_ENABLE (1 << 12)

745

# define PIN0_AUDIO_ENABLED (1 << 24)

746

# define PIN1_AUDIO_ENABLED (1 << 25)

747

# define PIN2_AUDIO_ENABLED (1 << 26)

748

# define PIN3_AUDIO_ENABLED (1 << 27)

749

# define AUDIO_ENABLED (1 << 31)

750

751

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

752

#define GC_USER_SHADER_PIPE_CONFIG 0x8954

753

#define INACTIVE_QD_PIPES(x) ((x) << 8)

754

#define INACTIVE_QD_PIPES_MASK 0x0000FF00

755

#define INACTIVE_SIMDS(x) ((x) << 16)

756

#define INACTIVE_SIMDS_MASK 0x00FF0000

757

758

#define GRBM_CNTL 0x8000

759

#define GRBM_READ_TIMEOUT(x) ((x) << 0)

760

#define GRBM_SOFT_RESET 0x8020

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

761

#define SOFT_RESET_CP (1 << 0)

762

#define SOFT_RESET_CB (1 << 1)

763

#define SOFT_RESET_DB (1 << 3)

764

#define SOFT_RESET_PA (1 << 5)

765

#define SOFT_RESET_SC (1 << 6)

766

#define SOFT_RESET_SPI (1 << 8)

767

#define SOFT_RESET_SH (1 << 9)

768

#define SOFT_RESET_SX (1 << 10)

769

#define SOFT_RESET_TC (1 << 11)

770

#define SOFT_RESET_TA (1 << 12)

771

#define SOFT_RESET_VC (1 << 13)

772

#define SOFT_RESET_VGT (1 << 14)

773

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

774

#define GRBM_STATUS 0x8010

775

#define CMDFIFO_AVAIL_MASK 0x0000000F

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

776

#define SRBM_RQ_PENDING (1 << 5)

777

#define CF_RQ_PENDING (1 << 7)

778

#define PF_RQ_PENDING (1 << 8)

779

#define GRBM_EE_BUSY (1 << 10)

780

#define SX_CLEAN (1 << 11)

781

#define DB_CLEAN (1 << 12)

782

#define CB_CLEAN (1 << 13)

783

#define TA_BUSY (1 << 14)

784

#define VGT_BUSY_NO_DMA (1 << 16)

785

#define VGT_BUSY (1 << 17)

786

#define SX_BUSY (1 << 20)

787

#define SH_BUSY (1 << 21)

788

#define SPI_BUSY (1 << 22)

789

#define SC_BUSY (1 << 24)

790

#define PA_BUSY (1 << 25)

791

#define DB_BUSY (1 << 26)

792

#define CP_COHERENCY_BUSY (1 << 28)

793

#define CP_BUSY (1 << 29)

794

#define CB_BUSY (1 << 30)

795

#define GUI_ACTIVE (1 << 31)

796

#define GRBM_STATUS_SE0 0x8014

797

#define GRBM_STATUS_SE1 0x8018

798

#define SE_SX_CLEAN (1 << 0)

799

#define SE_DB_CLEAN (1 << 1)

800

#define SE_CB_CLEAN (1 << 2)

801

#define SE_TA_BUSY (1 << 25)

802

#define SE_SX_BUSY (1 << 26)

803

#define SE_SPI_BUSY (1 << 27)

804

#define SE_SH_BUSY (1 << 28)

805

#define SE_SC_BUSY (1 << 29)

806

#define SE_DB_BUSY (1 << 30)

807

#define SE_CB_BUSY (1 << 31)

Alex Deucher

e33df25

2010-11-22 17:56:32 -0500

[diff] [blame]

808

/* evergreen */

Alex Deucher

67b3f82

2011-05-25 18:45:37 -0400

[diff] [blame]

809

#define CG_THERMAL_CTRL 0x72c

810

#define TOFFSET_MASK 0x00003FE0

811

#define TOFFSET_SHIFT 5

Alex Deucher

2013-06-26 00:33:35 -0400

[diff] [blame]

812

#define DIG_THERM_DPM(x) ((x) << 14)

813

#define DIG_THERM_DPM_MASK 0x003FC000

814

#define DIG_THERM_DPM_SHIFT 14

815

816

#define CG_THERMAL_INT 0x734

817

#define DIG_THERM_INTH(x) ((x) << 8)

818

#define DIG_THERM_INTH_MASK 0x0000FF00

819

#define DIG_THERM_INTH_SHIFT 8

820

#define DIG_THERM_INTL(x) ((x) << 16)

821

#define DIG_THERM_INTL_MASK 0x00FF0000

822

#define DIG_THERM_INTL_SHIFT 16

823

#define THERM_INT_MASK_HIGH (1 << 24)

824

#define THERM_INT_MASK_LOW (1 << 25)

825

Alex Deucher

d70229f

2013-04-12 16:40:41 -0400

[diff] [blame]

826

#define TN_CG_THERMAL_INT_CTRL 0x738

827

#define TN_DIG_THERM_INTH(x) ((x) << 0)

828

#define TN_DIG_THERM_INTH_MASK 0x000000FF

829

#define TN_DIG_THERM_INTH_SHIFT 0

830

#define TN_DIG_THERM_INTL(x) ((x) << 8)

831

#define TN_DIG_THERM_INTL_MASK 0x0000FF00

832

#define TN_DIG_THERM_INTL_SHIFT 8

833

#define TN_THERM_INT_MASK_HIGH (1 << 24)

834

#define TN_THERM_INT_MASK_LOW (1 << 25)

835

Alex Deucher

21a8122

2010-07-02 12:58:16 -0400

[diff] [blame]

836

#define CG_MULT_THERMAL_STATUS 0x740

837

#define ASIC_T(x) ((x) << 16)

Alex Deucher

67b3f82

2011-05-25 18:45:37 -0400

[diff] [blame]

838

#define ASIC_T_MASK 0x07FF0000

Alex Deucher

21a8122

2010-07-02 12:58:16 -0400

[diff] [blame]

839

#define ASIC_T_SHIFT 16

Alex Deucher

67b3f82

2011-05-25 18:45:37 -0400

[diff] [blame]

840

#define CG_TS0_STATUS 0x760

841

#define TS0_ADC_DOUT_MASK 0x000003FF

842

#define TS0_ADC_DOUT_SHIFT 0

Alex Deucher

2013-06-26 00:33:35 -0400

[diff] [blame]

843

Alex Deucher

e33df25

2010-11-22 17:56:32 -0500

[diff] [blame]

844

/* APU */

845

#define CG_THERMAL_STATUS 0x678

Alex Deucher

21a8122

2010-07-02 12:58:16 -0400

[diff] [blame]

846

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

847

#define HDP_HOST_PATH_CNTL 0x2C00

848

#define HDP_NONSURFACE_BASE 0x2C04

849

#define HDP_NONSURFACE_INFO 0x2C08

850

#define HDP_NONSURFACE_SIZE 0x2C0C

Alex Deucher

6f2f48a

2010-12-15 11:01:56 -0500

[diff] [blame]

851

#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

852

#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

853

#define HDP_TILING_CONFIG 0x2F3C

854

855

#define MC_SHARED_CHMAP 0x2004

856

#define NOOFCHAN_SHIFT 12

857

#define NOOFCHAN_MASK 0x00003000

Alex Deucher

9535ab7

2010-11-22 17:56:18 -0500

[diff] [blame]

858

#define MC_SHARED_CHREMAP 0x2008

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

859

Alex Deucher

62444b7

2012-08-15 17:18:42 -0400

[diff] [blame]

860

#define MC_SHARED_BLACKOUT_CNTL 0x20ac

861

#define BLACKOUT_MODE_MASK 0x00000007

862

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

863

#define MC_ARB_RAMCFG 0x2760

864

#define NOOFBANK_SHIFT 0

865

#define NOOFBANK_MASK 0x00000003

866

#define NOOFRANK_SHIFT 2

867

#define NOOFRANK_MASK 0x00000004

868

#define NOOFROWS_SHIFT 3

869

#define NOOFROWS_MASK 0x00000038

870

#define NOOFCOLS_SHIFT 6

871

#define NOOFCOLS_MASK 0x000000C0

872

#define CHANSIZE_SHIFT 8

873

#define CHANSIZE_MASK 0x00000100

874

#define BURSTLENGTH_SHIFT 9

875

#define BURSTLENGTH_MASK 0x00000200

876

#define CHANSIZE_OVERRIDE (1 << 11)

Alex Deucher

d9282fc

2011-05-11 03:15:24 -0400

[diff] [blame]

877

#define FUS_MC_ARB_RAMCFG 0x2768

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

878

#define MC_VM_AGP_TOP 0x2028

879

#define MC_VM_AGP_BOT 0x202C

880

#define MC_VM_AGP_BASE 0x2030

881

#define MC_VM_FB_LOCATION 0x2024

Alex Deucher

b4183e3

2010-12-15 11:04:10 -0500

[diff] [blame]

882

#define MC_FUS_VM_FB_OFFSET 0x2898

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

883

#define MC_VM_MB_L1_TLB0_CNTL 0x2234

884

#define MC_VM_MB_L1_TLB1_CNTL 0x2238

885

#define MC_VM_MB_L1_TLB2_CNTL 0x223C

886

#define MC_VM_MB_L1_TLB3_CNTL 0x2240

887

#define ENABLE_L1_TLB (1 << 0)

888

#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

889

#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)

890

#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)

891

#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)

892

#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)

893

#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)

894

#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)

895

#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)

896

#define MC_VM_MD_L1_TLB0_CNTL 0x2654

897

#define MC_VM_MD_L1_TLB1_CNTL 0x2658

898

#define MC_VM_MD_L1_TLB2_CNTL 0x265C

Alex Deucher

0b8c30b

2012-05-31 18:54:43 -0400

[diff] [blame]

899

#define MC_VM_MD_L1_TLB3_CNTL 0x2698

Alex Deucher

8aeb96f

2011-05-03 19:28:02 -0400

[diff] [blame]

900

901

#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C

902

#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660

903

#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664

904

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

905

#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C

906

#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038

907

#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034

908

909

#define PA_CL_ENHANCE 0x8A14

910

#define CLIP_VTX_REORDER_ENA (1 << 0)

911

#define NUM_CLIP_SEQ(x) ((x) << 1)

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

912

#define PA_SC_ENHANCE 0x8BF0

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

913

#define PA_SC_AA_CONFIG 0x28C04

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

914

#define MSAA_NUM_SAMPLES_SHIFT 0

915

#define MSAA_NUM_SAMPLES_MASK 0x3

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

916

#define PA_SC_CLIPRECT_RULE 0x2820C

917

#define PA_SC_EDGERULE 0x28230

918

#define PA_SC_FIFO_SIZE 0x8BCC

919

#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)

920

#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

921

#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

922

#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

923

#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

924

#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

925

#define PA_SC_LINE_STIPPLE 0x28A0C

Alex Deucher

1292059

2011-02-02 12:37:40 -0500

[diff] [blame]

926

#define PA_SU_LINE_STIPPLE_VALUE 0x8A60

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

927

#define PA_SC_LINE_STIPPLE_STATE 0x8B10

928

929

#define SCRATCH_REG0 0x8500

930

#define SCRATCH_REG1 0x8504

931

#define SCRATCH_REG2 0x8508

932

#define SCRATCH_REG3 0x850C

933

#define SCRATCH_REG4 0x8510

934

#define SCRATCH_REG5 0x8514

935

#define SCRATCH_REG6 0x8518

936

#define SCRATCH_REG7 0x851C

937

#define SCRATCH_UMSK 0x8540

938

#define SCRATCH_ADDR 0x8544

939

Alex Deucher

b866d13

2012-06-14 22:06:36 +0200

[diff] [blame]

940

#define SMX_SAR_CTL0 0xA008

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

941

#define SMX_DC_CTL0 0xA020

942

#define USE_HASH_FUNCTION (1 << 0)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

943

#define NUMBER_OF_SETS(x) ((x) << 1)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

944

#define FLUSH_ALL_ON_EVENT (1 << 10)

945

#define STALL_ON_EVENT (1 << 11)

946

#define SMX_EVENT_CTL 0xA02C

947

#define ES_FLUSH_CTL(x) ((x) << 0)

948

#define GS_FLUSH_CTL(x) ((x) << 3)

949

#define ACK_FLUSH_CTL(x) ((x) << 6)

950

#define SYNC_FLUSH_CTL (1 << 8)

951

952

#define SPI_CONFIG_CNTL 0x9100

953

#define GPR_WRITE_PRIORITY(x) ((x) << 0)

954

#define SPI_CONFIG_CNTL_1 0x913C

955

#define VTX_DONE_DELAY(x) ((x) << 0)

956

#define INTERP_ONE_PRIM_PER_ROW (1 << 4)

957

#define SPI_INPUT_Z 0x286D8

958

#define SPI_PS_IN_CONTROL_0 0x286CC

959

#define NUM_INTERP(x) ((x)<<0)

960

#define POSITION_ENA (1<<8)

961

#define POSITION_CENTROID (1<<9)

962

#define POSITION_ADDR(x) ((x)<<10)

963

#define PARAM_GEN(x) ((x)<<15)

964

#define PARAM_GEN_ADDR(x) ((x)<<19)

965

#define BARYC_SAMPLE_CNTL(x) ((x)<<26)

966

#define PERSP_GRADIENT_ENA (1<<28)

967

#define LINEAR_GRADIENT_ENA (1<<29)

968

#define POSITION_SAMPLE (1<<30)

969

#define BARYC_AT_SAMPLE_ENA (1<<31)

970

971

#define SQ_CONFIG 0x8C00

972

#define VC_ENABLE (1 << 0)

973

#define EXPORT_SRC_C (1 << 1)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

974

#define CS_PRIO(x) ((x) << 18)

975

#define LS_PRIO(x) ((x) << 20)

976

#define HS_PRIO(x) ((x) << 22)

977

#define PS_PRIO(x) ((x) << 24)

978

#define VS_PRIO(x) ((x) << 26)

979

#define GS_PRIO(x) ((x) << 28)

980

#define ES_PRIO(x) ((x) << 30)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

981

#define SQ_GPR_RESOURCE_MGMT_1 0x8C04

982

#define NUM_PS_GPRS(x) ((x) << 0)

983

#define NUM_VS_GPRS(x) ((x) << 16)

984

#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)

985

#define SQ_GPR_RESOURCE_MGMT_2 0x8C08

986

#define NUM_GS_GPRS(x) ((x) << 0)

987

#define NUM_ES_GPRS(x) ((x) << 16)

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

988

#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C

989

#define NUM_HS_GPRS(x) ((x) << 0)

990

#define NUM_LS_GPRS(x) ((x) << 16)

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

991

#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10

992

#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

993

#define SQ_THREAD_RESOURCE_MGMT 0x8C18

994

#define NUM_PS_THREADS(x) ((x) << 0)

995

#define NUM_VS_THREADS(x) ((x) << 8)

996

#define NUM_GS_THREADS(x) ((x) << 16)

997

#define NUM_ES_THREADS(x) ((x) << 24)

998

#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C

999

#define NUM_HS_THREADS(x) ((x) << 0)

1000

#define NUM_LS_THREADS(x) ((x) << 8)

1001

#define SQ_STACK_RESOURCE_MGMT_1 0x8C20

1002

#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)

1003

#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)

1004

#define SQ_STACK_RESOURCE_MGMT_2 0x8C24

1005

#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)

1006

#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)

1007

#define SQ_STACK_RESOURCE_MGMT_3 0x8C28

1008

#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)

1009

#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)

1010

#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

1011

#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94

1012

#define SQ_STATIC_THREAD_MGMT_1 0x8E20

1013

#define SQ_STATIC_THREAD_MGMT_2 0x8E24

1014

#define SQ_STATIC_THREAD_MGMT_3 0x8E28

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

1015

#define SQ_LDS_RESOURCE_MGMT 0x8E2C

1016

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

1017

#define SQ_MS_FIFO_SIZES 0x8CF0

1018

#define CACHE_FIFO_SIZE(x) ((x) << 0)

1019

#define FETCH_FIFO_HIWATER(x) ((x) << 8)

1020

#define DONE_FIFO_HIWATER(x) ((x) << 16)

1021

#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)

1022

1023

#define SX_DEBUG_1 0x9058

1024

#define ENABLE_NEW_SMX_ADDRESS (1 << 16)

1025

#define SX_EXPORT_BUFFER_SIZES 0x900C

1026

#define COLOR_BUFFER_SIZE(x) ((x) << 0)

1027

#define POSITION_BUFFER_SIZE(x) ((x) << 8)

1028

#define SMX_BUFFER_SIZE(x) ((x) << 16)

Alex Deucher

033b565

2011-06-08 15:26:45 -0400

[diff] [blame]

1029

#define SX_MEMORY_EXPORT_BASE 0x9010

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

1030

#define SX_MISC 0x28350

1031

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

1032

#define CB_PERF_CTR0_SEL_0 0x9A20

1033

#define CB_PERF_CTR0_SEL_1 0x9A24

1034

#define CB_PERF_CTR1_SEL_0 0x9A28

1035

#define CB_PERF_CTR1_SEL_1 0x9A2C

1036

#define CB_PERF_CTR2_SEL_0 0x9A30

1037

#define CB_PERF_CTR2_SEL_1 0x9A34

1038

#define CB_PERF_CTR3_SEL_0 0x9A38

1039

#define CB_PERF_CTR3_SEL_1 0x9A3C

1040

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

1041

#define TA_CNTL_AUX 0x9508

1042

#define DISABLE_CUBE_WRAP (1 << 0)

1043

#define DISABLE_CUBE_ANISO (1 << 1)

1044

#define SYNC_GRADIENT (1 << 24)

1045

#define SYNC_WALKER (1 << 25)

1046

#define SYNC_ALIGNER (1 << 26)

1047

Alex Deucher

9535ab7

2010-11-22 17:56:18 -0500

[diff] [blame]

1048

#define TCP_CHAN_STEER_LO 0x960c

1049

#define TCP_CHAN_STEER_HI 0x9610

1050

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

1051

#define VGT_CACHE_INVALIDATION 0x88C4

Alex Deucher

2010-03-24 13:33:47 -0400

[diff] [blame]

1052

#define CACHE_INVALIDATION(x) ((x) << 0)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

#define VC_ONLY 0

#define TC_ONLY 1

#define VC_AND_TC 2

#define AUTO_INVLD_EN(x) ((x) << 6)

#define NO_AUTO 0

#define ES_AUTO 1

#define GS_AUTO 2

#define ES_AND_GS_AUTO 3

1061

#define VGT_GS_VERTEX_REUSE 0x88D4

1062

#define VGT_NUM_INSTANCES 0x8974

1063

#define VGT_OUT_DEALLOC_CNTL 0x28C5C

1064

#define DEALLOC_DIST_MASK 0x0000007F

1065

#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58

1066

#define VTX_REUSE_DEPTH_MASK 0x000000FF

1067

1068

#define VM_CONTEXT0_CNTL 0x1410

1069

#define ENABLE_CONTEXT (1 << 0)

1070

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

1071

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

1072

#define VM_CONTEXT1_CNTL 0x1414

Christian König

ae133a1

2012-09-18 15:30:44 -0400

[diff] [blame]

1073

#define VM_CONTEXT1_CNTL2 0x1434

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

1074

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C

1075

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C

1076

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C

1077

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518

1078

#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470

1079

#define REQUEST_TYPE(x) (((x) & 0xf) << 0)

1080

#define RESPONSE_TYPE_MASK 0x000000F0

1081

#define RESPONSE_TYPE_SHIFT 4

1082

#define VM_L2_CNTL 0x1400

1083

#define ENABLE_L2_CACHE (1 << 0)

1084

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

1085

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

1086

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)

1087

#define VM_L2_CNTL2 0x1404

1088

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

1089

#define INVALIDATE_L2_CACHE (1 << 1)

1090

#define VM_L2_CNTL3 0x1408

1091

#define BANK_SELECT(x) ((x) << 0)

1092

#define CACHE_UPDATE_MODE(x) ((x) << 6)

1093

#define VM_L2_STATUS 0x140C

1094

#define L2_BUSY (1 << 0)

Christian König

ae133a1

2012-09-18 15:30:44 -0400

[diff] [blame]

1095

#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC

1096

#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

1097

1098

#define WAIT_UNTIL 0x8040

1099

1100

#define SRBM_STATUS 0x0E50

Alex Deucher

a65a436

2013-01-18 18:55:54 -0500

[diff] [blame]

1101

#define RLC_RQ_PENDING (1 << 3)

1102

#define GRBM_RQ_PENDING (1 << 5)

1103

#define VMC_BUSY (1 << 8)

1104

#define MCB_BUSY (1 << 9)

1105

#define MCB_NON_DISPLAY_BUSY (1 << 10)

1106

#define MCC_BUSY (1 << 11)

1107

#define MCD_BUSY (1 << 12)

1108

#define SEM_BUSY (1 << 14)

1109

#define RLC_BUSY (1 << 15)

1110

#define IH_BUSY (1 << 17)

1111

#define SRBM_STATUS2 0x0EC4

1112

#define DMA_BUSY (1 << 5)

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

1113

#define SRBM_SOFT_RESET 0x0E60

1114

#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6

1115

#define SOFT_RESET_BIF (1 << 1)

1116

#define SOFT_RESET_CG (1 << 2)

1117

#define SOFT_RESET_DC (1 << 5)

1118

#define SOFT_RESET_GRBM (1 << 8)

1119

#define SOFT_RESET_HDP (1 << 9)

1120

#define SOFT_RESET_IH (1 << 10)

1121

#define SOFT_RESET_MC (1 << 11)

1122

#define SOFT_RESET_RLC (1 << 13)

1123

#define SOFT_RESET_ROM (1 << 14)

1124

#define SOFT_RESET_SEM (1 << 15)

1125

#define SOFT_RESET_VMC (1 << 17)

Jerome Glisse

64c56e8

2013-01-02 17:30:35 -0500

[diff] [blame]

1126

#define SOFT_RESET_DMA (1 << 20)

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

1127

#define SOFT_RESET_TST (1 << 21)

Jerome Glisse

64c56e8

2013-01-02 17:30:35 -0500

[diff] [blame]

1128

#define SOFT_RESET_REGBB (1 << 22)

Alex Deucher

2010-03-24 13:26:36 -0400

[diff] [blame]

1129

#define SOFT_RESET_ORB (1 << 23)

Alex Deucher

2010-03-24 13:20:41 -0400

[diff] [blame]

1130

Alex Deucher

f9d9c36

2010-10-22 02:51:05 -0400

[diff] [blame]

1131

/* display watermarks */

1132

#define DC_LB_MEMORY_SPLIT 0x6b0c

1133

#define PRIORITY_A_CNT 0x6b18

1134

#define PRIORITY_MARK_MASK 0x7fff

1135

#define PRIORITY_OFF (1 << 16)

1136

#define PRIORITY_ALWAYS_ON (1 << 20)

1137

#define PRIORITY_B_CNT 0x6b1c

1138

#define PIPE0_ARBITRATION_CONTROL3 0x0bf0

1139

# define LATENCY_WATERMARK_MASK(x) ((x) << 16)

1140

#define PIPE0_LATENCY_CONTROL 0x0bf4

1141

# define LATENCY_LOW_WATERMARK(x) ((x) << 0)

1142

# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)

1143

Alex Deucher

45f9a39

2010-03-24 13:55:51 -0400

[diff] [blame]

1144

#define IH_RB_CNTL 0x3e00

1145

# define IH_RB_ENABLE (1 << 0)

1146

# define IH_IB_SIZE(x) ((x) << 1) /* log2 */

1147

# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)

1148

# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)

1149

# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */

1150

# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)

1151

# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)

1152

#define IH_RB_BASE 0x3e04

1153

#define IH_RB_RPTR 0x3e08

1154

#define IH_RB_WPTR 0x3e0c

1155

# define RB_OVERFLOW (1 << 0)

1156

# define WPTR_OFFSET_MASK 0x3fffc

1157

#define IH_RB_WPTR_ADDR_HI 0x3e10

1158

#define IH_RB_WPTR_ADDR_LO 0x3e14

1159

#define IH_CNTL 0x3e18

1160

# define ENABLE_INTR (1 << 0)

Alex Deucher

fcb857a

2011-07-06 19:52:27 +0000

[diff] [blame]

1161

# define IH_MC_SWAP(x) ((x) << 1)

Alex Deucher

45f9a39

2010-03-24 13:55:51 -0400

[diff] [blame]

1162

# define IH_MC_SWAP_NONE 0

1163

# define IH_MC_SWAP_16BIT 1

1164

# define IH_MC_SWAP_32BIT 2

1165

# define IH_MC_SWAP_64BIT 3

1166

# define RPTR_REARM (1 << 4)

1167

# define MC_WRREQ_CREDIT(x) ((x) << 15)

1168

# define MC_WR_CLEAN_CNT(x) ((x) << 20)

1169

1170

#define CP_INT_CNTL 0xc124

1171

# define CNTX_BUSY_INT_ENABLE (1 << 19)

1172

# define CNTX_EMPTY_INT_ENABLE (1 << 20)

1173

# define SCRATCH_INT_ENABLE (1 << 25)

1174

# define TIME_STAMP_INT_ENABLE (1 << 26)

1175

# define IB2_INT_ENABLE (1 << 29)

1176

# define IB1_INT_ENABLE (1 << 30)

1177

# define RB_INT_ENABLE (1 << 31)

1178

#define CP_INT_STATUS 0xc128

1179

# define SCRATCH_INT_STAT (1 << 25)

1180

# define TIME_STAMP_INT_STAT (1 << 26)

1181

# define IB2_INT_STAT (1 << 29)

1182

# define IB1_INT_STAT (1 << 30)

1183

# define RB_INT_STAT (1 << 31)

1184

1185

#define GRBM_INT_CNTL 0x8060

1186

# define RDERR_INT_ENABLE (1 << 0)

1187

# define GUI_IDLE_INT_ENABLE (1 << 19)

1188

1189

/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */

1190

#define CRTC_STATUS_FRAME_COUNT 0x6e98

1191

1192

/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */

1193

#define VLINE_STATUS 0x6bb8

1194

# define VLINE_OCCURRED (1 << 0)

1195

# define VLINE_ACK (1 << 4)

1196

# define VLINE_STAT (1 << 12)

1197

# define VLINE_INTERRUPT (1 << 16)

1198

# define VLINE_INTERRUPT_TYPE (1 << 17)

1199

/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */

1200

#define VBLANK_STATUS 0x6bbc

1201

# define VBLANK_OCCURRED (1 << 0)

1202

# define VBLANK_ACK (1 << 4)

1203

# define VBLANK_STAT (1 << 12)

1204

# define VBLANK_INTERRUPT (1 << 16)

1205

# define VBLANK_INTERRUPT_TYPE (1 << 17)

1206

1207

/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */

1208

#define INT_MASK 0x6b40

1209

# define VBLANK_INT_MASK (1 << 0)

1210

# define VLINE_INT_MASK (1 << 4)

1211

1212

#define DISP_INTERRUPT_STATUS 0x60f4

1213

# define LB_D1_VLINE_INTERRUPT (1 << 2)

1214

# define LB_D1_VBLANK_INTERRUPT (1 << 3)

1215

# define DC_HPD1_INTERRUPT (1 << 17)

1216

# define DC_HPD1_RX_INTERRUPT (1 << 18)

1217

# define DACA_AUTODETECT_INTERRUPT (1 << 22)

1218

# define DACB_AUTODETECT_INTERRUPT (1 << 23)

1219

# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)

1220

# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)

1221

#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8

1222

# define LB_D2_VLINE_INTERRUPT (1 << 2)

1223

# define LB_D2_VBLANK_INTERRUPT (1 << 3)

1224

# define DC_HPD2_INTERRUPT (1 << 17)

1225

# define DC_HPD2_RX_INTERRUPT (1 << 18)

1226

# define DISP_TIMER_INTERRUPT (1 << 24)

1227

#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc

1228

# define LB_D3_VLINE_INTERRUPT (1 << 2)

1229

# define LB_D3_VBLANK_INTERRUPT (1 << 3)

1230

# define DC_HPD3_INTERRUPT (1 << 17)

1231

# define DC_HPD3_RX_INTERRUPT (1 << 18)

1232

#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100

1233

# define LB_D4_VLINE_INTERRUPT (1 << 2)

1234

# define LB_D4_VBLANK_INTERRUPT (1 << 3)

1235

# define DC_HPD4_INTERRUPT (1 << 17)

1236

# define DC_HPD4_RX_INTERRUPT (1 << 18)

1237

#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c

1238

# define LB_D5_VLINE_INTERRUPT (1 << 2)

1239

# define LB_D5_VBLANK_INTERRUPT (1 << 3)

1240

# define DC_HPD5_INTERRUPT (1 << 17)

1241

# define DC_HPD5_RX_INTERRUPT (1 << 18)

Alex Deucher

37cba6c

2011-07-06 19:37:47 +0000

[diff] [blame]

1242

#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150

Alex Deucher

45f9a39

2010-03-24 13:55:51 -0400

[diff] [blame]

1243

# define LB_D6_VLINE_INTERRUPT (1 << 2)

1244

# define LB_D6_VBLANK_INTERRUPT (1 << 3)

1245

# define DC_HPD6_INTERRUPT (1 << 17)

1246

# define DC_HPD6_RX_INTERRUPT (1 << 18)

1247

1248

/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */

1249

#define GRPH_INT_STATUS 0x6858

1250

# define GRPH_PFLIP_INT_OCCURRED (1 << 0)

1251

# define GRPH_PFLIP_INT_CLEAR (1 << 8)

1252

/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */

1253

#define GRPH_INT_CONTROL 0x685c

1254

# define GRPH_PFLIP_INT_MASK (1 << 0)

1255

# define GRPH_PFLIP_INT_TYPE (1 << 8)

1256

1257

#define DACA_AUTODETECT_INT_CONTROL 0x66c8

1258

#define DACB_AUTODETECT_INT_CONTROL 0x67c8

1259

1260

#define DC_HPD1_INT_STATUS 0x601c

1261

#define DC_HPD2_INT_STATUS 0x6028

1262

#define DC_HPD3_INT_STATUS 0x6034

1263

#define DC_HPD4_INT_STATUS 0x6040

1264

#define DC_HPD5_INT_STATUS 0x604c

1265

#define DC_HPD6_INT_STATUS 0x6058

1266

# define DC_HPDx_INT_STATUS (1 << 0)

1267

# define DC_HPDx_SENSE (1 << 1)

1268

# define DC_HPDx_RX_INT_STATUS (1 << 8)

1269

1270

#define DC_HPD1_INT_CONTROL 0x6020

1271

#define DC_HPD2_INT_CONTROL 0x602c

1272

#define DC_HPD3_INT_CONTROL 0x6038

1273

#define DC_HPD4_INT_CONTROL 0x6044

1274

#define DC_HPD5_INT_CONTROL 0x6050

1275

#define DC_HPD6_INT_CONTROL 0x605c

1276

# define DC_HPDx_INT_ACK (1 << 0)

1277

# define DC_HPDx_INT_POLARITY (1 << 8)

1278

# define DC_HPDx_INT_EN (1 << 16)

1279

# define DC_HPDx_RX_INT_ACK (1 << 20)

1280

# define DC_HPDx_RX_INT_EN (1 << 24)

1281

1282

#define DC_HPD1_CONTROL 0x6024

1283

#define DC_HPD2_CONTROL 0x6030

1284

#define DC_HPD3_CONTROL 0x603c

1285

#define DC_HPD4_CONTROL 0x6048

1286

#define DC_HPD5_CONTROL 0x6054

1287

#define DC_HPD6_CONTROL 0x6060

1288

# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)

1289

# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)

1290

# define DC_HPDx_EN (1 << 28)

1291

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

1292

/* ASYNC DMA */

1293

#define DMA_RB_RPTR 0xd008

1294

#define DMA_RB_WPTR 0xd00c

1295

1296

#define DMA_CNTL 0xd02c

1297

# define TRAP_ENABLE (1 << 0)

1298

# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)

1299

# define SEM_WAIT_INT_ENABLE (1 << 2)

1300

# define DATA_SWAP_ENABLE (1 << 3)

1301

# define FENCE_SWAP_ENABLE (1 << 4)

1302

# define CTXEMPTY_INT_ENABLE (1 << 28)

1303

#define DMA_TILING_CONFIG 0xD0B8

1304

Alex Deucher

f60cbd1

2012-12-04 15:27:33 -0500

[diff] [blame]

1305

#define CAYMAN_DMA1_CNTL 0xd82c

1306

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

1307

/* async DMA packets */

Jerome Glisse

0fcb615

2013-01-14 11:32:27 -0500

[diff] [blame]

1308

#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \

1309

(((sub_cmd) & 0xFF) << 20) |\

1310

(((n) & 0xFFFFF) << 0))

1311

#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)

1312

#define GET_DMA_COUNT(h) ((h) & 0x000fffff)

1313

#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)

1314

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

1315

/* async DMA Packet types */

Jerome Glisse

0fcb615

2013-01-14 11:32:27 -0500

[diff] [blame]

1316

#define DMA_PACKET_WRITE 0x2

1317

#define DMA_PACKET_COPY 0x3

1318

#define DMA_PACKET_INDIRECT_BUFFER 0x4

1319

#define DMA_PACKET_SEMAPHORE 0x5

1320

#define DMA_PACKET_FENCE 0x6

1321

#define DMA_PACKET_TRAP 0x7

1322

#define DMA_PACKET_SRBM_WRITE 0x9

1323

#define DMA_PACKET_CONSTANT_FILL 0xd

1324

#define DMA_PACKET_NOP 0xf

Alex Deucher

2012-12-04 15:25:59 -0500

[diff] [blame]

1325

Alex Deucher

f52382d

2013-02-15 11:02:50 -0500

[diff] [blame^]

1326

/* PIF PHY0 indirect regs */

1327

#define PB0_PIF_CNTL 0x10

1328

# define LS2_EXIT_TIME(x) ((x) << 17)

1329

# define LS2_EXIT_TIME_MASK (0x7 << 17)

1330

# define LS2_EXIT_TIME_SHIFT 17

1331

#define PB0_PIF_PAIRING 0x11

1332

# define MULTI_PIF (1 << 25)

1333

#define PB0_PIF_PWRDOWN_0 0x12

1334

# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)

1335

# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)

1336

# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7

1337

# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)

1338

# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)

1339

# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10

1340

# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)

1341

# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)

1342

# define PLL_RAMP_UP_TIME_0_SHIFT 24

1343

#define PB0_PIF_PWRDOWN_1 0x13

1344

# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)

1345

# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)

1346

# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7

1347

# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)

1348

# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)

1349

# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10

1350

# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)

1351

# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)

1352

# define PLL_RAMP_UP_TIME_1_SHIFT 24

1353

/* PIF PHY1 indirect regs */

1354

#define PB1_PIF_CNTL 0x10

1355

#define PB1_PIF_PAIRING 0x11

1356

#define PB1_PIF_PWRDOWN_0 0x12

1357

#define PB1_PIF_PWRDOWN_1 0x13

1358

/* PCIE PORT indirect regs */

1359

#define PCIE_LC_CNTL 0xa0

1360

# define LC_L0S_INACTIVITY(x) ((x) << 8)

1361

# define LC_L0S_INACTIVITY_MASK (0xf << 8)

1362

# define LC_L0S_INACTIVITY_SHIFT 8

1363

# define LC_L1_INACTIVITY(x) ((x) << 12)

1364

# define LC_L1_INACTIVITY_MASK (0xf << 12)

1365

# define LC_L1_INACTIVITY_SHIFT 12

1366

# define LC_PMI_TO_L1_DIS (1 << 16)

1367

# define LC_ASPM_TO_L1_DIS (1 << 24)

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

1368

#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */

1369

#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */

1370

# define LC_LINK_WIDTH_SHIFT 0

1371

# define LC_LINK_WIDTH_MASK 0x7

1372

# define LC_LINK_WIDTH_X0 0

1373

# define LC_LINK_WIDTH_X1 1

1374

# define LC_LINK_WIDTH_X2 2

1375

# define LC_LINK_WIDTH_X4 3

1376

# define LC_LINK_WIDTH_X8 4

1377

# define LC_LINK_WIDTH_X16 6

1378

# define LC_LINK_WIDTH_RD_SHIFT 4

1379

# define LC_LINK_WIDTH_RD_MASK 0x70

1380

# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

1381

# define LC_RECONFIG_NOW (1 << 8)

1382

# define LC_RENEGOTIATION_SUPPORT (1 << 9)

1383

# define LC_RENEGOTIATE_EN (1 << 10)

1384

# define LC_SHORT_RECONFIG_EN (1 << 11)

1385

# define LC_UPCONFIGURE_SUPPORT (1 << 12)

1386

# define LC_UPCONFIGURE_DIS (1 << 13)

Alex Deucher

f52382d

2013-02-15 11:02:50 -0500

[diff] [blame^]

1387

# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)

1388

# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)

1389

# define LC_DYN_LANES_PWR_STATE_SHIFT 21

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

1390

#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */

1391

# define LC_GEN2_EN_STRAP (1 << 0)

1392

# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)

1393

# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)

1394

# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)

1395

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)

1396

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3

1397

# define LC_CURRENT_DATA_RATE (1 << 11)

Alex Deucher

2013-06-26 00:33:35 -0400

[diff] [blame]

1398

# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)

1399

# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)

1400

# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

1401

# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)

1402

# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)

1403

# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)

1404

# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)

1405

#define MM_CFGREGS_CNTL 0x544c

1406

# define MM_WR_TO_CFG_EN (1 << 3)

1407

#define LINK_CNTL2 0x88 /* F0 */

1408

# define TARGET_LINK_SPEED_MASK (0xf << 0)

1409

# define SELECTABLE_DEEMPHASIS (1 << 6)

1410

Christian König

f2ba57b

2013-04-08 12:41:29 +0200

[diff] [blame]

/*

* UVD

*/

Christian König

9a21059

2013-04-08 12:41:37 +0200

[diff] [blame]

1415

#define UVD_UDEC_ADDR_CONFIG 0xef4c

1416

#define UVD_UDEC_DB_ADDR_CONFIG 0xef50

1417

#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54

Christian König

f2ba57b

2013-04-08 12:41:29 +0200

[diff] [blame]

1418

#define UVD_RBC_RB_RPTR 0xf690

1419

#define UVD_RBC_RB_WPTR 0xf694

1420

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1421

/*

1422

* PM4

1423

*/

Ilija Hadzic

4e872ae

2013-01-02 18:27:48 -0500

[diff] [blame]

1424

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1425

(((reg) >> 2) & 0xFFFF) | \

1426

((n) & 0x3FFF) << 16)

1427

#define CP_PACKET2 0x80000000

1428

#define PACKET2_PAD_SHIFT 0

1429

#define PACKET2_PAD_MASK (0x3fffffff << 0)

1430

1431

#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

1432

Ilija Hadzic

4e872ae

2013-01-02 18:27:48 -0500

[diff] [blame]

1433

#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1434

(((op) & 0xFF) << 8) | \

1435

((n) & 0x3FFF) << 16)

1436

1437

/* Packet 3 types */

1438

#define PACKET3_NOP 0x10

1439

#define PACKET3_SET_BASE 0x11

1440

#define PACKET3_CLEAR_STATE 0x12

Alex Deucher

32171d2

2011-01-06 19:13:32 -0500

[diff] [blame]

1441

#define PACKET3_INDEX_BUFFER_SIZE 0x13

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1442

#define PACKET3_DISPATCH_DIRECT 0x15

1443

#define PACKET3_DISPATCH_INDIRECT 0x16

1444

#define PACKET3_INDIRECT_BUFFER_END 0x17

Alex Deucher

1292059

2011-02-02 12:37:40 -0500

[diff] [blame]

1445

#define PACKET3_MODE_CONTROL 0x18

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1446

#define PACKET3_SET_PREDICATION 0x20

1447

#define PACKET3_REG_RMW 0x21

1448

#define PACKET3_COND_EXEC 0x22

1449

#define PACKET3_PRED_EXEC 0x23

1450

#define PACKET3_DRAW_INDIRECT 0x24

1451

#define PACKET3_DRAW_INDEX_INDIRECT 0x25

1452

#define PACKET3_INDEX_BASE 0x26

1453

#define PACKET3_DRAW_INDEX_2 0x27

1454

#define PACKET3_CONTEXT_CONTROL 0x28

1455

#define PACKET3_DRAW_INDEX_OFFSET 0x29

1456

#define PACKET3_INDEX_TYPE 0x2A

1457

#define PACKET3_DRAW_INDEX 0x2B

1458

#define PACKET3_DRAW_INDEX_AUTO 0x2D

1459

#define PACKET3_DRAW_INDEX_IMMD 0x2E

1460

#define PACKET3_NUM_INSTANCES 0x2F

1461

#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30

1462

#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34

1463

#define PACKET3_DRAW_INDEX_OFFSET_2 0x35

1464

#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36

1465

#define PACKET3_MEM_SEMAPHORE 0x39

1466

#define PACKET3_MPEG_INDEX 0x3A

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

1467

#define PACKET3_COPY_DW 0x3B

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1468

#define PACKET3_WAIT_REG_MEM 0x3C

1469

#define PACKET3_MEM_WRITE 0x3D

1470

#define PACKET3_INDIRECT_BUFFER 0x32

Alex Deucher

b997a8b

2012-12-03 18:07:25 -0500

[diff] [blame]

1471

#define PACKET3_CP_DMA 0x41

1472

/* 1. header

1473

* 2. SRC_ADDR_LO or DATA [31:0]

1474

* 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |

1475

* SRC_ADDR_HI [7:0]

1476

* 4. DST_ADDR_LO [31:0]

1477

* 5. DST_ADDR_HI [7:0]

1478

* 6. COMMAND [29:22] | BYTE_COUNT [20:0]

1479

*/

1480

# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)

/* 0 - SRC_ADDR

* 1 - GDS

*/

# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)

/* 0 - ME

* 1 - PFP

*/

# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)

/* 0 - SRC_ADDR

* 1 - GDS

* 2 - DATA

*/

# define PACKET3_CP_DMA_CP_SYNC (1 << 31)

1494

/* COMMAND */

1495

# define PACKET3_CP_DMA_DIS_WC (1 << 21)

1496

# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

/* 0 - none

* 1 - 8 in 16

* 2 - 8 in 32

* 3 - 8 in 64

*/

# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)

/* 0 - none

* 1 - 8 in 16

* 2 - 8 in 32

* 3 - 8 in 64

*/

# define PACKET3_CP_DMA_CMD_SAS (1 << 26)

/* 0 - memory

* 1 - register

*/

# define PACKET3_CP_DMA_CMD_DAS (1 << 27)

/* 0 - memory

* 1 - register

*/

# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)

1517

# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1518

#define PACKET3_SURFACE_SYNC 0x43

1519

# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)

1520

# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)

1521

# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)

1522

# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)

1523

# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)

1524

# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)

1525

# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)

1526

# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)

1527

# define PACKET3_DB_DEST_BASE_ENA (1 << 14)

1528

# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)

1529

# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)

1530

# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)

Alex Deucher

32171d2

2011-01-06 19:13:32 -0500

[diff] [blame]

1531

# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1532

# define PACKET3_FULL_CACHE_ENA (1 << 20)

1533

# define PACKET3_TC_ACTION_ENA (1 << 23)

1534

# define PACKET3_VC_ACTION_ENA (1 << 24)

1535

# define PACKET3_CB_ACTION_ENA (1 << 25)

1536

# define PACKET3_DB_ACTION_ENA (1 << 26)

1537

# define PACKET3_SH_ACTION_ENA (1 << 27)

Alex Deucher

32171d2

2011-01-06 19:13:32 -0500

[diff] [blame]

1538

# define PACKET3_SX_ACTION_ENA (1 << 28)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1539

#define PACKET3_ME_INITIALIZE 0x44

1540

#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

1541

#define PACKET3_COND_WRITE 0x45

1542

#define PACKET3_EVENT_WRITE 0x46

1543

#define PACKET3_EVENT_WRITE_EOP 0x47

1544

#define PACKET3_EVENT_WRITE_EOS 0x48

1545

#define PACKET3_PREAMBLE_CNTL 0x4A

Alex Deucher

2281a37

2010-10-21 13:31:38 -0400

[diff] [blame]

1546

# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)

1547

# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1548

#define PACKET3_RB_OFFSET 0x4B

1549

#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C

1550

#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D

1551

#define PACKET3_ALU_PS_CONST_UPDATE 0x4E

1552

#define PACKET3_ALU_VS_CONST_UPDATE 0x4F

1553

#define PACKET3_ONE_REG_WRITE 0x57

1554

#define PACKET3_SET_CONFIG_REG 0x68

1555

#define PACKET3_SET_CONFIG_REG_START 0x00008000

1556

#define PACKET3_SET_CONFIG_REG_END 0x0000ac00

1557

#define PACKET3_SET_CONTEXT_REG 0x69

1558

#define PACKET3_SET_CONTEXT_REG_START 0x00028000

1559

#define PACKET3_SET_CONTEXT_REG_END 0x00029000

1560

#define PACKET3_SET_ALU_CONST 0x6A

1561

/* alu const buffers only; no reg file */

1562

#define PACKET3_SET_BOOL_CONST 0x6B

1563

#define PACKET3_SET_BOOL_CONST_START 0x0003a500

1564

#define PACKET3_SET_BOOL_CONST_END 0x0003a518

1565

#define PACKET3_SET_LOOP_CONST 0x6C

1566

#define PACKET3_SET_LOOP_CONST_START 0x0003a200

1567

#define PACKET3_SET_LOOP_CONST_END 0x0003a500

1568

#define PACKET3_SET_RESOURCE 0x6D

1569

#define PACKET3_SET_RESOURCE_START 0x00030000

1570

#define PACKET3_SET_RESOURCE_END 0x00038000

1571

#define PACKET3_SET_SAMPLER 0x6E

1572

#define PACKET3_SET_SAMPLER_START 0x0003c000

1573

#define PACKET3_SET_SAMPLER_END 0x0003c600

1574

#define PACKET3_SET_CTL_CONST 0x6F

1575

#define PACKET3_SET_CTL_CONST_START 0x0003cff0

1576

#define PACKET3_SET_CTL_CONST_END 0x0003ff0c

1577

#define PACKET3_SET_RESOURCE_OFFSET 0x70

1578

#define PACKET3_SET_ALU_CONST_VS 0x71

1579

#define PACKET3_SET_ALU_CONST_DI 0x72

1580

#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73

1581

#define PACKET3_SET_RESOURCE_INDIRECT 0x74

1582

#define PACKET3_SET_APPEND_CNT 0x75

1583

1584

#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c

1585

#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)

1586

#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)

1587

#define SQ_TEX_VTX_INVALID_TEXTURE 0x0

1588

#define SQ_TEX_VTX_INVALID_BUFFER 0x1

1589

#define SQ_TEX_VTX_VALID_TEXTURE 0x2

1590

#define SQ_TEX_VTX_VALID_BUFFER 0x3

1591

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

1592

#define VGT_VTX_VECT_EJECT_REG 0x88b0

1593

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1594

#define SQ_CONST_MEM_BASE 0x8df8

1595

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1596

#define SQ_ESGS_RING_BASE 0x8c40

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1597

#define SQ_ESGS_RING_SIZE 0x8c44

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1598

#define SQ_GSVS_RING_BASE 0x8c48

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1599

#define SQ_GSVS_RING_SIZE 0x8c4c

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1600

#define SQ_ESTMP_RING_BASE 0x8c50

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1601

#define SQ_ESTMP_RING_SIZE 0x8c54

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1602

#define SQ_GSTMP_RING_BASE 0x8c58

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1603

#define SQ_GSTMP_RING_SIZE 0x8c5c

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1604

#define SQ_VSTMP_RING_BASE 0x8c60

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1605

#define SQ_VSTMP_RING_SIZE 0x8c64

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1606

#define SQ_PSTMP_RING_BASE 0x8c68

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1607

#define SQ_PSTMP_RING_SIZE 0x8c6c

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1608

#define SQ_LSTMP_RING_BASE 0x8e10

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1609

#define SQ_LSTMP_RING_SIZE 0x8e14

Alex Deucher

2011-03-02 20:07:40 -0500

[diff] [blame]

1610

#define SQ_HSTMP_RING_BASE 0x8e18

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1611

#define SQ_HSTMP_RING_SIZE 0x8e1c

1612

#define VGT_TF_RING_SIZE 0x8988

1613

1614

#define SQ_ESGS_RING_ITEMSIZE 0x28900

1615

#define SQ_GSVS_RING_ITEMSIZE 0x28904

1616

#define SQ_ESTMP_RING_ITEMSIZE 0x28908

1617

#define SQ_GSTMP_RING_ITEMSIZE 0x2890c

1618

#define SQ_VSTMP_RING_ITEMSIZE 0x28910

1619

#define SQ_PSTMP_RING_ITEMSIZE 0x28914

1620

#define SQ_LSTMP_RING_ITEMSIZE 0x28830

1621

#define SQ_HSTMP_RING_ITEMSIZE 0x28834

1622

1623

#define SQ_GS_VERT_ITEMSIZE 0x2891c

1624

#define SQ_GS_VERT_ITEMSIZE_1 0x28920

1625

#define SQ_GS_VERT_ITEMSIZE_2 0x28924

1626

#define SQ_GS_VERT_ITEMSIZE_3 0x28928

1627

#define SQ_GSVS_RING_OFFSET_1 0x2892c

1628

#define SQ_GSVS_RING_OFFSET_2 0x28930

1629

#define SQ_GSVS_RING_OFFSET_3 0x28934

1630

Alex Deucher

60a4a3e

2010-06-29 17:03:35 -0400

[diff] [blame]

1631

#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140

1632

#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80

1633

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1634

#define SQ_ALU_CONST_CACHE_PS_0 0x28940

1635

#define SQ_ALU_CONST_CACHE_PS_1 0x28944

1636

#define SQ_ALU_CONST_CACHE_PS_2 0x28948

1637

#define SQ_ALU_CONST_CACHE_PS_3 0x2894c

1638

#define SQ_ALU_CONST_CACHE_PS_4 0x28950

1639

#define SQ_ALU_CONST_CACHE_PS_5 0x28954

1640

#define SQ_ALU_CONST_CACHE_PS_6 0x28958

1641

#define SQ_ALU_CONST_CACHE_PS_7 0x2895c

1642

#define SQ_ALU_CONST_CACHE_PS_8 0x28960

1643

#define SQ_ALU_CONST_CACHE_PS_9 0x28964

1644

#define SQ_ALU_CONST_CACHE_PS_10 0x28968

1645

#define SQ_ALU_CONST_CACHE_PS_11 0x2896c

1646

#define SQ_ALU_CONST_CACHE_PS_12 0x28970

1647

#define SQ_ALU_CONST_CACHE_PS_13 0x28974

1648

#define SQ_ALU_CONST_CACHE_PS_14 0x28978

1649

#define SQ_ALU_CONST_CACHE_PS_15 0x2897c

1650

#define SQ_ALU_CONST_CACHE_VS_0 0x28980

1651

#define SQ_ALU_CONST_CACHE_VS_1 0x28984

1652

#define SQ_ALU_CONST_CACHE_VS_2 0x28988

1653

#define SQ_ALU_CONST_CACHE_VS_3 0x2898c

1654

#define SQ_ALU_CONST_CACHE_VS_4 0x28990

1655

#define SQ_ALU_CONST_CACHE_VS_5 0x28994

1656

#define SQ_ALU_CONST_CACHE_VS_6 0x28998

1657

#define SQ_ALU_CONST_CACHE_VS_7 0x2899c

1658

#define SQ_ALU_CONST_CACHE_VS_8 0x289a0

1659

#define SQ_ALU_CONST_CACHE_VS_9 0x289a4

1660

#define SQ_ALU_CONST_CACHE_VS_10 0x289a8

1661

#define SQ_ALU_CONST_CACHE_VS_11 0x289ac

1662

#define SQ_ALU_CONST_CACHE_VS_12 0x289b0

1663

#define SQ_ALU_CONST_CACHE_VS_13 0x289b4

1664

#define SQ_ALU_CONST_CACHE_VS_14 0x289b8

1665

#define SQ_ALU_CONST_CACHE_VS_15 0x289bc

1666

#define SQ_ALU_CONST_CACHE_GS_0 0x289c0

1667

#define SQ_ALU_CONST_CACHE_GS_1 0x289c4

1668

#define SQ_ALU_CONST_CACHE_GS_2 0x289c8

1669

#define SQ_ALU_CONST_CACHE_GS_3 0x289cc

1670

#define SQ_ALU_CONST_CACHE_GS_4 0x289d0

1671

#define SQ_ALU_CONST_CACHE_GS_5 0x289d4

1672

#define SQ_ALU_CONST_CACHE_GS_6 0x289d8

1673

#define SQ_ALU_CONST_CACHE_GS_7 0x289dc

1674

#define SQ_ALU_CONST_CACHE_GS_8 0x289e0

1675

#define SQ_ALU_CONST_CACHE_GS_9 0x289e4

1676

#define SQ_ALU_CONST_CACHE_GS_10 0x289e8

1677

#define SQ_ALU_CONST_CACHE_GS_11 0x289ec

1678

#define SQ_ALU_CONST_CACHE_GS_12 0x289f0

1679

#define SQ_ALU_CONST_CACHE_GS_13 0x289f4

1680

#define SQ_ALU_CONST_CACHE_GS_14 0x289f8

1681

#define SQ_ALU_CONST_CACHE_GS_15 0x289fc

1682

#define SQ_ALU_CONST_CACHE_HS_0 0x28f00

1683

#define SQ_ALU_CONST_CACHE_HS_1 0x28f04

1684

#define SQ_ALU_CONST_CACHE_HS_2 0x28f08

1685

#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c

1686

#define SQ_ALU_CONST_CACHE_HS_4 0x28f10

1687

#define SQ_ALU_CONST_CACHE_HS_5 0x28f14

1688

#define SQ_ALU_CONST_CACHE_HS_6 0x28f18

1689

#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c

1690

#define SQ_ALU_CONST_CACHE_HS_8 0x28f20

1691

#define SQ_ALU_CONST_CACHE_HS_9 0x28f24

1692

#define SQ_ALU_CONST_CACHE_HS_10 0x28f28

1693

#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c

1694

#define SQ_ALU_CONST_CACHE_HS_12 0x28f30

1695

#define SQ_ALU_CONST_CACHE_HS_13 0x28f34

1696

#define SQ_ALU_CONST_CACHE_HS_14 0x28f38

1697

#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c

1698

#define SQ_ALU_CONST_CACHE_LS_0 0x28f40

1699

#define SQ_ALU_CONST_CACHE_LS_1 0x28f44

1700

#define SQ_ALU_CONST_CACHE_LS_2 0x28f48

1701

#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c

1702

#define SQ_ALU_CONST_CACHE_LS_4 0x28f50

1703

#define SQ_ALU_CONST_CACHE_LS_5 0x28f54

1704

#define SQ_ALU_CONST_CACHE_LS_6 0x28f58

1705

#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c

1706

#define SQ_ALU_CONST_CACHE_LS_8 0x28f60

1707

#define SQ_ALU_CONST_CACHE_LS_9 0x28f64

1708

#define SQ_ALU_CONST_CACHE_LS_10 0x28f68

1709

#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c

1710

#define SQ_ALU_CONST_CACHE_LS_12 0x28f70

1711

#define SQ_ALU_CONST_CACHE_LS_13 0x28f74

1712

#define SQ_ALU_CONST_CACHE_LS_14 0x28f78

1713

#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c

1714

Alex Deucher

d7ccd8f

2010-09-09 11:33:36 -0400

[diff] [blame]

1715

#define PA_SC_SCREEN_SCISSOR_TL 0x28030

1716

#define PA_SC_GENERIC_SCISSOR_TL 0x28240

1717

#define PA_SC_WINDOW_SCISSOR_TL 0x28204

Alex Deucher

d7ccd8f

2010-09-09 11:33:36 -0400

[diff] [blame]

1718

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

1719

#define VGT_PRIMITIVE_TYPE 0x8958

1720

#define VGT_INDEX_TYPE 0x895C

1721

1722

#define VGT_NUM_INDICES 0x8970

1723

1724

#define VGT_COMPUTE_DIM_X 0x8990

1725

#define VGT_COMPUTE_DIM_Y 0x8994

1726

#define VGT_COMPUTE_DIM_Z 0x8998

1727

#define VGT_COMPUTE_START_X 0x899C

1728

#define VGT_COMPUTE_START_Y 0x89A0

1729

#define VGT_COMPUTE_START_Z 0x89A4

1730

#define VGT_COMPUTE_INDEX 0x89A8

1731

#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC

1732

#define VGT_HS_OFFCHIP_PARAM 0x89B0

1733

1734

#define DB_DEBUG 0x9830

1735

#define DB_DEBUG2 0x9834

1736

#define DB_DEBUG3 0x9838

1737

#define DB_DEBUG4 0x983C

1738

#define DB_WATERMARKS 0x9854

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1739

#define DB_DEPTH_CONTROL 0x28800

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1740

#define R_028800_DB_DEPTH_CONTROL 0x028800

1741

#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)

1742

#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)

1743

#define C_028800_STENCIL_ENABLE 0xFFFFFFFE

1744

#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)

1745

#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)

1746

#define C_028800_Z_ENABLE 0xFFFFFFFD

1747

#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)

1748

#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)

1749

#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB

1750

#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)

1751

#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)

1752

#define C_028800_ZFUNC 0xFFFFFF8F

1753

#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)

1754

#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)

1755

#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F

1756

#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)

1757

#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)

1758

#define C_028800_STENCILFUNC 0xFFFFF8FF

1759

#define V_028800_STENCILFUNC_NEVER 0x00000000

1760

#define V_028800_STENCILFUNC_LESS 0x00000001

1761

#define V_028800_STENCILFUNC_EQUAL 0x00000002

1762

#define V_028800_STENCILFUNC_LEQUAL 0x00000003

1763

#define V_028800_STENCILFUNC_GREATER 0x00000004

1764

#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005

1765

#define V_028800_STENCILFUNC_GEQUAL 0x00000006

1766

#define V_028800_STENCILFUNC_ALWAYS 0x00000007

1767

#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)

1768

#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)

1769

#define C_028800_STENCILFAIL 0xFFFFC7FF

1770

#define V_028800_STENCIL_KEEP 0x00000000

1771

#define V_028800_STENCIL_ZERO 0x00000001

1772

#define V_028800_STENCIL_REPLACE 0x00000002

1773

#define V_028800_STENCIL_INCR 0x00000003

1774

#define V_028800_STENCIL_DECR 0x00000004

1775

#define V_028800_STENCIL_INVERT 0x00000005

1776

#define V_028800_STENCIL_INCR_WRAP 0x00000006

1777

#define V_028800_STENCIL_DECR_WRAP 0x00000007

1778

#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)

1779

#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)

1780

#define C_028800_STENCILZPASS 0xFFFE3FFF

1781

#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)

1782

#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)

1783

#define C_028800_STENCILZFAIL 0xFFF1FFFF

1784

#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)

1785

#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)

1786

#define C_028800_STENCILFUNC_BF 0xFF8FFFFF

1787

#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)

1788

#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)

1789

#define C_028800_STENCILFAIL_BF 0xFC7FFFFF

1790

#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)

1791

#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)

1792

#define C_028800_STENCILZPASS_BF 0xE3FFFFFF

1793

#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)

1794

#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)

1795

#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1796

#define DB_DEPTH_VIEW 0x28008

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1797

#define R_028008_DB_DEPTH_VIEW 0x00028008

1798

#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)

1799

#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)

1800

#define C_028008_SLICE_START 0xFFFFF800

1801

#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)

1802

#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

1803

#define C_028008_SLICE_MAX 0xFF001FFF

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1804

#define DB_HTILE_DATA_BASE 0x28014

Jerome Glisse

88f50c8

2012-03-21 19:18:21 -0400

[diff] [blame]

1805

#define DB_HTILE_SURFACE 0x28abc

1806

#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)

1807

#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)

1808

#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE

1809

#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)

1810

#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)

1811

#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD

1812

#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1813

#define DB_Z_INFO 0x28040

1814

# define Z_ARRAY_MODE(x) ((x) << 4)

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

1815

# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)

1816

# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)

1817

# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)

1818

# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1819

# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)

1820

#define R_028040_DB_Z_INFO 0x028040

1821

#define S_028040_FORMAT(x) (((x) & 0x3) << 0)

1822

#define G_028040_FORMAT(x) (((x) >> 0) & 0x3)

1823

#define C_028040_FORMAT 0xFFFFFFFC

1824

#define V_028040_Z_INVALID 0x00000000

1825

#define V_028040_Z_16 0x00000001

1826

#define V_028040_Z_24 0x00000002

1827

#define V_028040_Z_32_FLOAT 0x00000003

1828

#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)

1829

#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)

1830

#define C_028040_ARRAY_MODE 0xFFFFFF0F

1831

#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)

1832

#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)

1833

#define C_028040_READ_SIZE 0xEFFFFFFF

1834

#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)

1835

#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)

1836

#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF

1837

#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)

1838

#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)

1839

#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF

1840

#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)

1841

#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)

1842

#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)

1843

#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)

1844

#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)

1845

#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)

1846

#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)

1847

#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)

1848

#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)

1849

#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1850

#define DB_STENCIL_INFO 0x28044

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1851

#define R_028044_DB_STENCIL_INFO 0x028044

1852

#define S_028044_FORMAT(x) (((x) & 0x1) << 0)

1853

#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)

1854

#define C_028044_FORMAT 0xFFFFFFFE

Marek Olšák

0f457e4

2012-07-29 16:24:57 +0200

[diff] [blame]

1855

#define V_028044_STENCIL_INVALID 0

1856

#define V_028044_STENCIL_8 1

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1857

#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1858

#define DB_Z_READ_BASE 0x28048

1859

#define DB_STENCIL_READ_BASE 0x2804c

1860

#define DB_Z_WRITE_BASE 0x28050

1861

#define DB_STENCIL_WRITE_BASE 0x28054

1862

#define DB_DEPTH_SIZE 0x28058

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1863

#define R_028058_DB_DEPTH_SIZE 0x028058

1864

#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)

1865

#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)

1866

#define C_028058_PITCH_TILE_MAX 0xFFFFF800

1867

#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)

1868

#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)

1869

#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF

1870

#define R_02805C_DB_DEPTH_SLICE 0x02805C

1871

#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)

1872

#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)

1873

#define C_02805C_SLICE_TILE_MAX 0xFFC00000

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1874

1875

#define SQ_PGM_START_PS 0x28840

1876

#define SQ_PGM_START_VS 0x2885c

1877

#define SQ_PGM_START_GS 0x28874

1878

#define SQ_PGM_START_ES 0x2888c

1879

#define SQ_PGM_START_FS 0x288a4

1880

#define SQ_PGM_START_HS 0x288b8

1881

#define SQ_PGM_START_LS 0x288d0

1882

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

1883

#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8

1884

#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8

1885

#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8

1886

#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08

1887

#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0

1888

#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0

1889

#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0

1890

#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

1891

#define VGT_STRMOUT_CONFIG 0x28b94

1892

#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98

1893

1894

#define CB_TARGET_MASK 0x28238

1895

#define CB_SHADER_MASK 0x2823c

1896

1897

#define GDS_ADDR_BASE 0x28720

1898

1899

#define CB_IMMED0_BASE 0x28b9c

1900

#define CB_IMMED1_BASE 0x28ba0

1901

#define CB_IMMED2_BASE 0x28ba4

1902

#define CB_IMMED3_BASE 0x28ba8

1903

#define CB_IMMED4_BASE 0x28bac

1904

#define CB_IMMED5_BASE 0x28bb0

1905

#define CB_IMMED6_BASE 0x28bb4

1906

#define CB_IMMED7_BASE 0x28bb8

1907

#define CB_IMMED8_BASE 0x28bbc

1908

#define CB_IMMED9_BASE 0x28bc0

1909

#define CB_IMMED10_BASE 0x28bc4

1910

#define CB_IMMED11_BASE 0x28bc8

1911

1912

/* all 12 CB blocks have these regs */

1913

#define CB_COLOR0_BASE 0x28c60

1914

#define CB_COLOR0_PITCH 0x28c64

1915

#define CB_COLOR0_SLICE 0x28c68

1916

#define CB_COLOR0_VIEW 0x28c6c

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

1917

#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C

1918

#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)

1919

#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)

1920

#define C_028C6C_SLICE_START 0xFFFFF800

1921

#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)

1922

#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

1923

#define C_028C6C_SLICE_MAX 0xFF001FFF

1924

#define R_028C70_CB_COLOR0_INFO 0x028C70

1925

#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)

1926

#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)

1927

#define C_028C70_ENDIAN 0xFFFFFFFC

1928

#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)

1929

#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)

1930

#define C_028C70_FORMAT 0xFFFFFF03

1931

#define V_028C70_COLOR_INVALID 0x00000000

1932

#define V_028C70_COLOR_8 0x00000001

1933

#define V_028C70_COLOR_4_4 0x00000002

1934

#define V_028C70_COLOR_3_3_2 0x00000003

1935

#define V_028C70_COLOR_16 0x00000005

1936

#define V_028C70_COLOR_16_FLOAT 0x00000006

1937

#define V_028C70_COLOR_8_8 0x00000007

1938

#define V_028C70_COLOR_5_6_5 0x00000008

1939

#define V_028C70_COLOR_6_5_5 0x00000009

1940

#define V_028C70_COLOR_1_5_5_5 0x0000000A

1941

#define V_028C70_COLOR_4_4_4_4 0x0000000B

1942

#define V_028C70_COLOR_5_5_5_1 0x0000000C

1943

#define V_028C70_COLOR_32 0x0000000D

1944

#define V_028C70_COLOR_32_FLOAT 0x0000000E

1945

#define V_028C70_COLOR_16_16 0x0000000F

1946

#define V_028C70_COLOR_16_16_FLOAT 0x00000010

1947

#define V_028C70_COLOR_8_24 0x00000011

1948

#define V_028C70_COLOR_8_24_FLOAT 0x00000012

1949

#define V_028C70_COLOR_24_8 0x00000013

1950

#define V_028C70_COLOR_24_8_FLOAT 0x00000014

1951

#define V_028C70_COLOR_10_11_11 0x00000015

1952

#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016

1953

#define V_028C70_COLOR_11_11_10 0x00000017

1954

#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018

1955

#define V_028C70_COLOR_2_10_10_10 0x00000019

1956

#define V_028C70_COLOR_8_8_8_8 0x0000001A

1957

#define V_028C70_COLOR_10_10_10_2 0x0000001B

1958

#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C

1959

#define V_028C70_COLOR_32_32 0x0000001D

1960

#define V_028C70_COLOR_32_32_FLOAT 0x0000001E

1961

#define V_028C70_COLOR_16_16_16_16 0x0000001F

1962

#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020

1963

#define V_028C70_COLOR_32_32_32_32 0x00000022

1964

#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023

1965

#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030

1966

#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)

1967

#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)

1968

#define C_028C70_ARRAY_MODE 0xFFFFF0FF

1969

#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000

1970

#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001

1971

#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002

1972

#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004

1973

#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)

1974

#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)

1975

#define C_028C70_NUMBER_TYPE 0xFFFF8FFF

1976

#define V_028C70_NUMBER_UNORM 0x00000000

1977

#define V_028C70_NUMBER_SNORM 0x00000001

1978

#define V_028C70_NUMBER_USCALED 0x00000002

1979

#define V_028C70_NUMBER_SSCALED 0x00000003

1980

#define V_028C70_NUMBER_UINT 0x00000004

1981

#define V_028C70_NUMBER_SINT 0x00000005

1982

#define V_028C70_NUMBER_SRGB 0x00000006

1983

#define V_028C70_NUMBER_FLOAT 0x00000007

1984

#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)

1985

#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)

1986

#define C_028C70_COMP_SWAP 0xFFFE7FFF

1987

#define V_028C70_SWAP_STD 0x00000000

1988

#define V_028C70_SWAP_ALT 0x00000001

1989

#define V_028C70_SWAP_STD_REV 0x00000002

1990

#define V_028C70_SWAP_ALT_REV 0x00000003

1991

#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)

1992

#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)

1993

#define C_028C70_FAST_CLEAR 0xFFFDFFFF

1994

#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)

1995

#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)

1996

#define C_028C70_COMPRESSION 0xFFF3FFFF

1997

#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)

1998

#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)

1999

#define C_028C70_BLEND_CLAMP 0xFFF7FFFF

2000

#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)

2001

#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)

2002

#define C_028C70_BLEND_BYPASS 0xFFEFFFFF

2003

#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)

2004

#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)

2005

#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF

2006

#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)

2007

#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)

2008

#define C_028C70_ROUND_MODE 0xFFBFFFFF

2009

#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)

2010

#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)

2011

#define C_028C70_TILE_COMPACT 0xFF7FFFFF

2012

#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)

2013

#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)

2014

#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF

2015

#define V_028C70_EXPORT_4C_32BPC 0x0

2016

#define V_028C70_EXPORT_4C_16BPC 0x1

2017

#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */

2018

#define S_028C70_RAT(x) (((x) & 0x1) << 26)

2019

#define G_028C70_RAT(x) (((x) >> 26) & 0x1)

2020

#define C_028C70_RAT 0xFBFFFFFF

2021

#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)

2022

#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)

2023

#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF

2024

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2025

#define CB_COLOR0_INFO 0x28c70

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

2026

# define CB_FORMAT(x) ((x) << 2)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2027

# define CB_ARRAY_MODE(x) ((x) << 8)

2028

# define ARRAY_LINEAR_GENERAL 0

2029

# define ARRAY_LINEAR_ALIGNED 1

2030

# define ARRAY_1D_TILED_THIN1 2

2031

# define ARRAY_2D_TILED_THIN1 4

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

2032

# define CB_SOURCE_FORMAT(x) ((x) << 24)

2033

# define CB_SF_EXPORT_FULL 0

2034

# define CB_SF_EXPORT_NORM 1

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

2035

#define R_028C74_CB_COLOR0_ATTRIB 0x028C74

2036

#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)

2037

#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)

2038

#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF

2039

#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)

2040

#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)

2041

#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)

2042

#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)

2043

#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)

2044

#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)

2045

#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)

2046

#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)

2047

#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)

2048

#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2049

#define CB_COLOR0_ATTRIB 0x28c74

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

2050

# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)

2051

# define ADDR_SURF_TILE_SPLIT_64B 0

2052

# define ADDR_SURF_TILE_SPLIT_128B 1

2053

# define ADDR_SURF_TILE_SPLIT_256B 2

2054

# define ADDR_SURF_TILE_SPLIT_512B 3

2055

# define ADDR_SURF_TILE_SPLIT_1KB 4

2056

# define ADDR_SURF_TILE_SPLIT_2KB 5

2057

# define ADDR_SURF_TILE_SPLIT_4KB 6

2058

# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)

2059

# define ADDR_SURF_2_BANK 0

2060

# define ADDR_SURF_4_BANK 1

2061

# define ADDR_SURF_8_BANK 2

2062

# define ADDR_SURF_16_BANK 3

2063

# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)

2064

# define ADDR_SURF_BANK_WIDTH_1 0

2065

# define ADDR_SURF_BANK_WIDTH_2 1

2066

# define ADDR_SURF_BANK_WIDTH_4 2

2067

# define ADDR_SURF_BANK_WIDTH_8 3

2068

# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)

2069

# define ADDR_SURF_BANK_HEIGHT_1 0

2070

# define ADDR_SURF_BANK_HEIGHT_2 1

2071

# define ADDR_SURF_BANK_HEIGHT_4 2

2072

# define ADDR_SURF_BANK_HEIGHT_8 3

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

2073

# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2074

#define CB_COLOR0_DIM 0x28c78

2075

/* only CB0-7 blocks have these regs */

2076

#define CB_COLOR0_CMASK 0x28c7c

2077

#define CB_COLOR0_CMASK_SLICE 0x28c80

2078

#define CB_COLOR0_FMASK 0x28c84

2079

#define CB_COLOR0_FMASK_SLICE 0x28c88

2080

#define CB_COLOR0_CLEAR_WORD0 0x28c8c

2081

#define CB_COLOR0_CLEAR_WORD1 0x28c90

2082

#define CB_COLOR0_CLEAR_WORD2 0x28c94

2083

#define CB_COLOR0_CLEAR_WORD3 0x28c98

2084

2085

#define CB_COLOR1_BASE 0x28c9c

2086

#define CB_COLOR2_BASE 0x28cd8

2087

#define CB_COLOR3_BASE 0x28d14

2088

#define CB_COLOR4_BASE 0x28d50

2089

#define CB_COLOR5_BASE 0x28d8c

2090

#define CB_COLOR6_BASE 0x28dc8

2091

#define CB_COLOR7_BASE 0x28e04

2092

#define CB_COLOR8_BASE 0x28e40

2093

#define CB_COLOR9_BASE 0x28e5c

2094

#define CB_COLOR10_BASE 0x28e78

2095

#define CB_COLOR11_BASE 0x28e94

2096

2097

#define CB_COLOR1_PITCH 0x28ca0

2098

#define CB_COLOR2_PITCH 0x28cdc

2099

#define CB_COLOR3_PITCH 0x28d18

2100

#define CB_COLOR4_PITCH 0x28d54

2101

#define CB_COLOR5_PITCH 0x28d90

2102

#define CB_COLOR6_PITCH 0x28dcc

2103

#define CB_COLOR7_PITCH 0x28e08

2104

#define CB_COLOR8_PITCH 0x28e44

2105

#define CB_COLOR9_PITCH 0x28e60

2106

#define CB_COLOR10_PITCH 0x28e7c

2107

#define CB_COLOR11_PITCH 0x28e98

2108

2109

#define CB_COLOR1_SLICE 0x28ca4

2110

#define CB_COLOR2_SLICE 0x28ce0

2111

#define CB_COLOR3_SLICE 0x28d1c

2112

#define CB_COLOR4_SLICE 0x28d58

2113

#define CB_COLOR5_SLICE 0x28d94

2114

#define CB_COLOR6_SLICE 0x28dd0

2115

#define CB_COLOR7_SLICE 0x28e0c

2116

#define CB_COLOR8_SLICE 0x28e48

2117

#define CB_COLOR9_SLICE 0x28e64

2118

#define CB_COLOR10_SLICE 0x28e80

2119

#define CB_COLOR11_SLICE 0x28e9c

2120

2121

#define CB_COLOR1_VIEW 0x28ca8

2122

#define CB_COLOR2_VIEW 0x28ce4

2123

#define CB_COLOR3_VIEW 0x28d20

2124

#define CB_COLOR4_VIEW 0x28d5c

2125

#define CB_COLOR5_VIEW 0x28d98

2126

#define CB_COLOR6_VIEW 0x28dd4

2127

#define CB_COLOR7_VIEW 0x28e10

2128

#define CB_COLOR8_VIEW 0x28e4c

2129

#define CB_COLOR9_VIEW 0x28e68

2130

#define CB_COLOR10_VIEW 0x28e84

2131

#define CB_COLOR11_VIEW 0x28ea0

2132

2133

#define CB_COLOR1_INFO 0x28cac

2134

#define CB_COLOR2_INFO 0x28ce8

2135

#define CB_COLOR3_INFO 0x28d24

2136

#define CB_COLOR4_INFO 0x28d60

2137

#define CB_COLOR5_INFO 0x28d9c

2138

#define CB_COLOR6_INFO 0x28dd8

2139

#define CB_COLOR7_INFO 0x28e14

2140

#define CB_COLOR8_INFO 0x28e50

2141

#define CB_COLOR9_INFO 0x28e6c

2142

#define CB_COLOR10_INFO 0x28e88

2143

#define CB_COLOR11_INFO 0x28ea4

2144

2145

#define CB_COLOR1_ATTRIB 0x28cb0

2146

#define CB_COLOR2_ATTRIB 0x28cec

2147

#define CB_COLOR3_ATTRIB 0x28d28

2148

#define CB_COLOR4_ATTRIB 0x28d64

2149

#define CB_COLOR5_ATTRIB 0x28da0

2150

#define CB_COLOR6_ATTRIB 0x28ddc

2151

#define CB_COLOR7_ATTRIB 0x28e18

2152

#define CB_COLOR8_ATTRIB 0x28e54

2153

#define CB_COLOR9_ATTRIB 0x28e70

2154

#define CB_COLOR10_ATTRIB 0x28e8c

2155

#define CB_COLOR11_ATTRIB 0x28ea8

2156

2157

#define CB_COLOR1_DIM 0x28cb4

2158

#define CB_COLOR2_DIM 0x28cf0

2159

#define CB_COLOR3_DIM 0x28d2c

2160

#define CB_COLOR4_DIM 0x28d68

2161

#define CB_COLOR5_DIM 0x28da4

2162

#define CB_COLOR6_DIM 0x28de0

2163

#define CB_COLOR7_DIM 0x28e1c

2164

#define CB_COLOR8_DIM 0x28e58

2165

#define CB_COLOR9_DIM 0x28e74

2166

#define CB_COLOR10_DIM 0x28e90

2167

#define CB_COLOR11_DIM 0x28eac

2168

2169

#define CB_COLOR1_CMASK 0x28cb8

2170

#define CB_COLOR2_CMASK 0x28cf4

2171

#define CB_COLOR3_CMASK 0x28d30

2172

#define CB_COLOR4_CMASK 0x28d6c

2173

#define CB_COLOR5_CMASK 0x28da8

2174

#define CB_COLOR6_CMASK 0x28de4

2175

#define CB_COLOR7_CMASK 0x28e20

2176

2177

#define CB_COLOR1_CMASK_SLICE 0x28cbc

2178

#define CB_COLOR2_CMASK_SLICE 0x28cf8

2179

#define CB_COLOR3_CMASK_SLICE 0x28d34

2180

#define CB_COLOR4_CMASK_SLICE 0x28d70

2181

#define CB_COLOR5_CMASK_SLICE 0x28dac

2182

#define CB_COLOR6_CMASK_SLICE 0x28de8

2183

#define CB_COLOR7_CMASK_SLICE 0x28e24

2184

2185

#define CB_COLOR1_FMASK 0x28cc0

2186

#define CB_COLOR2_FMASK 0x28cfc

2187

#define CB_COLOR3_FMASK 0x28d38

2188

#define CB_COLOR4_FMASK 0x28d74

2189

#define CB_COLOR5_FMASK 0x28db0

2190

#define CB_COLOR6_FMASK 0x28dec

2191

#define CB_COLOR7_FMASK 0x28e28

2192

2193

#define CB_COLOR1_FMASK_SLICE 0x28cc4

2194

#define CB_COLOR2_FMASK_SLICE 0x28d00

2195

#define CB_COLOR3_FMASK_SLICE 0x28d3c

2196

#define CB_COLOR4_FMASK_SLICE 0x28d78

2197

#define CB_COLOR5_FMASK_SLICE 0x28db4

2198

#define CB_COLOR6_FMASK_SLICE 0x28df0

2199

#define CB_COLOR7_FMASK_SLICE 0x28e2c

2200

2201

#define CB_COLOR1_CLEAR_WORD0 0x28cc8

2202

#define CB_COLOR2_CLEAR_WORD0 0x28d04

2203

#define CB_COLOR3_CLEAR_WORD0 0x28d40

2204

#define CB_COLOR4_CLEAR_WORD0 0x28d7c

2205

#define CB_COLOR5_CLEAR_WORD0 0x28db8

2206

#define CB_COLOR6_CLEAR_WORD0 0x28df4

2207

#define CB_COLOR7_CLEAR_WORD0 0x28e30

2208

2209

#define CB_COLOR1_CLEAR_WORD1 0x28ccc

2210

#define CB_COLOR2_CLEAR_WORD1 0x28d08

2211

#define CB_COLOR3_CLEAR_WORD1 0x28d44

2212

#define CB_COLOR4_CLEAR_WORD1 0x28d80

2213

#define CB_COLOR5_CLEAR_WORD1 0x28dbc

2214

#define CB_COLOR6_CLEAR_WORD1 0x28df8

2215

#define CB_COLOR7_CLEAR_WORD1 0x28e34

2216

2217

#define CB_COLOR1_CLEAR_WORD2 0x28cd0

2218

#define CB_COLOR2_CLEAR_WORD2 0x28d0c

2219

#define CB_COLOR3_CLEAR_WORD2 0x28d48

2220

#define CB_COLOR4_CLEAR_WORD2 0x28d84

2221

#define CB_COLOR5_CLEAR_WORD2 0x28dc0

2222

#define CB_COLOR6_CLEAR_WORD2 0x28dfc

2223

#define CB_COLOR7_CLEAR_WORD2 0x28e38

2224

2225

#define CB_COLOR1_CLEAR_WORD3 0x28cd4

2226

#define CB_COLOR2_CLEAR_WORD3 0x28d10

2227

#define CB_COLOR3_CLEAR_WORD3 0x28d4c

2228

#define CB_COLOR4_CLEAR_WORD3 0x28d88

2229

#define CB_COLOR5_CLEAR_WORD3 0x28dc4

2230

#define CB_COLOR6_CLEAR_WORD3 0x28e00

2231

#define CB_COLOR7_CLEAR_WORD3 0x28e3c

2232

2233

#define SQ_TEX_RESOURCE_WORD0_0 0x30000

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

2234

# define TEX_DIM(x) ((x) << 0)

2235

# define SQ_TEX_DIM_1D 0

2236

# define SQ_TEX_DIM_2D 1

2237

# define SQ_TEX_DIM_3D 2

2238

# define SQ_TEX_DIM_CUBEMAP 3

2239

# define SQ_TEX_DIM_1D_ARRAY 4

2240

# define SQ_TEX_DIM_2D_ARRAY 5

2241

# define SQ_TEX_DIM_2D_MSAA 6

2242

# define SQ_TEX_DIM_2D_ARRAY_MSAA 7

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2243

#define SQ_TEX_RESOURCE_WORD1_0 0x30004

2244

# define TEX_ARRAY_MODE(x) ((x) << 28)

2245

#define SQ_TEX_RESOURCE_WORD2_0 0x30008

2246

#define SQ_TEX_RESOURCE_WORD3_0 0x3000C

2247

#define SQ_TEX_RESOURCE_WORD4_0 0x30010

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

2248

# define TEX_DST_SEL_X(x) ((x) << 16)

2249

# define TEX_DST_SEL_Y(x) ((x) << 19)

2250

# define TEX_DST_SEL_Z(x) ((x) << 22)

2251

# define TEX_DST_SEL_W(x) ((x) << 25)

# define SQ_SEL_X 0

# define SQ_SEL_Y 1

# define SQ_SEL_Z 2

# define SQ_SEL_W 3

# define SQ_SEL_0 4

# define SQ_SEL_1 5

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2258

#define SQ_TEX_RESOURCE_WORD5_0 0x30014

2259

#define SQ_TEX_RESOURCE_WORD6_0 0x30018

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

2260

# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2261

#define SQ_TEX_RESOURCE_WORD7_0 0x3001c

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

2262

# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)

Alex Deucher

2011-11-28 14:49:28 -0500

[diff] [blame]

2263

# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)

2264

# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)

2265

# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)

Jerome Glisse

2011-12-16 17:03:42 -0500

[diff] [blame]

2266

#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000

2267

#define S_030000_DIM(x) (((x) & 0x7) << 0)

2268

#define G_030000_DIM(x) (((x) >> 0) & 0x7)

2269

#define C_030000_DIM 0xFFFFFFF8

2270

#define V_030000_SQ_TEX_DIM_1D 0x00000000

2271

#define V_030000_SQ_TEX_DIM_2D 0x00000001

2272

#define V_030000_SQ_TEX_DIM_3D 0x00000002

2273

#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003

2274

#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004

2275

#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005

2276

#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006

2277

#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007

2278

#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)

2279

#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)

2280

#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF

2281

#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)

2282

#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)

2283

#define C_030000_PITCH 0xFFFC003F

2284

#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)

2285

#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)

2286

#define C_030000_TEX_WIDTH 0x0003FFFF

2287

#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004

2288

#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)

2289

#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)

2290

#define C_030004_TEX_HEIGHT 0xFFFFC000

2291

#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)

2292

#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)

2293

#define C_030004_TEX_DEPTH 0xF8003FFF

2294

#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)

2295

#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)

2296

#define C_030004_ARRAY_MODE 0x0FFFFFFF

2297

#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008

2298

#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)

2299

#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)

2300

#define C_030008_BASE_ADDRESS 0x00000000

2301

#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C

2302

#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)

2303

#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)

2304

#define C_03000C_MIP_ADDRESS 0x00000000

2305

#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010

2306

#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)

2307

#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)

2308

#define C_030010_FORMAT_COMP_X 0xFFFFFFFC

2309

#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000

2310

#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001

2311

#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002

2312

#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)

2313

#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)

2314

#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3

2315

#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)

2316

#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)

2317

#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF

2318

#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)

2319

#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)

2320

#define C_030010_FORMAT_COMP_W 0xFFFFFF3F

2321

#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)

2322

#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)

2323

#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF

2324

#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000

2325

#define V_030010_SQ_NUM_FORMAT_INT 0x00000001

2326

#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002

2327

#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)

2328

#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)

2329

#define C_030010_SRF_MODE_ALL 0xFFFFFBFF

2330

#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000

2331

#define V_030010_SRF_MODE_NO_ZERO 0x00000001

2332

#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)

2333

#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)

2334

#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF

2335

#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)

2336

#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)

2337

#define C_030010_ENDIAN_SWAP 0xFFFFCFFF

2338

#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)

2339

#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)

2340

#define C_030010_DST_SEL_X 0xFFF8FFFF

2341

#define V_030010_SQ_SEL_X 0x00000000

2342

#define V_030010_SQ_SEL_Y 0x00000001

2343

#define V_030010_SQ_SEL_Z 0x00000002

2344

#define V_030010_SQ_SEL_W 0x00000003

2345

#define V_030010_SQ_SEL_0 0x00000004

2346

#define V_030010_SQ_SEL_1 0x00000005

2347

#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)

2348

#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)

2349

#define C_030010_DST_SEL_Y 0xFFC7FFFF

2350

#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)

2351

#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)

2352

#define C_030010_DST_SEL_Z 0xFE3FFFFF

2353

#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)

2354

#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)

2355

#define C_030010_DST_SEL_W 0xF1FFFFFF

2356

#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)

2357

#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)

2358

#define C_030010_BASE_LEVEL 0x0FFFFFFF

2359

#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014

2360

#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)

2361

#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)

2362

#define C_030014_LAST_LEVEL 0xFFFFFFF0

2363

#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)

2364

#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)

2365

#define C_030014_BASE_ARRAY 0xFFFE000F

2366

#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)

2367

#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)

2368

#define C_030014_LAST_ARRAY 0xC001FFFF

2369

#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018

2370

#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)

2371

#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)

2372

#define C_030018_MAX_ANISO 0xFFFFFFF8

2373

#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)

2374

#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)

2375

#define C_030018_PERF_MODULATION 0xFFFFFFC7

2376

#define S_030018_INTERLACED(x) (((x) & 0x1) << 6)

2377

#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)

2378

#define C_030018_INTERLACED 0xFFFFFFBF

2379

#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)

2380

#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)

2381

#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C

2382

#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)

2383

#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)

2384

#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)

2385

#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)

2386

#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)

2387

#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)

2388

#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)

2389

#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)

2390

#define S_03001C_TYPE(x) (((x) & 0x3) << 30)

2391

#define G_03001C_TYPE(x) (((x) >> 30) & 0x3)

2392

#define C_03001C_TYPE 0x3FFFFFFF

2393

#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000

2394

#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001

2395

#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002

2396

#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003

2397

#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)

2398

#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)

2399

#define C_03001C_DATA_FORMAT 0xFFFFFFC0

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2400

Ilija Hadzic

2011-10-12 23:29:36 -0400

[diff] [blame]

2401

#define SQ_VTX_CONSTANT_WORD0_0 0x30000

2402

#define SQ_VTX_CONSTANT_WORD1_0 0x30004

2403

#define SQ_VTX_CONSTANT_WORD2_0 0x30008

2404

# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)

2405

# define SQ_VTXC_STRIDE(x) ((x) << 8)

2406

# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)

2407

# define SQ_ENDIAN_NONE 0

2408

# define SQ_ENDIAN_8IN16 1

2409

# define SQ_ENDIAN_8IN32 2

2410

#define SQ_VTX_CONSTANT_WORD3_0 0x3000C

2411

# define SQ_VTCX_SEL_X(x) ((x) << 3)

2412

# define SQ_VTCX_SEL_Y(x) ((x) << 6)

2413

# define SQ_VTCX_SEL_Z(x) ((x) << 9)

2414

# define SQ_VTCX_SEL_W(x) ((x) << 12)

2415

#define SQ_VTX_CONSTANT_WORD4_0 0x30010

2416

#define SQ_VTX_CONSTANT_WORD5_0 0x30014

2417

#define SQ_VTX_CONSTANT_WORD6_0 0x30018

2418

#define SQ_VTX_CONSTANT_WORD7_0 0x3001c

2419

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

2420

#define TD_PS_BORDER_COLOR_INDEX 0xA400

2421

#define TD_PS_BORDER_COLOR_RED 0xA404

2422

#define TD_PS_BORDER_COLOR_GREEN 0xA408

2423

#define TD_PS_BORDER_COLOR_BLUE 0xA40C

2424

#define TD_PS_BORDER_COLOR_ALPHA 0xA410

2425

#define TD_VS_BORDER_COLOR_INDEX 0xA414

2426

#define TD_VS_BORDER_COLOR_RED 0xA418

2427

#define TD_VS_BORDER_COLOR_GREEN 0xA41C

2428

#define TD_VS_BORDER_COLOR_BLUE 0xA420

2429

#define TD_VS_BORDER_COLOR_ALPHA 0xA424

2430

#define TD_GS_BORDER_COLOR_INDEX 0xA428

2431

#define TD_GS_BORDER_COLOR_RED 0xA42C

2432

#define TD_GS_BORDER_COLOR_GREEN 0xA430

2433

#define TD_GS_BORDER_COLOR_BLUE 0xA434

2434

#define TD_GS_BORDER_COLOR_ALPHA 0xA438

2435

#define TD_HS_BORDER_COLOR_INDEX 0xA43C

2436

#define TD_HS_BORDER_COLOR_RED 0xA440

2437

#define TD_HS_BORDER_COLOR_GREEN 0xA444

2438

#define TD_HS_BORDER_COLOR_BLUE 0xA448

2439

#define TD_HS_BORDER_COLOR_ALPHA 0xA44C

2440

#define TD_LS_BORDER_COLOR_INDEX 0xA450

2441

#define TD_LS_BORDER_COLOR_RED 0xA454

2442

#define TD_LS_BORDER_COLOR_GREEN 0xA458

2443

#define TD_LS_BORDER_COLOR_BLUE 0xA45C

2444

#define TD_LS_BORDER_COLOR_ALPHA 0xA460

2445

#define TD_CS_BORDER_COLOR_INDEX 0xA464

2446

#define TD_CS_BORDER_COLOR_RED 0xA468

2447

#define TD_CS_BORDER_COLOR_GREEN 0xA46C

2448

#define TD_CS_BORDER_COLOR_BLUE 0xA470

2449

#define TD_CS_BORDER_COLOR_ALPHA 0xA474

2450

Alex Deucher

c175ca9

2011-03-02 20:07:37 -0500

[diff] [blame]

2451

/* cayman 3D regs */

Jerome Glisse

2012-01-05 22:11:05 -0500

[diff] [blame]

2452

#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4

2453

#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48

Alex Deucher

c175ca9

2011-03-02 20:07:37 -0500

[diff] [blame]

2454

#define CAYMAN_DB_EQAA 0x28804

2455

#define CAYMAN_DB_DEPTH_INFO 0x2803C

2456

#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0

2457

#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0

2458

#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7

Alex Deucher

033b565

2011-06-08 15:26:45 -0400

[diff] [blame]

2459

#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358

Alex Deucher

c175ca9

2011-03-02 20:07:37 -0500

[diff] [blame]

2460

/* cayman packet3 addition */

2461

#define CAYMAN_PACKET3_DEALLOC_STATE 0x14

Alex Deucher

2010-05-28 19:01:35 -0400

[diff] [blame]

2462

Jerome Glisse

eaaa698

2013-01-02 15:12:15 -0500

[diff] [blame]

2463

/* DMA regs common on r6xx/r7xx/evergreen/ni */

Jerome Glisse

64c56e8

2013-01-02 17:30:35 -0500

[diff] [blame]

2464

#define DMA_RB_CNTL 0xd000

2465

# define DMA_RB_ENABLE (1 << 0)

2466

# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */

2467

# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */

2468

# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)

2469

# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */

2470

# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */

Jerome Glisse

eaaa698

2013-01-02 15:12:15 -0500

[diff] [blame]

2471

#define DMA_STATUS_REG 0xd034

Alex Deucher

0ecebb9

2013-01-03 12:40:13 -0500

[diff] [blame]

2472

# define DMA_IDLE (1 << 0)

Jerome Glisse

eaaa698

2013-01-02 15:12:15 -0500

[diff] [blame]

2473

Alex Deucher