| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* | 
 | 2 |  * linux/kernel/irq/chip.c | 
 | 3 |  * | 
 | 4 |  * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | 
 | 5 |  * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | 
 | 6 |  * | 
 | 7 |  * This file contains the core interrupt handling code, for irq-chip | 
 | 8 |  * based architectures. | 
 | 9 |  * | 
 | 10 |  * Detailed information is available in Documentation/DocBook/genericirq | 
 | 11 |  */ | 
 | 12 |  | 
 | 13 | #include <linux/irq.h> | 
| Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> | 
 | 16 | #include <linux/interrupt.h> | 
 | 17 | #include <linux/kernel_stat.h> | 
 | 18 |  | 
 | 19 | #include "internals.h" | 
 | 20 |  | 
| Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 21 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 22 |  *	irq_set_chip - set the irq chip for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 23 |  *	@irq:	irq number | 
 | 24 |  *	@chip:	pointer to irq chip description structure | 
 | 25 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 26 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 27 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 28 | 	unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 29 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 30 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 31 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 32 | 		return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 33 |  | 
 | 34 | 	if (!chip) | 
 | 35 | 		chip = &no_irq_chip; | 
 | 36 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 37 | 	irq_chip_set_defaults(chip); | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 38 | 	desc->irq_data.chip = chip; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 39 | 	irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 40 | 	return 0; | 
 | 41 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 42 | EXPORT_SYMBOL(irq_set_chip); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 43 |  | 
 | 44 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 45 |  *	irq_set_type - set the irq trigger type for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 46 |  *	@irq:	irq number | 
| David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 47 |  *	@type:	IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 48 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 49 | int irq_set_irq_type(unsigned int irq, unsigned int type) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 50 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 51 | 	unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 52 | 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); | 
 | 53 | 	int ret = 0; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 54 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 55 | 	if (!desc) | 
 | 56 | 		return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 57 |  | 
| David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 58 | 	type &= IRQ_TYPE_SENSE_MASK; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 59 | 	if (type != IRQ_TYPE_NONE) | 
 | 60 | 		ret = __irq_set_trigger(desc, irq, type); | 
 | 61 | 	irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 62 | 	return ret; | 
 | 63 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 64 | EXPORT_SYMBOL(irq_set_irq_type); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 65 |  | 
 | 66 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 67 |  *	irq_set_handler_data - set irq handler data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 68 |  *	@irq:	Interrupt number | 
 | 69 |  *	@data:	Pointer to interrupt specific data | 
 | 70 |  * | 
 | 71 |  *	Set the hardware irq controller data for an irq | 
 | 72 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 73 | int irq_set_handler_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 74 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 75 | 	unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 76 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 77 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 78 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 79 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 80 | 	desc->irq_data.handler_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 81 | 	irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 82 | 	return 0; | 
 | 83 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 84 | EXPORT_SYMBOL(irq_set_handler_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 85 |  | 
 | 86 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 87 |  *	irq_set_msi_desc - set MSI descriptor data for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 88 |  *	@irq:	Interrupt number | 
| Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 89 |  *	@entry:	Pointer to MSI descriptor data | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 90 |  * | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 91 |  *	Set the MSI descriptor entry for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 92 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 93 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 94 | { | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 95 | 	unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 96 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 97 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 98 | 	if (!desc) | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 99 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 100 | 	desc->irq_data.msi_desc = entry; | 
| Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 101 | 	if (entry) | 
 | 102 | 		entry->irq = irq; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 103 | 	irq_put_desc_unlock(desc, flags); | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 104 | 	return 0; | 
 | 105 | } | 
 | 106 |  | 
 | 107 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 108 |  *	irq_set_chip_data - set irq chip data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 109 |  *	@irq:	Interrupt number | 
 | 110 |  *	@data:	Pointer to chip specific data | 
 | 111 |  * | 
 | 112 |  *	Set the hardware irq chip data for an irq | 
 | 113 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 114 | int irq_set_chip_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 115 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 116 | 	unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 117 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 118 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 119 | 	if (!desc) | 
| Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 120 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 121 | 	desc->irq_data.chip_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 122 | 	irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 123 | 	return 0; | 
 | 124 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 125 | EXPORT_SYMBOL(irq_set_chip_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 126 |  | 
| Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 127 | struct irq_data *irq_get_irq_data(unsigned int irq) | 
 | 128 | { | 
 | 129 | 	struct irq_desc *desc = irq_to_desc(irq); | 
 | 130 |  | 
 | 131 | 	return desc ? &desc->irq_data : NULL; | 
 | 132 | } | 
 | 133 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | 
 | 134 |  | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 135 | static void irq_state_clr_disabled(struct irq_desc *desc) | 
 | 136 | { | 
 | 137 | 	desc->istate &= ~IRQS_DISABLED; | 
 | 138 | 	irq_compat_clr_disabled(desc); | 
 | 139 | } | 
 | 140 |  | 
 | 141 | static void irq_state_set_disabled(struct irq_desc *desc) | 
 | 142 | { | 
 | 143 | 	desc->istate |= IRQS_DISABLED; | 
 | 144 | 	irq_compat_set_disabled(desc); | 
 | 145 | } | 
 | 146 |  | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 147 | static void irq_state_clr_masked(struct irq_desc *desc) | 
 | 148 | { | 
 | 149 | 	desc->istate &= ~IRQS_MASKED; | 
 | 150 | 	irq_compat_clr_masked(desc); | 
 | 151 | } | 
 | 152 |  | 
 | 153 | static void irq_state_set_masked(struct irq_desc *desc) | 
 | 154 | { | 
 | 155 | 	desc->istate |= IRQS_MASKED; | 
 | 156 | 	irq_compat_set_masked(desc); | 
 | 157 | } | 
 | 158 |  | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 159 | int irq_startup(struct irq_desc *desc) | 
 | 160 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 161 | 	irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 162 | 	desc->depth = 0; | 
 | 163 |  | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 164 | 	if (desc->irq_data.chip->irq_startup) { | 
 | 165 | 		int ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 166 | 		irq_state_clr_masked(desc); | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 167 | 		return ret; | 
 | 168 | 	} | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 169 |  | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 170 | 	irq_enable(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 171 | 	return 0; | 
 | 172 | } | 
 | 173 |  | 
 | 174 | void irq_shutdown(struct irq_desc *desc) | 
 | 175 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 176 | 	irq_state_set_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 177 | 	desc->depth = 1; | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 178 | 	if (desc->irq_data.chip->irq_shutdown) | 
 | 179 | 		desc->irq_data.chip->irq_shutdown(&desc->irq_data); | 
 | 180 | 	if (desc->irq_data.chip->irq_disable) | 
 | 181 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
 | 182 | 	else | 
 | 183 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 184 | 	irq_state_set_masked(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 185 | } | 
 | 186 |  | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 187 | void irq_enable(struct irq_desc *desc) | 
 | 188 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 189 | 	irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 190 | 	if (desc->irq_data.chip->irq_enable) | 
 | 191 | 		desc->irq_data.chip->irq_enable(&desc->irq_data); | 
 | 192 | 	else | 
 | 193 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 194 | 	irq_state_clr_masked(desc); | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 195 | } | 
 | 196 |  | 
 | 197 | void irq_disable(struct irq_desc *desc) | 
 | 198 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 199 | 	irq_state_set_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 200 | 	if (desc->irq_data.chip->irq_disable) { | 
 | 201 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
| Thomas Gleixner | a61d825 | 2011-02-21 12:54:34 +0100 | [diff] [blame] | 202 | 		irq_state_set_masked(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 203 | 	} | 
| Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 204 | } | 
 | 205 |  | 
| Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 206 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED | 
| Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 207 | /* Temporary migration helpers */ | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 208 | static void compat_irq_mask(struct irq_data *data) | 
 | 209 | { | 
 | 210 | 	data->chip->mask(data->irq); | 
 | 211 | } | 
 | 212 |  | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 213 | static void compat_irq_unmask(struct irq_data *data) | 
 | 214 | { | 
 | 215 | 	data->chip->unmask(data->irq); | 
 | 216 | } | 
 | 217 |  | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 218 | static void compat_irq_ack(struct irq_data *data) | 
 | 219 | { | 
 | 220 | 	data->chip->ack(data->irq); | 
 | 221 | } | 
 | 222 |  | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 223 | static void compat_irq_mask_ack(struct irq_data *data) | 
 | 224 | { | 
 | 225 | 	data->chip->mask_ack(data->irq); | 
 | 226 | } | 
 | 227 |  | 
| Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 228 | static void compat_irq_eoi(struct irq_data *data) | 
 | 229 | { | 
 | 230 | 	data->chip->eoi(data->irq); | 
 | 231 | } | 
 | 232 |  | 
| Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 233 | static void compat_irq_enable(struct irq_data *data) | 
 | 234 | { | 
 | 235 | 	data->chip->enable(data->irq); | 
 | 236 | } | 
 | 237 |  | 
| Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 238 | static void compat_irq_disable(struct irq_data *data) | 
 | 239 | { | 
 | 240 | 	data->chip->disable(data->irq); | 
 | 241 | } | 
 | 242 |  | 
 | 243 | static void compat_irq_shutdown(struct irq_data *data) | 
 | 244 | { | 
 | 245 | 	data->chip->shutdown(data->irq); | 
 | 246 | } | 
 | 247 |  | 
| Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 248 | static unsigned int compat_irq_startup(struct irq_data *data) | 
 | 249 | { | 
 | 250 | 	return data->chip->startup(data->irq); | 
 | 251 | } | 
 | 252 |  | 
| Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 253 | static int compat_irq_set_affinity(struct irq_data *data, | 
 | 254 | 				   const struct cpumask *dest, bool force) | 
 | 255 | { | 
 | 256 | 	return data->chip->set_affinity(data->irq, dest); | 
 | 257 | } | 
 | 258 |  | 
| Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 259 | static int compat_irq_set_type(struct irq_data *data, unsigned int type) | 
 | 260 | { | 
 | 261 | 	return data->chip->set_type(data->irq, type); | 
 | 262 | } | 
 | 263 |  | 
| Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 264 | static int compat_irq_set_wake(struct irq_data *data, unsigned int on) | 
 | 265 | { | 
 | 266 | 	return data->chip->set_wake(data->irq, on); | 
 | 267 | } | 
 | 268 |  | 
| Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 269 | static int compat_irq_retrigger(struct irq_data *data) | 
 | 270 | { | 
 | 271 | 	return data->chip->retrigger(data->irq); | 
 | 272 | } | 
 | 273 |  | 
| Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 274 | static void compat_bus_lock(struct irq_data *data) | 
 | 275 | { | 
 | 276 | 	data->chip->bus_lock(data->irq); | 
 | 277 | } | 
 | 278 |  | 
 | 279 | static void compat_bus_sync_unlock(struct irq_data *data) | 
 | 280 | { | 
 | 281 | 	data->chip->bus_sync_unlock(data->irq); | 
 | 282 | } | 
| Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 283 | #endif | 
| Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 284 |  | 
| Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 285 | /* | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 286 |  * Fixup enable/disable function pointers | 
 | 287 |  */ | 
 | 288 | void irq_chip_set_defaults(struct irq_chip *chip) | 
 | 289 | { | 
| Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 290 | #ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED | 
| Thomas Gleixner | c5f7563 | 2010-09-27 12:44:56 +0000 | [diff] [blame] | 291 | 	if (chip->enable) | 
 | 292 | 		chip->irq_enable = compat_irq_enable; | 
| Thomas Gleixner | bc310dd | 2010-09-27 12:45:02 +0000 | [diff] [blame] | 293 | 	if (chip->disable) | 
 | 294 | 		chip->irq_disable = compat_irq_disable; | 
 | 295 | 	if (chip->shutdown) | 
 | 296 | 		chip->irq_shutdown = compat_irq_shutdown; | 
| Thomas Gleixner | 37e12df | 2010-09-27 12:45:38 +0000 | [diff] [blame] | 297 | 	if (chip->startup) | 
 | 298 | 		chip->irq_startup = compat_irq_startup; | 
| Zhang, Yanmin | b86432b | 2006-11-16 01:19:10 -0800 | [diff] [blame] | 299 | 	if (!chip->end) | 
 | 300 | 		chip->end = dummy_irq_chip.end; | 
| Thomas Gleixner | 3876ec9 | 2010-09-27 12:44:35 +0000 | [diff] [blame] | 301 | 	if (chip->bus_lock) | 
 | 302 | 		chip->irq_bus_lock = compat_bus_lock; | 
 | 303 | 	if (chip->bus_sync_unlock) | 
 | 304 | 		chip->irq_bus_sync_unlock = compat_bus_sync_unlock; | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 305 | 	if (chip->mask) | 
 | 306 | 		chip->irq_mask = compat_irq_mask; | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 307 | 	if (chip->unmask) | 
 | 308 | 		chip->irq_unmask = compat_irq_unmask; | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 309 | 	if (chip->ack) | 
 | 310 | 		chip->irq_ack = compat_irq_ack; | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 311 | 	if (chip->mask_ack) | 
 | 312 | 		chip->irq_mask_ack = compat_irq_mask_ack; | 
| Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 313 | 	if (chip->eoi) | 
 | 314 | 		chip->irq_eoi = compat_irq_eoi; | 
| Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 315 | 	if (chip->set_affinity) | 
 | 316 | 		chip->irq_set_affinity = compat_irq_set_affinity; | 
| Thomas Gleixner | b2ba2c3 | 2010-09-27 12:45:47 +0000 | [diff] [blame] | 317 | 	if (chip->set_type) | 
 | 318 | 		chip->irq_set_type = compat_irq_set_type; | 
| Thomas Gleixner | 2f7e99b | 2010-09-27 12:45:50 +0000 | [diff] [blame] | 319 | 	if (chip->set_wake) | 
 | 320 | 		chip->irq_set_wake = compat_irq_set_wake; | 
| Thomas Gleixner | 21e2b8c | 2010-09-27 12:45:53 +0000 | [diff] [blame] | 321 | 	if (chip->retrigger) | 
 | 322 | 		chip->irq_retrigger = compat_irq_retrigger; | 
| Thomas Gleixner | bd15141 | 2010-10-01 15:17:14 +0200 | [diff] [blame] | 323 | #endif | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 324 | } | 
 | 325 |  | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 326 | static inline void mask_ack_irq(struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 327 | { | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 328 | 	if (desc->irq_data.chip->irq_mask_ack) | 
 | 329 | 		desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 330 | 	else { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 331 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 332 | 		if (desc->irq_data.chip->irq_ack) | 
 | 333 | 			desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 334 | 	} | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 335 | 	irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 336 | } | 
 | 337 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 338 | void mask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 339 | { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 340 | 	if (desc->irq_data.chip->irq_mask) { | 
 | 341 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 342 | 		irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 343 | 	} | 
 | 344 | } | 
 | 345 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 346 | void unmask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 347 | { | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 348 | 	if (desc->irq_data.chip->irq_unmask) { | 
 | 349 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 350 | 		irq_state_clr_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 351 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 352 | } | 
 | 353 |  | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 354 | /* | 
 | 355 |  *	handle_nested_irq - Handle a nested irq from a irq thread | 
 | 356 |  *	@irq:	the interrupt number | 
 | 357 |  * | 
 | 358 |  *	Handle interrupts which are nested into a threaded interrupt | 
 | 359 |  *	handler. The handler function is called inside the calling | 
 | 360 |  *	threads context. | 
 | 361 |  */ | 
 | 362 | void handle_nested_irq(unsigned int irq) | 
 | 363 | { | 
 | 364 | 	struct irq_desc *desc = irq_to_desc(irq); | 
 | 365 | 	struct irqaction *action; | 
 | 366 | 	irqreturn_t action_ret; | 
 | 367 |  | 
 | 368 | 	might_sleep(); | 
 | 369 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 370 | 	raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 371 |  | 
 | 372 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
 | 373 |  | 
 | 374 | 	action = desc->action; | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 375 | 	if (unlikely(!action || (desc->istate & IRQS_DISABLED))) | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 376 | 		goto out_unlock; | 
 | 377 |  | 
| Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 378 | 	irq_compat_set_progress(desc); | 
 | 379 | 	desc->istate |= IRQS_INPROGRESS; | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 380 | 	raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 381 |  | 
 | 382 | 	action_ret = action->thread_fn(action->irq, action->dev_id); | 
 | 383 | 	if (!noirqdebug) | 
 | 384 | 		note_interrupt(irq, desc, action_ret); | 
 | 385 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 386 | 	raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 387 | 	desc->istate &= ~IRQS_INPROGRESS; | 
 | 388 | 	irq_compat_clr_progress(desc); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 389 |  | 
 | 390 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 391 | 	raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 392 | } | 
 | 393 | EXPORT_SYMBOL_GPL(handle_nested_irq); | 
 | 394 |  | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 395 | static bool irq_check_poll(struct irq_desc *desc) | 
 | 396 | { | 
| Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 397 | 	if (!(desc->istate & IRQS_POLL_INPROGRESS)) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 398 | 		return false; | 
 | 399 | 	return irq_wait_for_poll(desc); | 
 | 400 | } | 
 | 401 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 402 | /** | 
 | 403 |  *	handle_simple_irq - Simple and software-decoded IRQs. | 
 | 404 |  *	@irq:	the interrupt number | 
 | 405 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 406 |  * | 
 | 407 |  *	Simple interrupts are either sent from a demultiplexing interrupt | 
 | 408 |  *	handler or come from hardware, where no interrupt hardware control | 
 | 409 |  *	is necessary. | 
 | 410 |  * | 
 | 411 |  *	Note: The caller is expected to handle the ack, clear, mask and | 
 | 412 |  *	unmask issues if necessary. | 
 | 413 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 414 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 415 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 416 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 417 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 418 |  | 
| Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 419 | 	if (unlikely(desc->istate & IRQS_INPROGRESS)) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 420 | 		if (!irq_check_poll(desc)) | 
 | 421 | 			goto out_unlock; | 
 | 422 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 423 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 424 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 425 |  | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 426 | 	if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 427 | 		goto out_unlock; | 
 | 428 |  | 
| Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 429 | 	handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 430 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 431 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 432 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 433 | } | 
 | 434 |  | 
 | 435 | /** | 
 | 436 |  *	handle_level_irq - Level type irq handler | 
 | 437 |  *	@irq:	the interrupt number | 
 | 438 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 439 |  * | 
 | 440 |  *	Level type interrupts are active as long as the hardware line has | 
 | 441 |  *	the active level. This may require to mask the interrupt and unmask | 
 | 442 |  *	it after the associated handler has acknowledged the device, so the | 
 | 443 |  *	interrupt line is back to inactive. | 
 | 444 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 445 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 446 | handle_level_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 447 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 448 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 449 | 	mask_ack_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 450 |  | 
| Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 451 | 	if (unlikely(desc->istate & IRQS_INPROGRESS)) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 452 | 		if (!irq_check_poll(desc)) | 
 | 453 | 			goto out_unlock; | 
 | 454 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 455 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 456 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 457 |  | 
 | 458 | 	/* | 
 | 459 | 	 * If its disabled or no action available | 
 | 460 | 	 * keep it masked and get out of here | 
 | 461 | 	 */ | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 462 | 	if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 463 | 		goto out_unlock; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 464 |  | 
| Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 465 | 	handle_irq_event(desc); | 
| Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 466 |  | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 467 | 	if (!(desc->istate & (IRQS_DISABLED | IRQS_ONESHOT))) | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 468 | 		unmask_irq(desc); | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 469 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 470 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 471 | } | 
| Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 472 | EXPORT_SYMBOL_GPL(handle_level_irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 473 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 474 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI | 
 | 475 | static inline void preflow_handler(struct irq_desc *desc) | 
 | 476 | { | 
 | 477 | 	if (desc->preflow_handler) | 
 | 478 | 		desc->preflow_handler(&desc->irq_data); | 
 | 479 | } | 
 | 480 | #else | 
 | 481 | static inline void preflow_handler(struct irq_desc *desc) { } | 
 | 482 | #endif | 
 | 483 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 484 | /** | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 485 |  *	handle_fasteoi_irq - irq handler for transparent controllers | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 486 |  *	@irq:	the interrupt number | 
 | 487 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 488 |  * | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 489 |  *	Only a single callback will be issued to the chip: an ->eoi() | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 490 |  *	call when the interrupt has been serviced. This enables support | 
 | 491 |  *	for modern forms of interrupt handlers, which handle the flow | 
 | 492 |  *	details in hardware, transparently. | 
 | 493 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 494 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 495 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 496 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 497 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 498 |  | 
| Thomas Gleixner | 009b4c3 | 2011-02-07 21:48:49 +0100 | [diff] [blame] | 499 | 	if (unlikely(desc->istate & IRQS_INPROGRESS)) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 500 | 		if (!irq_check_poll(desc)) | 
 | 501 | 			goto out; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 502 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 503 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 504 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 505 |  | 
 | 506 | 	/* | 
 | 507 | 	 * If its disabled or no action available | 
| Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 508 | 	 * then mask it and get out of here: | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 509 | 	 */ | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 510 | 	if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 511 | 		irq_compat_set_pending(desc); | 
 | 512 | 		desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 513 | 		mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 514 | 		goto out; | 
| Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 515 | 	} | 
| Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 516 |  | 
 | 517 | 	if (desc->istate & IRQS_ONESHOT) | 
 | 518 | 		mask_irq(desc); | 
 | 519 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 520 | 	preflow_handler(desc); | 
| Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 521 | 	handle_irq_event(desc); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 522 |  | 
 | 523 | out_eoi: | 
| Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 524 | 	desc->irq_data.chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 525 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 526 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 527 | 	return; | 
 | 528 | out: | 
 | 529 | 	if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) | 
 | 530 | 		goto out_eoi; | 
 | 531 | 	goto out_unlock; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 532 | } | 
 | 533 |  | 
 | 534 | /** | 
 | 535 |  *	handle_edge_irq - edge type IRQ handler | 
 | 536 |  *	@irq:	the interrupt number | 
 | 537 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 538 |  * | 
 | 539 |  *	Interrupt occures on the falling and/or rising edge of a hardware | 
 | 540 |  *	signal. The occurence is latched into the irq controller hardware | 
 | 541 |  *	and must be acked in order to be reenabled. After the ack another | 
 | 542 |  *	interrupt can happen on the same source even before the first one | 
| Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 543 |  *	is handled by the associated event handler. If this happens it | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 544 |  *	might be necessary to disable (mask) the interrupt depending on the | 
 | 545 |  *	controller hardware. This requires to reenable the interrupt inside | 
 | 546 |  *	of the loop which handles the interrupts which have arrived while | 
 | 547 |  *	the handler was running. If all pending interrupts are handled, the | 
 | 548 |  *	loop is left. | 
 | 549 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 550 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 551 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 552 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 553 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 554 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 555 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 556 | 	/* | 
 | 557 | 	 * If we're currently running this IRQ, or its disabled, | 
 | 558 | 	 * we shouldn't process the IRQ. Mark it pending, handle | 
 | 559 | 	 * the necessary masking and go out | 
 | 560 | 	 */ | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 561 | 	if (unlikely((desc->istate & (IRQS_DISABLED | IRQS_INPROGRESS) || | 
 | 562 | 		      !desc->action))) { | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 563 | 		if (!irq_check_poll(desc)) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 564 | 			irq_compat_set_pending(desc); | 
 | 565 | 			desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 566 | 			mask_ack_irq(desc); | 
 | 567 | 			goto out_unlock; | 
 | 568 | 		} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 569 | 	} | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 570 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 571 |  | 
 | 572 | 	/* Start handling the irq */ | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 573 | 	desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 574 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 575 | 	do { | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 576 | 		if (unlikely(!desc->action)) { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 577 | 			mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 578 | 			goto out_unlock; | 
 | 579 | 		} | 
 | 580 |  | 
 | 581 | 		/* | 
 | 582 | 		 * When another irq arrived while we were handling | 
 | 583 | 		 * one, we could have masked the irq. | 
 | 584 | 		 * Renable it, if it was not disabled in meantime. | 
 | 585 | 		 */ | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 586 | 		if (unlikely(desc->istate & IRQS_PENDING)) { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 587 | 			if (!(desc->istate & IRQS_DISABLED) && | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 588 | 			    (desc->istate & IRQS_MASKED)) | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 589 | 				unmask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 590 | 		} | 
 | 591 |  | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 592 | 		handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 593 |  | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 594 | 	} while ((desc->istate & IRQS_PENDING) && | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 595 | 		 !(desc->istate & IRQS_DISABLED)); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 596 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 597 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 598 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 599 | } | 
 | 600 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 601 | /** | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 602 |  *	handle_percpu_irq - Per CPU local irq handler | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 603 |  *	@irq:	the interrupt number | 
 | 604 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 605 |  * | 
 | 606 |  *	Per CPU interrupts on SMP machines without locking requirements | 
 | 607 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 608 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 609 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 610 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 611 | 	struct irq_chip *chip = irq_desc_get_chip(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 612 |  | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 613 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 614 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 615 | 	if (chip->irq_ack) | 
 | 616 | 		chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 617 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 618 | 	handle_irq_event_percpu(desc, desc->action); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 619 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 620 | 	if (chip->irq_eoi) | 
 | 621 | 		chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 622 | } | 
 | 623 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 624 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 625 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 626 | 		  const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 627 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 628 | 	unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 629 | 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 630 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 631 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 632 | 		return; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 633 |  | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 634 | 	if (!handle) { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 635 | 		handle = handle_bad_irq; | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 636 | 	} else { | 
 | 637 | 		if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 638 | 			goto out; | 
| Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 639 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 640 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 641 | 	/* Uninstall? */ | 
 | 642 | 	if (handle == handle_bad_irq) { | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 643 | 		if (desc->irq_data.chip != &no_irq_chip) | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 644 | 			mask_ack_irq(desc); | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 645 | 		irq_compat_set_disabled(desc); | 
 | 646 | 		desc->istate |= IRQS_DISABLED; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 647 | 		desc->depth = 1; | 
 | 648 | 	} | 
 | 649 | 	desc->handle_irq = handle; | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 650 | 	desc->name = name; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 651 |  | 
 | 652 | 	if (handle != handle_bad_irq && is_chained) { | 
| Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 653 | 		irq_settings_set_noprobe(desc); | 
 | 654 | 		irq_settings_set_norequest(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 655 | 		irq_startup(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 656 | 	} | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 657 | out: | 
 | 658 | 	irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 659 | } | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 660 | EXPORT_SYMBOL_GPL(__irq_set_handler); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 661 |  | 
 | 662 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 663 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 664 | 			      irq_flow_handler_t handle, const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 665 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 666 | 	irq_set_chip(irq, chip); | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 667 | 	__irq_set_handler(irq, handle, 0, name); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 668 | } | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 669 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 670 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 671 | { | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 672 | 	unsigned long flags; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 673 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 674 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 675 | 	if (!desc) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 676 | 		return; | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 677 | 	irq_settings_clr_and_set(desc, clr, set); | 
 | 678 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 679 | 	irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 680 | 		   IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 681 | 	if (irq_settings_has_no_balance_set(desc)) | 
 | 682 | 		irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | 
 | 683 | 	if (irq_settings_is_per_cpu(desc)) | 
 | 684 | 		irqd_set(&desc->irq_data, IRQD_PER_CPU); | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 685 | 	if (irq_settings_can_move_pcntxt(desc)) | 
 | 686 | 		irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 687 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 688 | 	irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); | 
 | 689 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 690 | 	irq_put_desc_unlock(desc, flags); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 691 | } |