Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / f80dff9da07d81da16e3b842118d47b9febf9c01 / . / include / asm-arm / arch-ebsa285 / entry-macro.S
blob: 4203dbf106624d95a8955f953e968822579af99b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +0200[diff] [blame]2 * include/asm-arm/arch-ebsa285/entry-macro.S
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3 *
4 * Low-level IRQ helper macros for footbridge-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
Russell King78ff18a2006-01-03 17:39:34 +0000[diff] [blame]10#include <asm/hardware.h>
11#include <asm/arch/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]12#include <asm/hardware/dec21285.h>
13
14 .macro disable_fiq
15 .endm
16
Dan Williamsf80dff92007-02-16 22:16:32 +0100[diff] [blame^]17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]23 .equ dc21285_high, ARMCSR_BASE & 0xff000000
24 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
25
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mov r4, #dc21285_high
28 .if dc21285_low
29 orr r4, r4, #dc21285_low
30 .endif
31 ldr \irqstat, [r4, #0x180] @ get interrupts
32
33 mov \irqnr, #IRQ_SDRAMPARITY
34 tst \irqstat, #IRQ_MASK_SDRAMPARITY
35 bne 1001f
36
37 tst \irqstat, #IRQ_MASK_UART_RX
38 movne \irqnr, #IRQ_CONRX
39 bne 1001f
40
41 tst \irqstat, #IRQ_MASK_DMA1
42 movne \irqnr, #IRQ_DMA1
43 bne 1001f
44
45 tst \irqstat, #IRQ_MASK_DMA2
46 movne \irqnr, #IRQ_DMA2
47 bne 1001f
48
49 tst \irqstat, #IRQ_MASK_IN0
50 movne \irqnr, #IRQ_IN0
51 bne 1001f
52
53 tst \irqstat, #IRQ_MASK_IN1
54 movne \irqnr, #IRQ_IN1
55 bne 1001f
56
57 tst \irqstat, #IRQ_MASK_IN2
58 movne \irqnr, #IRQ_IN2
59 bne 1001f
60
61 tst \irqstat, #IRQ_MASK_IN3
62 movne \irqnr, #IRQ_IN3
63 bne 1001f
64
65 tst \irqstat, #IRQ_MASK_PCI
66 movne \irqnr, #IRQ_PCI
67 bne 1001f
68
69 tst \irqstat, #IRQ_MASK_DOORBELLHOST
70 movne \irqnr, #IRQ_DOORBELLHOST
71 bne 1001f
72
73 tst \irqstat, #IRQ_MASK_I2OINPOST
74 movne \irqnr, #IRQ_I2OINPOST
75 bne 1001f
76
77 tst \irqstat, #IRQ_MASK_TIMER1
78 movne \irqnr, #IRQ_TIMER1
79 bne 1001f
80
81 tst \irqstat, #IRQ_MASK_TIMER2
82 movne \irqnr, #IRQ_TIMER2
83 bne 1001f
84
85 tst \irqstat, #IRQ_MASK_TIMER3
86 movne \irqnr, #IRQ_TIMER3
87 bne 1001f
88
89 tst \irqstat, #IRQ_MASK_UART_TX
90 movne \irqnr, #IRQ_CONTX
91 bne 1001f
92
93 tst \irqstat, #IRQ_MASK_PCI_ABORT
94 movne \irqnr, #IRQ_PCI_ABORT
95 bne 1001f
96
97 tst \irqstat, #IRQ_MASK_PCI_SERR
98 movne \irqnr, #IRQ_PCI_SERR
99 bne 1001f
100
101 tst \irqstat, #IRQ_MASK_DISCARD_TIMER
102 movne \irqnr, #IRQ_DISCARD_TIMER
103 bne 1001f
104
105 tst \irqstat, #IRQ_MASK_PCI_DPERR
106 movne \irqnr, #IRQ_PCI_DPERR
107 bne 1001f
108
109 tst \irqstat, #IRQ_MASK_PCI_PERR
110 movne \irqnr, #IRQ_PCI_PERR
1111001:
112 .endm
113