)]}'
{
  "log": [
    {
      "commit": "62e37ca78b1a4ca2eb77875bfd7ac63a7e068c67",
      "tree": "19bb12d1f88431eb66b583900ac104cfbc278fcc",
      "parents": [
        "dcd6c92267155e70a94b3927bce681ce74b80d1f"
      ],
      "author": {
        "name": "Stephen Warren",
        "email": "swarren@nvidia.com",
        "time": "Mon Jan 09 11:00:32 2012 -0700"
      },
      "committer": {
        "name": "Mark Salter",
        "email": "msalter@redhat.com",
        "time": "Tue Feb 14 21:14:44 2012 -0500"
      },
      "message": "Kbuild: Use dtc\u0027s -d (dependency) option\n\nThis hooks dtc into Kbuild\u0027s dependency system.\n\nThus, for example, \"make dtbs\" will rebuild tegra-harmony.dtb if only\ntegra20.dtsi has changed yet tegra-harmony.dts has not. The previous\nlack of this feature recently caused me to have very confusing \"git\nbisect\" results.\n\nFor ARM, it\u0027s obvious what to add to $(targets). I\u0027m not familiar enough\nwith other architectures to know what to add there. Powerpc appears to\nalready add various .dtb files into $(targets), but the other archs may\nneed something added to $(targets) to work.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nAcked-by: Mark Salter \u003cmsalter@redhat.com\u003e\n"
    },
    {
      "commit": "041cadca7008f08fb4785f2288c8127c16faa529",
      "tree": "19008ae2e32faf489f85e00838a571a5295c79f4",
      "parents": [
        "c1a144d77a6ca3a14ba3c0fec30bc4fd20b3d817"
      ],
      "author": {
        "name": "Mark Salter",
        "email": "msalter@redhat.com",
        "time": "Tue Oct 04 12:12:20 2011 -0400"
      },
      "committer": {
        "name": "Mark Salter",
        "email": "msalter@redhat.com",
        "time": "Thu Oct 06 19:47:33 2011 -0400"
      },
      "message": "C6X: devicetree support\n\nThis is the basic devicetree support for C6X. Currently, four boards are\nsupported. Each one uses a different SoC part. Two of the four supported\nSoCs are multicore. One with 3 cores and the other with 6 cores. There is\nno coherency between the core-level caches, so SMP is not an option. It is\npossible to run separate kernel instances on the various cores. There is\ncurrently no C6X bootloader support for device trees so we build in the DTB\nfor now.\n\nThere are some interesting twists to the hardware which are of note for device\ntree support. Each core has its own interrupt controller which is controlled\nby special purpose core registers. This core controller provides 12 general\npurpose prioritized interrupt sources. Each core is contained within a\nhardware \"module\" which provides L1 and L2 caches, power control, and another\ninterrupt controller which cascades into the core interrupt controller. These\ncore module functions are controlled by memory mapped registers. The addresses\nfor these registers are the same for each core. That is, when coreN accesses\na module-level MMIO register at a given address, it accesses the register for\ncoreN even though other cores would use the same address to access the register\nin the module containing those cores. Other hardware modules (timers, enet, etc)\nwhich are memory mapped can be accessed by all cores.\n\nThe timers need some further explanation for multicore SoCs. Even though all\ntimer control registers are visible to all cores, interrupt routing or other\nconsiderations may make a given timer more suitable for use by a core than\nsome other timer. Because of this and the desire to have the same image run\non more than one core, the timer nodes have a \"ti,core-mask\" property which\nis used by the driver to scan for a suitable timer to use.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n"
    },
    {
      "commit": "c278400c52c14203894c5dc0d63cf385239d8329",
      "tree": "a3f82945b3ebb49b058e99cefdafca65732b041a",
      "parents": [
        "e66d3c490c7a45daa49c1ae9cc5fe0687d14b823"
      ],
      "author": {
        "name": "Aurelien Jacquiot",
        "email": "a-jacquiot@ti.com",
        "time": "Tue Oct 04 10:54:51 2011 -0400"
      },
      "committer": {
        "name": "Mark Salter",
        "email": "msalter@redhat.com",
        "time": "Thu Oct 06 19:47:25 2011 -0400"
      },
      "message": "C6X: build infrastructure\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n"
    }
  ]
}