)]}'
{
  "log": [
    {
      "commit": "0b928af1f40f152dd6469f32b7792480048e6b44",
      "tree": "e220bc8640bd513703fce55e2ad700e0dbe7e813",
      "parents": [
        "e3978dc7dfcb9e7b022bda775929943b43bdefd8"
      ],
      "author": {
        "name": "Viresh Kumar",
        "email": "viresh.kumar@st.com",
        "time": "Thu Apr 19 22:23:13 2012 +0530"
      },
      "committer": {
        "name": "Arnd Bergmann",
        "email": "arnd@arndb.de",
        "time": "Mon May 14 17:34:05 2012 +0200"
      },
      "message": "SPEAr13xx: Add common clock framework support\n\nThis patch adds SPEAr1310 and SPEAr1340\u0027s clock framework support. It is based\non earlier support for SPEAr3xx family.\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nReviewed-by: Mike Turquette \u003cmturquette@ti.com\u003e\n"
    },
    {
      "commit": "5df33a62c4a028d6fc7f2dcc159827d09b7334b8",
      "tree": "f4da61ce3bf14e9bf4a1dae3188109a6de34f708",
      "parents": [
        "f8abc080d33e69dfa2c3dd0f84c31832e2679091"
      ],
      "author": {
        "name": "Viresh Kumar",
        "email": "viresh.kumar@st.com",
        "time": "Tue Apr 10 09:02:35 2012 +0530"
      },
      "committer": {
        "name": "Arnd Bergmann",
        "email": "arnd@arndb.de",
        "time": "Sat May 12 21:44:12 2012 +0200"
      },
      "message": "SPEAr: Switch to common clock framework\n\nSPEAr SoCs used its own clock framework since now. From now on they will move to\nuse common clock framework.\n\nThis patch updates existing SPEAr machine support to adapt for common clock\nframework.\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nReviewed-by: Mike Turquette \u003cmturquette@linaro.org\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n"
    },
    {
      "commit": "a45896bd3a4b7beb571fa704efa7c2782b791093",
      "tree": "abbcf23625304e123839af8af6e5ba278d20797e",
      "parents": [
        "270b9f421e66ee5d135c99ba1c2b883c7750ab6c"
      ],
      "author": {
        "name": "Viresh Kumar",
        "email": "viresh.kumar@st.com",
        "time": "Wed Apr 11 18:04:23 2012 +0530"
      },
      "committer": {
        "name": "Arnd Bergmann",
        "email": "arnd@arndb.de",
        "time": "Sat May 12 21:19:27 2012 +0200"
      },
      "message": "SPEAr: clk: Add General Purpose Timer Synthesizer clock\n\nAll SPEAr SoC\u0027s contain GPT Synthesizers. Their Fout is derived from\nfollowing equations:\n\nFout\u003d Fin/((2 ^ (N+1)) * (M+1))\n\nThis patch adds in support for this type of clock.\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nReviewed-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n"
    },
    {
      "commit": "270b9f421e66ee5d135c99ba1c2b883c7750ab6c",
      "tree": "8cc17279410af8a36edd9c866ac2c7b98bb93ac2",
      "parents": [
        "5335a639ecc5646cbe8e99086fb7e743b801ac58"
      ],
      "author": {
        "name": "Viresh Kumar",
        "email": "viresh.kumar@st.com",
        "time": "Wed Apr 11 18:04:23 2012 +0530"
      },
      "committer": {
        "name": "Arnd Bergmann",
        "email": "arnd@arndb.de",
        "time": "Sat May 12 21:19:27 2012 +0200"
      },
      "message": "SPEAr: clk: Add Fractional Synthesizer clock\n\nAll SPEAr SoC\u0027s contain Fractional Synthesizers. Their Fout is derived from\nfollowing equations:\n\nFout \u003d Fin / (2 * div) (division factor)\ndiv is 17 bits:-\n     0-13 (fractional part)\n     14-16 (integer part)\n     div is (16-14 bits).(13-0 bits) (in binary)\n\n     Fout \u003d Fin/(2 * div)\n     Fout \u003d ((Fin / 10000)/(2 * div)) * 10000\n     Fout \u003d (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000\n     Fout \u003d (((Fin / 10000) \u003c\u003c 14)/(2 * (div \u003c\u003c 14))) * 10000\n\ndiv \u003c\u003c 14 is simply 17 bit value written at register.\n\nThis patch adds in support for this type of clock.\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nReviewed-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n"
    },
    {
      "commit": "5335a639ecc5646cbe8e99086fb7e743b801ac58",
      "tree": "812d38780a2eecf385e5f42a4ee3808aa3a85da3",
      "parents": [
        "55b8fd4f428501b0f35d62b8313311fd9863c188"
      ],
      "author": {
        "name": "Viresh Kumar",
        "email": "viresh.kumar@st.com",
        "time": "Wed Apr 11 18:04:23 2012 +0530"
      },
      "committer": {
        "name": "Arnd Bergmann",
        "email": "arnd@arndb.de",
        "time": "Sat May 12 21:19:26 2012 +0200"
      },
      "message": "SPEAr: clk: Add Auxiliary Synthesizer clock\n\nAll SPEAr SoC\u0027s contain Auxiliary Synthesizers. Their Fout is derived based on\nvalues of eq, x and y.\n\nFout from synthesizer can be given from two equations:\nFout1 \u003d (Fin * X/Y)/2\t\tEQ1\nFout2 \u003d Fin * X/Y\t\tEQ2\n\nThis patch adds in support for this type of clock.\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nReviewed-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n"
    },
    {
      "commit": "55b8fd4f428501b0f35d62b8313311fd9863c188",
      "tree": "2c61fe9c307baa73048345adbb11e20e5eeb586e",
      "parents": [
        "e12ff34402bd3a6cbeab0423012066874bb10f4b"
      ],
      "author": {
        "name": "Viresh Kumar",
        "email": "viresh.kumar@st.com",
        "time": "Tue Apr 10 09:02:35 2012 +0530"
      },
      "committer": {
        "name": "Arnd Bergmann",
        "email": "arnd@arndb.de",
        "time": "Sat May 12 21:19:23 2012 +0200"
      },
      "message": "SPEAr: clk: Add VCO-PLL Synthesizer clock\n\nAll SPEAr SoC\u0027s contain PLLs. Their Fout is derived based on following equations\n\n- In normal mode\n  vco \u003d (2 * M[15:8] * Fin)/N\n\n- In Dithered mode\n  vco \u003d (2 * M[15:0] * Fin)/(256 * N)\n\npll_rate \u003d vco/2^p\n\nvco and pll are very closely bound to each other,\n\"vco needs to program: mode, m \u0026 n\" and \"pll needs to program p\",\nboth share common enable/disable logic and registers.\n\nThis patch adds in support for this type of clock.\n\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nReviewed-by: Mike Turquette \u003cmturquette@linaro.org\u003e\n"
    }
  ]
}