)]}'
{
  "log": [
    {
      "commit": "81b279d80a63628e580c71a31d30a8c3b3047ad4",
      "tree": "d0695169d5445ce6f7bcd50e558b196dd47f2a1e",
      "parents": [
        "ab2dde9924dd1ddb791fa8b14aa52e1df681e20c"
      ],
      "author": {
        "name": "Sekhar Nori",
        "email": "nsekhar@ti.com",
        "time": "Sun Mar 11 18:16:12 2012 +0530"
      },
      "committer": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Mon Mar 12 11:53:33 2012 -0600"
      },
      "message": "gpio/davinci: fix enabling unbanked GPIO IRQs\n\nUnbanked GPIO IRQ handling code made a copy of just\nthe irq_chip structure for GPIO IRQ lines which caused\nproblems after the generic IRQ chip conversion because\nthere was no valid irq_chip_type structure with the\nright \"regs\" populated. irq_gc_mask_set_bit() was\ntherefore accessing random addresses.\n\nFix it by making a copy of irq_chip_type structure\ninstead. This will ensure sane register offsets.\n\nCc: \u003cstable@vger.kernel.org\u003e # v3.0.x+\nReported-by: Jon Povey \u003cJon.Povey@racelogic.co.uk\u003e\nTested-by: Jon Povey \u003cJon.Povey@racelogic.co.uk\u003e\nSigned-off-by: Sekhar Nori \u003cnsekhar@ti.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n"
    },
    {
      "commit": "ab2dde9924dd1ddb791fa8b14aa52e1df681e20c",
      "tree": "56310874792ccd9208bae177cbd63d62630f9313",
      "parents": [
        "8805f410e4fb88a56552c1af42d61b38837a38fd"
      ],
      "author": {
        "name": "Sekhar Nori",
        "email": "nsekhar@ti.com",
        "time": "Sun Mar 11 18:16:11 2012 +0530"
      },
      "committer": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Mon Mar 12 11:49:33 2012 -0600"
      },
      "message": "gpio/davinci: fix oops on unbanked gpio irq request\n\nUnbanked GPIO irq setup code was overwriting chip_data leading\nto the following oops on request_irq()\n\nUnable to handle kernel paging request at virtual address febfffff\npgd \u003d c22dc000\n[febfffff] *pgd\u003d00000000\nInternal error: Oops: 801 [#1] PREEMPT\nModules linked in: mcu(+) edmak irqk cmemk\nCPU: 0    Not tainted  (3.0.0-rc7+ #93)\nPC is at irq_gc_mask_set_bit+0x68/0x7c\nLR is at vprintk+0x22c/0x484\npc : [\u003cc0080c0c\u003e]    lr : [\u003cc00457e0\u003e]    psr: 60000093\nsp : c33e3ba0  ip : c33e3af0  fp : c33e3bc4\nr10: c04555bc  r9 : c33d4340  r8 : 60000013\nr7 : 0000002d  r6 : c04555bc  r5 : fec67010  r4 : 00000000\nr3 : c04734c8  r2 : fec00000  r1 : ffffffff  r0 : 00000026\nFlags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment user\nControl: 0005317f  Table: 822dc000  DAC: 00000015\nProcess modprobe (pid: 526, stack limit \u003d 0xc33e2270)\nStack: (0xc33e3ba0 to 0xc33e4000)\n3ba0: 00000000 c007d3d4 c33e3bcc c04555bc c04555bc c33d4340 c33e3bdc c33e3bc8\n3bc0: c007f5f8 c0080bb4 00000000 c04555bc c33e3bf4 c33e3be0 c007f654 c007f5c0\n3be0: 00000000 c04555bc c33e3c24 c33e3bf8 c007e6e8 c007f618 c01f2284 c0350af8\n3c00: c0405214 bf016c98 00000001 00000000 c33dc008 0000002d c33e3c54 c33e3c28\n3c20: c007e888 c007e408 00000001 c23ef880 c33dc000 00000000 c33dc080 c25caa00\n3c40: c0487498 bf017078 c33e3c94 c33e3c58 bf016b44 c007e7d4 bf017078 c33dc008\n3c60: c25caa08 c33dc008 c33e3c84 bf017484 c25caa00 c25caa00 c01f5f48 c25caa08\n3c80: c0496d60 bf017484 c33e3ca4 c33e3c98 c022a698 bf01692c c33e3cd4 c33e3ca8\n3ca0: c01f5d88 c022a688 00000000 bf017484 c25caa00 c25caa00 c01f5f48 c25caa08\n3cc0: c0496d60 00000000 c33e3cec c33e3cd8 c01f5f8c c01f5d10 00000000 c33e3cf0\n3ce0: c33e3d14 c33e3cf0 c01f5210 c01f5f58 c303cb48 c25ecf94 c25caa00 c25caa00\n3d00: c25caa34 c33e3dd8 c33e3d34 c33e3d18 c01f6044 c01f51b8 c0496d3c c25caa00\n3d20: c044e918 c33e3dd8 c33e3d44 c33e3d38 c01f4ff4 c01f5fcc c33e3d94 c33e3d48\n3d40: c01f3d10 c01f4fd8 00000000 c044e918 00000000 00000000 c01f52c0 c034d570\n3d60: c33e3d84 c33e3d70 c022bf84 c25caa00 00000000 c044e918 c33e3dd8 c25c2e00\n3d80: c0496d60 bf01763c c33e3db4 c33e3d98 c022b1a0 c01f384c c25caa00 c33e3dd8\n3da0: 00000000 c33e3dd8 c33e3dd4 c33e3db8 c022b27c c022b0e8 00000000 bf01763c\n3dc0: c0451c80 c33e3dd8 c33e3e34 c33e3dd8 bf016f60 c022b210 5f75636d 746e6f63\n3de0: 006c6f72 00000000 00000000 00000000 00000000 00000000 00000000 bf0174bc\n3e00: 00000000 00989680 00000000 00000020 c0451c80 c0451c80 bf0174dc c01f5eb0\n3e20: c33f0f00 bf0174dc c33e3e44 c33e3e38 c01f72f4 bf016e2c c33e3e74 c33e3e48\n3e40: c01f5d88 c01f72e4 00000000 c0451c80 c0451cb4 bf0174dc c01f5eb0 c33f0f00\n3e60: c0473100 00000000 c33e3e94 c33e3e78 c01f5f44 c01f5d10 00000000 c33e3e98\n3e80: bf0174dc c01f5eb0 c33e3ebc c33e3e98 c01f5534 c01f5ec0 c303c038 c3061c30\n3ea0: 00003cd8 00098258 bf0174dc c0462ac8 c33e3ecc c33e3ec0 c01f5bec c01f54dc\n3ec0: c33e3efc c33e3ed0 c01f4d30 c01f5bdc bf0173a0 c33e2000 00003cd8 00098258\n3ee0: bf0174dc c33e2000 c00301a4 bf019000 c33e3f1c c33e3f00 c01f6588 c01f4c8c\n3f00: 00003cd8 00098258 00000000 c33e2000 c33e3f2c c33e3f20 c01f777c c01f6524\n3f20: c33e3f3c c33e3f30 bf019014 c01f7740 c33e3f7c c33e3f40 c002f3ec bf019010\n3f40: 00000000 00003cd8 00098258 bf017518 00000000 00003cd8 00098258 bf017518\n3f60: 00000000 c00301a4 c33e2000 00000000 c33e3fa4 c33e3f80 c007b934 c002f3c4\n3f80: c00b307c c00b2f48 00003cd8 00000000 00000003 00000080 00000000 c33e3fa8\n3fa0: c0030020 c007b8b8 00003cd8 00000000 00098288 00003cd8 00098258 00098240\n3fc0: 00003cd8 00000000 00000003 00000080 00098008 00098028 00098288 00000001\n3fe0: be892998 be892988 00013d7c 40178740 60000010 00098288 09089041 00200845\nBacktrace:\n[\u003cc0080ba4\u003e] (irq_gc_mask_set_bit+0x0/0x7c) from [\u003cc007f5f8\u003e] (irq_enable+0x48/0x58)\n r6:c33d4340 r5:c04555bc r4:c04555bc\n[\u003cc007f5b0\u003e] (irq_enable+0x0/0x58) from [\u003cc007f654\u003e] (irq_startup+0x4c/0x54)\n r5:c04555bc r4:00000000\n[\u003cc007f608\u003e] (irq_startup+0x0/0x54) from [\u003cc007e6e8\u003e] (__setup_irq+0x2f0/0x3cc)\n r5:c04555bc r4:00000000\n[\u003cc007e3f8\u003e] (__setup_irq+0x0/0x3cc) from [\u003cc007e888\u003e] (request_threaded_irq+0xc4/0x110)\n r8:0000002d r7:c33dc008 r6:00000000 r5:00000001 r4:bf016c98\n[\u003cc007e7c4\u003e] (request_threaded_irq+0x0/0x110) from [\u003cbf016b44\u003e] (mcu_spi_probe+0x228/0x37c [mcu])\n[\u003cbf01691c\u003e] (mcu_spi_probe+0x0/0x37c [mcu]) from [\u003cc022a698\u003e] (spi_drv_probe+0x20/0x24)\n[\u003cc022a678\u003e] (spi_drv_probe+0x0/0x24) from [\u003cc01f5d88\u003e] (driver_probe_device+0x88/0x1b0)\n[\u003cc01f5d00\u003e] (driver_probe_device+0x0/0x1b0) from [\u003cc01f5f8c\u003e] (__device_attach+0x44/0x48)\n[\u003cc01f5f48\u003e] (__device_attach+0x0/0x48) from [\u003cc01f5210\u003e] (bus_for_each_drv+0x68/0x94)\n r5:c33e3cf0 r4:00000000\n[\u003cc01f51a8\u003e] (bus_for_each_drv+0x0/0x94) from [\u003cc01f6044\u003e] (device_attach+0x88/0xa0)\n r7:c33e3dd8 r6:c25caa34 r5:c25caa00 r4:c25caa00\n[\u003cc01f5fbc\u003e] (device_attach+0x0/0xa0) from [\u003cc01f4ff4\u003e] (bus_probe_device+0x2c/0x4c)\n r7:c33e3dd8 r6:c044e918 r5:c25caa00 r4:c0496d3c\n[\u003cc01f4fc8\u003e] (bus_probe_device+0x0/0x4c) from [\u003cc01f3d10\u003e] (device_add+0x4d4/0x648)\n[\u003cc01f383c\u003e] (device_add+0x0/0x648) from [\u003cc022b1a0\u003e] (spi_add_device+0xc8/0x128)\n[\u003cc022b0d8\u003e] (spi_add_device+0x0/0x128) from [\u003cc022b27c\u003e] (spi_new_device+0x7c/0xb4)\n r7:c33e3dd8 r6:00000000 r5:c33e3dd8 r4:c25caa00\n[\u003cc022b200\u003e] (spi_new_device+0x0/0xb4) from [\u003cbf016f60\u003e] (mcu_probe+0x144/0x224 [mcu])\n r7:c33e3dd8 r6:c0451c80 r5:bf01763c r4:00000000\n[\u003cbf016e1c\u003e] (mcu_probe+0x0/0x224 [mcu]) from [\u003cc01f72f4\u003e] (platform_drv_probe+0x20/0x24)\n[\u003cc01f72d4\u003e] (platform_drv_probe+0x0/0x24) from [\u003cc01f5d88\u003e] (driver_probe_device+0x88/0x1b0)\n[\u003cc01f5d00\u003e] (driver_probe_device+0x0/0x1b0) from [\u003cc01f5f44\u003e] (__driver_attach+0x94/0x98)\n[\u003cc01f5eb0\u003e] (__driver_attach+0x0/0x98) from [\u003cc01f5534\u003e] (bus_for_each_dev+0x68/0x94)\n r7:c01f5eb0 r6:bf0174dc r5:c33e3e98 r4:00000000\n[\u003cc01f54cc\u003e] (bus_for_each_dev+0x0/0x94) from [\u003cc01f5bec\u003e] (driver_attach+0x20/0x28)\n r7:c0462ac8 r6:bf0174dc r5:00098258 r4:00003cd8\n[\u003cc01f5bcc\u003e] (driver_attach+0x0/0x28) from [\u003cc01f4d30\u003e] (bus_add_driver+0xb4/0x258)\n[\u003cc01f4c7c\u003e] (bus_add_driver+0x0/0x258) from [\u003cc01f6588\u003e] (driver_register+0x74/0x158)\n[\u003cc01f6514\u003e] (driver_register+0x0/0x158) from [\u003cc01f777c\u003e] (platform_driver_register+0x4c/0x60)\n r7:c33e2000 r6:00000000 r5:00098258 r4:00003cd8\n[\u003cc01f7730\u003e] (platform_driver_register+0x0/0x60) from [\u003cbf019014\u003e] (mcu_init+0x14/0x20 [mcu])\n[\u003cbf019000\u003e] (mcu_init+0x0/0x20 [mcu]) from [\u003cc002f3ec\u003e] (do_one_initcall+0x38/0x170)\n[\u003cc002f3b4\u003e] (do_one_initcall+0x0/0x170) from [\u003cc007b934\u003e] (sys_init_module+0x8c/0x1a4)\n[\u003cc007b8a8\u003e] (sys_init_module+0x0/0x1a4) from [\u003cc0030020\u003e] (ret_fast_syscall+0x0/0x2c)\n r7:00000080 r6:00000003 r5:00000000 r4:00003cd8\nCode: e1844003 e585400c e596300c e5932064 (e7814002)\n\nFix the issue.\n\nCc: \u003cstable@vger.kernel.org\u003e # v3.0.x+\nReported-by: Jon Povey \u003cJon.Povey@racelogic.co.uk\u003e\nSigned-off-by: Sekhar Nori \u003cnsekhar@ti.com\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n"
    },
    {
      "commit": "526a0dc771a5cac3224e26abd1f018976b967516",
      "tree": "70dcc181ec6d644ec9d41b483cf6037dda4fd1c8",
      "parents": [
        "058b96d445a05eac71be5e6b5b5db34412b4b175"
      ],
      "author": {
        "name": "Axel Lin",
        "email": "axel.lin@gmail.com",
        "time": "Mon Sep 05 03:29:04 2011 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Mon Sep 05 11:26:34 2011 +0100"
      },
      "message": "ARM: 7074/1: gpio: davinci: eliminate unused variable warnings\n\nSince commit 5093aec872e5be7a55d8dd2b639e8a3818dc19db\n\"arm: davinci: Cleanup irq chip code\", the variable \u0027mask\u0027 and \u0027g\u0027\nare not being used.\n\nThis patch eliminate below unused variable warnings:\n\n  CC      drivers/gpio/gpio-davinci.o\ndrivers/gpio/gpio-davinci.c: In function \u0027gpio_irq_type\u0027:\ndrivers/gpio/gpio-davinci.c:234: warning: unused variable \u0027mask\u0027\ndrivers/gpio/gpio-davinci.c:233: warning: unused variable \u0027g\u0027\n\nSigned-off-by: Axel Lin \u003caxel.lin@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "8338d87fea2c001b4f5a07f9217df89956d1fddd",
      "tree": "efc6a257dacf3dd87c90282fdaaa626939c3e47e",
      "parents": [
        "386ab6400a4d2331f60695cb355dcc3790ccfbcc"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@linaro.org",
        "time": "Mon Aug 22 08:39:28 2011 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Mon Aug 22 09:12:55 2011 +0100"
      },
      "message": "ARM: 7038/1: mach-davinci: move GPIO driver to GPIO subsystem\n\nAs per example from the other ARM boards, push the DaVinci GPIO\ndriver down to the GPIO subsystem so it can be consolidated.\n\nCc: Sekhar Nori \u003cnsekhar@ti.com\u003e\nCc: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "2f8163baada3dbd0ce891c35bc59ae46e773487a",
      "tree": "cf148d2c014e777bf374e49daa74ba68e440a5d7",
      "parents": [
        "b7a949549de42e4cf8af301c63ee8af13a06a956"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Tue Jul 26 10:53:52 2011 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Mon Aug 08 14:27:41 2011 +0100"
      },
      "message": "ARM: gpio: convert includes of mach/gpio.h and asm/gpio.h to linux/gpio.h\n\nConvert arch/arm includes of mach/gpio.h and asm/gpio.h to linux/gpio.h\nbefore we start consolidating the individual platform implementations\nof the gpio header files.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "f299bb9527abfa6ee45a5e26288b5e3a619f01d6",
      "tree": "9ab723a7349506d49500cd795fe53ccdbcd88855",
      "parents": [
        "620917de59eeb934b9f8cf35cc2d95c1ac8ed0fc"
      ],
      "author": {
        "name": "Ido Yariv",
        "email": "ido@wizery.com",
        "time": "Tue Jul 12 00:03:11 2011 +0300"
      },
      "committer": {
        "name": "Sekhar Nori",
        "email": "nsekhar@ti.com",
        "time": "Tue Jul 12 14:21:43 2011 +0530"
      },
      "message": "arm: davinci: Fix low level gpio irq handlers\u0027 argument\n\nCommit 7416401 (\"arm: davinci: Fix fallout from generic irq chip\nconversion\") introduced a bug, causing low level interrupt handlers to\nget a bogus irq number as an argument. The gpio irq handler falsely\nassumes that the handler data is the irq base number and that is no\nlonger true.\n\nSet the irq handler data to be a pointer to the corresponding gpio\ncontroller. The chained irq handler can then use it to extract both the\nirq base number and the gpio registers structure.\n\nSigned-off-by: Ido Yariv \u003cido@wizery.com\u003e\nCC: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n[nsekhar@ti.com: renamed \"ctl\" to \"d\", simplified indexing logic for chips and\ntook care of odd bank handling in irq handler]\nSigned-off-by: Sekhar Nori \u003cnsekhar@ti.com\u003e\n"
    },
    {
      "commit": "7416401661fad5c7ee9edb17cb54e7bff7a74dfe",
      "tree": "598260d3ccbdeb7bb8b93c0ee6ec79fda48bbf28",
      "parents": [
        "59c5f46fbe01a00eedf54a23789634438bb80603"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Mon Jun 06 11:51:43 2011 +0200"
      },
      "committer": {
        "name": "Sekhar Nori",
        "email": "nsekhar@ti.com",
        "time": "Wed Jun 08 14:33:52 2011 +0530"
      },
      "message": "arm: davinci: Fix fallout from generic irq chip conversion\n\nThe code which does the chained handler setup was overwriting\nchip_data.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nTested-by: Holger Hans Peter Freyther \u003cholger@freyther.de\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@ti.com\u003e\nSigned-off-by: Sekhar Nori \u003cnsekhar@ti.com\u003e\n"
    },
    {
      "commit": "6845664a6a7d443f03883db59d10749d38d98b8e",
      "tree": "4b4499f4d41f24152190220d93ea186fbf991fca",
      "parents": [
        "25a5662a13e604d86b0a9fd71703582a7393d8ec"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Mar 24 13:25:22 2011 +0100"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Tue Mar 29 14:47:57 2011 +0200"
      },
      "message": "arm: Cleanup the irq namespace\n\nConvert to the new function names. Automated with coccinelle.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "5093aec872e5be7a55d8dd2b639e8a3818dc19db",
      "tree": "13fa9ff0778bfd5463c79fa3a81239afb81dc374",
      "parents": [
        "d1735a2ebd8868ee9b5bb419860e633f0f839042"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Mar 24 12:47:04 2011 +0100"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Tue Mar 29 14:47:56 2011 +0200"
      },
      "message": "arm: davinci: Cleanup irq chip code\n\nMake use of the new functionality which ensures that irq_set_type is\ncalled with the chip masked. Unmask is only done when the interrupt is\nnot disabled.\n\nRetrieve the trigger type from irq_data in unmask\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "23265442b02b3cc3c0dd2bf89bc235970c629806",
      "tree": "97a985d585a838dbd2e4e8aee53d6cf42597bfaa",
      "parents": [
        "8ad357ca4dd99a0f277528e63746bb04629de213"
      ],
      "author": {
        "name": "Lennert Buytenhek",
        "email": "buytenh@wantstofly.org",
        "time": "Mon Nov 29 10:27:27 2010 +0100"
      },
      "committer": {
        "name": "Lennert Buytenhek",
        "email": "buytenh@wantstofly.org",
        "time": "Thu Jan 13 17:18:26 2011 +0100"
      },
      "message": "ARM: davinci: irq_data conversion.\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@secretlab.ca\u003e\n"
    },
    {
      "commit": "b8d44293952e4b32b8595d924a377351f3cd1565",
      "tree": "9d5e44f154f18ce9a5496e9f9198fd03e57c8a73",
      "parents": [
        "a6374f53405b719c767c6318fe052a6d8f32cd89"
      ],
      "author": {
        "name": "Cyril Chemparathy",
        "email": "cyril@ti.com",
        "time": "Fri May 07 17:06:32 2010 -0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 13 10:05:22 2010 -0700"
      },
      "message": "Davinci: gpio - use ioremap()\n\nThis patch modifies the gpio_base definition in davinci_soc_info to be a\nphysical address, which is then ioremap()ed by the gpio initialization\nfunction.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "5b3a05ca911688c53680f2b020a1512b9da29c89",
      "tree": "4724dd98e7ef949d1976865ad1198c8693d341da",
      "parents": [
        "b27b6d03f245e5eaf6473da58a2612077fb7cfe7"
      ],
      "author": {
        "name": "Cyril Chemparathy",
        "email": "cyril@ti.com",
        "time": "Sat May 01 18:38:27 2010 -0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:09 2010 -0700"
      },
      "message": "Davinci: eliminate pinmux offset verbosity\n\nPinmux registers are sequential, and do not need to be enumerated out as they\ncurrently are.  This reduces code volume and keeps things simple.\n\nIf some future SoC comes up with a discontiguous register map, PINMUX() can\nthen be expanded with local token pasting.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "b27b6d03f245e5eaf6473da58a2612077fb7cfe7",
      "tree": "b6ed359c8b604edcaed5025aa83c57d77daec1a9",
      "parents": [
        "686b634a07451fc4fe3b712fe211bfa861a53241"
      ],
      "author": {
        "name": "Cyril Chemparathy",
        "email": "cyril@ti.com",
        "time": "Sat May 01 18:37:55 2010 -0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:09 2010 -0700"
      },
      "message": "Davinci: gpio - fine grained locking\n\nThis patch eliminates the global gpio_lock, and implements a per-controller\nlock instead.  This also switches to irqsave/irqrestore locks in case gpios\nare manipulated in isr.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nTested-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "686b634a07451fc4fe3b712fe211bfa861a53241",
      "tree": "109557ee13bc43e3e574fd54fe2354a2da7d6dc9",
      "parents": [
        "c12f415a9144a76dc99df34f56ce3022207ad1d0"
      ],
      "author": {
        "name": "Cyril Chemparathy",
        "email": "cyril@ti.com",
        "time": "Sat May 01 18:37:54 2010 -0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:08 2010 -0700"
      },
      "message": "Davinci: gpio - controller type support\n\nThis patch allows for gpio controllers that deviate from those found on\ntraditional davinci socs.  davinci_soc_info has an added field to indicate the\nsoc-specific gpio controller type.  The gpio initialization code then bails\nout if necessary.\n\nMore elements (tnetv107x) to be added later into enum davinci_gpio_type.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nTested-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "c12f415a9144a76dc99df34f56ce3022207ad1d0",
      "tree": "6fa81f4b2494ab8d0bf4f6bd7f71b5c0bdae8ecb",
      "parents": [
        "99e9e52de635728d7c89a0fdf79b307f3082cf3a"
      ],
      "author": {
        "name": "Cyril Chemparathy",
        "email": "cyril@ti.com",
        "time": "Sat May 01 18:37:53 2010 -0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:08 2010 -0700"
      },
      "message": "Davinci: gpio - register layout invariant inlines\n\nThis patch renders the inlined gpio accessors in gpio.h independent of the\nunderlying controller\u0027s register layout.  This is done by including three new\nfields in davinci_gpio_controller to hold the addresses of the set, clear, and\nin data registers.\n\nOther changes:\n\n1. davinci_gpio_regs structure definition moved to gpio.c.  This structure is\nno longer common across all davinci socs (davinci_gpio_controller is).\n\n2. controller base address calculation code (gpio2controller()) moved to\ngpio.c as this was no longer necessary for the inline implementation.\n\n3. modified inline range checks to use davinci_soc_info.gpio_num instead of\nDAVINCI_N_GPIO.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nTested-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "99e9e52de635728d7c89a0fdf79b307f3082cf3a",
      "tree": "554517b1dc2552819954174c8ddafd3927f34970",
      "parents": [
        "ba4a984e838dfb1c46135ff8cadeea5f8ca5fd0a"
      ],
      "author": {
        "name": "Cyril Chemparathy",
        "email": "cyril@ti.com",
        "time": "Sat May 01 18:37:52 2010 -0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:08 2010 -0700"
      },
      "message": "Davinci: gpio - structs and functions renamed\n\nRenamed gpio types to something more sensible:\n\tstruct gpio_controller\t--\u003e struct davinci_gpio_regs\n\tstruct davinci_gpio\t--\u003e struct davinci_gpio_controller\n\tgpio2controller()\t--\u003e gpio2regs()\n\tirq2controller()\t--\u003e irq2regs()\n\nThis change also moves davinci_gpio_controller definition to gpio.h.\nEventually, the gpio registers structure will be moved to gpio.c and no longer\na common cross-soc definition.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nTested-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "ba4a984e838dfb1c46135ff8cadeea5f8ca5fd0a",
      "tree": "1650621c7dbdfe8bcb3b9d9d2198715bc0d21043",
      "parents": [
        "7a9978a1e2225507025a8b90b4289d506a416bd9"
      ],
      "author": {
        "name": "Cyril Chemparathy",
        "email": "cyril@ti.com",
        "time": "Sat May 01 18:37:51 2010 -0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:08 2010 -0700"
      },
      "message": "Davinci: gpio - minor cleanup\n\nmacroized repeated container_of()s to improve readability.\nunified direction in/out functions.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nTested-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "21ce873d211a42e315558d6ae09a8bb04508a592",
      "tree": "bc409c611d9d77c61b109a97061584792753a186",
      "parents": [
        "28552c2eae472a0a52d1cdb02eb32766c7f690e1"
      ],
      "author": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu Feb 25 16:49:56 2010 -0800"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:01 2010 -0700"
      },
      "message": "davinci: sparse: gpio: void casting\n\nCleanup usage of void pointers when using genirq.  genirq API\ntakes and returns void *, where this GPIO API is using those\nas __iomem pointers.\n\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "28552c2eae472a0a52d1cdb02eb32766c7f690e1",
      "tree": "b996bede5ecde42ad8b95d99b494418b1acd2a90",
      "parents": [
        "66f41d4c5c8a5deed66fdcc84509376c9a0bf9d8"
      ],
      "author": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu Feb 25 15:36:38 2010 -0800"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 06 15:02:01 2010 -0700"
      },
      "message": "davinci: misc cleanups from sparse\n\n- Convert data/functions to static\n- include headers for missing declarations\n- pointer cleanups:  struct foo *__iomem f --\u003e struct foo __iomem *f;\n\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "42d399e4189346b495fec8a9a267e8b7f744ee48",
      "tree": "0549b107249544fc2913a9f3a5c868f6086e9df0",
      "parents": [
        "69872e93d971e72cd43fdf90befaaffd8e32437a"
      ],
      "author": {
        "name": "Sergei Shtylyov",
        "email": "sshtylyov@ru.mvista.com",
        "time": "Fri Oct 02 22:05:29 2009 +0400"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Wed Nov 25 10:21:31 2009 -0800"
      },
      "message": "DaVinci: remove unneeded #include\u0027s\n\nThere have accumulated quite a lot of them after the code reorganizations...\n\nIn several cases I had to replace #include \u003clinux/dma-mapping.h\u003e which wasn\u0027t\nneeded directly but happened to #include \u003clinux/err.h\u003e which was needed.\n\nSigned-off-by: Sergei Shtylyov \u003csshtylyov@ru.mvista.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "7a36071e7954836ba437987e5ca4ced174462b28",
      "tree": "921d150b7f2cc677d226daa40a18f3ab9bf6da78",
      "parents": [
        "af5dbaef76cb01995639cef10ca6f5a2b08207e8"
      ],
      "author": {
        "name": "David Brownell",
        "email": "dbrownell@users.sourceforge.net",
        "time": "Thu Jun 25 17:01:31 2009 -0700"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Wed Aug 26 10:57:00 2009 +0300"
      },
      "message": "davinci: dm365 gpio irq support\n\nSupport DM365 GPIOs ... primarily by handling non-banked GPIO IRQs:\n\n - Flag DM365 chips as using non-banked GPIO interrupts, using a\n   new soc_info field.\n\n - Replace the gpio_to_irq() mapping logic.  This now uses some\n   runtime infrastructure, keyed off that new soc_info field,\n   which doesn\u0027t handle irq_to_gpio().\n\n - Provide a new irq_chip ... GPIO IRQs handled directly by AINTC\n   still need edge triggering managed by the GPIO controller.\n\nDM365 chips no longer falsely report 104 GPIO IRQs as they boot.\n\nIntelligence about IRQ muxing is missing, so for the moment this\nonly exposes the first eight DM365 GPIOs, which are never muxed.\nThe next eight are muxed, half with Ethernet (which uses most of\nthose pins anyway).\n\nTested on DM355 (10 unbanked IRQs _or_ 104 banked ones) and also\non DM365 (16 unbanked ones, only 8 made available).\n\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "a994955cc091a8a51b7d7412174d9cf6de04d26b",
      "tree": "14c62610ee3ec0aa59fa5df49d4bf5ac88c8eb4c",
      "parents": [
        "951d6f6d703110790256abfce03ced117d2dcc6b"
      ],
      "author": {
        "name": "Mark A. Greer",
        "email": "mgreer@mvista.com",
        "time": "Wed Apr 15 12:40:35 2009 -0700"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Thu May 28 15:16:30 2009 -0700"
      },
      "message": "davinci: Make GPIO code more generic\n\nThe current gpio code needs to know the number of\ngpio irqs there are and what the bank irq number is.\nTo determine those values, it checks the SoC type.\n\nIt also assumes that the base address and the number\nof irqs the interrupt controller uses is fixed.\n\nTo clean up the SoC checks and make it support\ndifferent base addresses and interrupt controllers,\nhave the SoC-specific code set those values in\nthe soc_info structure and have the gpio code\nreference them there.\n\nSigned-off-by: Mark A. Greer \u003cmgreer@mvista.com\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "dc75602628472d7fbc4cb43f010bf0257e95ab71",
      "tree": "05632b60b16e7e3334ea5000620c8e8ece844a3c",
      "parents": [
        "df4aab46a8256ac0f0c2701b3fe23b7dd05e6b48"
      ],
      "author": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Mon May 11 11:04:53 2009 -0700"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Tue May 26 07:17:54 2009 -0700"
      },
      "message": "davinci: fixups for banked GPIO interrupt handling\n\nThis patch seems to get me much more reliable performance using the\nGPIO banked interrupts on dm355 for the dm9000 driver.\n\nChanges include:\n\n- init GPIO handling along with normal GPIO init\n- mask the level-sensitive bank IRQ during handling\n\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "df4aab46a8256ac0f0c2701b3fe23b7dd05e6b48",
      "tree": "3ac065f49b9f20d0e759b829824caf7553358e32",
      "parents": [
        "59a3759d0fe8d969888c741bb33f4946e4d3750d"
      ],
      "author": {
        "name": "David Brownell",
        "email": "dbrownell@users.sourceforge.net",
        "time": "Mon May 04 13:14:27 2009 -0700"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Tue May 26 07:17:54 2009 -0700"
      },
      "message": "davinci: gpio irq enable tweaks\n\nFix two IRQ triggering bugs affecting GPIO IRQs:\n\n - Make sure enabling with IRQ_TYPE_NONE (\"default, unspecified\")\n   isn\u0027t a NOP ... default to both edges, at least one must work.\n\n - As noted by Kevin Hilman, setting the irq trigger type for a\n   banked gpio interrupt shouldn\u0027t enable irqs that are disabled.\n\nSince GPIO IRQs haven\u0027t been used much yet, it\u0027s not clear these\nbugs could have affected anything.  The few current users don\u0027t\nseem to have been obviously suffering from these issues.\n\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "474dad54baee8f8abe63ac334357a37021147701",
      "tree": "1d8f57b71f2e36ac9442b9d6fad685234f1ae853",
      "parents": [
        "a4768d2275cb7c0d2a665b9ad4de07834be0714b"
      ],
      "author": {
        "name": "David Brownell",
        "email": "dbrownell@users.sourceforge.net",
        "time": "Sun Dec 07 11:46:23 2008 -0800"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Mon Apr 27 09:49:43 2009 -0700"
      },
      "message": "davinci: gpio bugfixes\n\nUpdate the DaVinci GPIO code to work better on non-dm6446 parts,\nnotably the dm355:\n\n - Only handle the number of GPIOs the chip actually has.  So\n   for example on dm6467, GPIO-42 is the last GPIO, and trying\n   to use GPIO-43 now fails cleanly; or GPIO-72 on dm6446.\n\n - Enable GPIO interrupts on each 16-bit GPIO-irq bank ...\n   previously, only the first five were enabled, so GPIO-80\n   and above (on dm355) wouldn\u0027t trigger IRQs.\n\n - Use the right IRQ for each GPIO bank.  The wrong values were\n   used for dm355 chips, so GPIO IRQs got routed incorrectly.\n\n - Handle up to four pairs of 16-bit GPIO banks ... previously\n   only three were handled, so accessing GPIO-96 and up (e.g. on\n   dm355) would oops.\n\n - Update several comments that were dm6446-specific.\n\nVerified by receiving GPIO-1 (dm9000) and GPIO-5 (msp430) IRQs\non the DM355 EVM.\n\nOne thing this doesn\u0027t do is handle the way some of the GPIO\nnumbers on dm6467 are reserved but aren\u0027t valid as GPIOs.  Some\nbitmap logic could fix that if needed.\n\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "c97f68145e8067b3ac4b126a6faebf90f9ffc302",
      "tree": "eb2060681552a00e9efa98224b95f69a3dc84390",
      "parents": [
        "b1add0480a95b6ceaece5caf6c50614771eae9b2",
        "7bff3c4ce44ea48f50dc47a5994454984bd08c59"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Thu Oct 09 21:33:05 2008 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Oct 09 21:33:05 2008 +0100"
      },
      "message": "Merge branch \u0027for-rmk\u0027 of git://source.mvista.com/git/linux-davinci-2.6.git\n\nMerge branch \u0027davinci\u0027 into devel\n"
    },
    {
      "commit": "d8aa0251f12546e9bd1e9ee1d9782d6492819a04",
      "tree": "7be5c9d598bc727bfcc0f04f679f972c68ca346f",
      "parents": [
        "27c4cae28148ad97baa2bf8275f7ebc9e2c37c34"
      ],
      "author": {
        "name": "Dmitry Baryshkov",
        "email": "dbaryshkov@gmail.com",
        "time": "Thu Oct 09 13:36:24 2008 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Oct 09 15:00:36 2008 +0100"
      },
      "message": "[ARM] 5298/1: Drop desc_handle_irq()\n\ndesc_handle_irq() was declared as obsolete since long ago.\nReplace it with generic_handle_irq()\n\nSigned-off-by: Dmitry Baryshkov \u003cdbaryshkov@gmail.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "dce1115bc32d66237102a4c925e1e0a5e82b9945",
      "tree": "ad89ff75c84a433c6a3ca0d8829315edbdf52d0b",
      "parents": [
        "ac7643e4d36c63b190709777d9e03392a7d20477"
      ],
      "author": {
        "name": "David Brownell",
        "email": "dbrownell@users.sourceforge.net",
        "time": "Sun Sep 07 23:41:04 2008 -0700"
      },
      "committer": {
        "name": "Kevin Hilman",
        "email": "khilman@deeprootsystems.com",
        "time": "Wed Sep 17 00:31:41 2008 -0700"
      },
      "message": "ARM: DaVinci: SOC GPIOs use gpiolib\n\nSwitch DaVinci SOC gpios over to using the new GPIO library, so it can\naccess GPIO expanders and other non-SOC GPIOs using the same calls.\n\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Kevin Hilman \u003ckhilman@deeprootsystems.com\u003e\n"
    },
    {
      "commit": "a09e64fbc0094e3073dbb09c3b4bfe4ab669244b",
      "tree": "69689f467179891b498bd7423fcf61925173db31",
      "parents": [
        "a1b81a84fff05dbfef45b7012c26e1fee9973e5d"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Tue Aug 05 16:14:15 2008 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Aug 07 09:55:48 2008 +0100"
      },
      "message": "[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach\n\nThis just leaves include/asm-arm/plat-* to deal with.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "3d9edf09d4525dad95f98b31f31aa86b8071fab9",
      "tree": "e923d8ff8c71e83ed4edf97f7f52a95c34da2683",
      "parents": [
        "3e062b07ada88edb9ffdd147e39c7df4b4418f64"
      ],
      "author": {
        "name": "Vladimir Barinov",
        "email": "vbarinov@ru.mvista.com",
        "time": "Tue Jul 10 13:03:43 2007 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Jul 12 09:57:09 2007 +0100"
      },
      "message": "[ARM] 4457/2: davinci: GPIO support\n\nSupport GPIO driver for TI DaVinci SoC\n\nSigned-off-by: Vladimir Barinov \u003cvbarino@ru.mvista.com\u003e\nAcked-by: David Brownell \u003cdavid-b@pacbell.net\u003e\nAcked-by: Kevin Hilman \u003ckhilman@mvista.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    }
  ]
}