)]}' { "log": [ { "commit": "1267b3a325f00291e847ea4a001ccabe5d5516f2", "tree": "c7a9ceaf50653d87278362a05389b91ab74fca1d", "parents": [ "0cbaa57d828aa0a067e06d3c6d795b12ae9fb776" ], "author": { "name": "Chunhe Lan", "email": "Chunhe.Lan@freescale.com", "time": "Wed Mar 07 15:16:26 2012 +0800" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon May 07 09:27:26 2012 -0600" }, "message": "PCI: fix uninitialized variable \u0027cap_mask\u0027\n\nGet rid of these:\n\ndrivers/pci/pcie/portdrv_core.c: In function \u0027pcie_port_device_register\u0027:\ndrivers/pci/pcie/portdrv_core.c:275:16: warning: \u0027cap_mask\u0027 may be used\nuninitialized in this function [-Wuninitialized]\ndrivers/pci/pcie/portdrv_core.c:240:6: note: \u0027cap_mask\u0027 was declared here\n\nIn some cases, \u0027cap_mask\u0027 may be not set in pcie_port_platform_notify,\nholding a garbage value.\n\nSigned-off-by: Chunhe Lan \u003cChunhe.Lan@freescale.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "c9651e70ad0aa499814817cbf3cc1d0b806ed3a1", "tree": "6347cadf5e3d2835bf63dc52a8fdfe2daaea5161", "parents": [ "cdb0f9a1ad2ee3c11e21bc99f0c2021a02844666" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Tue Mar 27 10:17:41 2012 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Mar 31 12:49:56 2012 -0700" }, "message": "ASPM: Fix pcie devices with non-pcie children\n\nSince 3.2.12 and 3.3, some systems are failing to boot with a BUG_ON.\nSome other systems using the pata_jmicron driver fail to boot because no\ndisks are detected. Passing pcie_aspm\u003dforce on the kernel command line\nworks around it.\n\nThe cause: commit 4949be16822e (\"PCI: ignore pre-1.1 ASPM quirking when\nASPM is disabled\") changed the behaviour of pcie_aspm_sanity_check() to\nalways return 0 if aspm is disabled, in order to avoid cases where we\nchanged ASPM state on pre-PCIe 1.1 devices.\n\nThis skipped the secondary function of pcie_aspm_sanity_check which was\nto avoid us enabling ASPM on devices that had non-PCIe children, causing\ntrouble later on. Move the aspm_disabled check so we continue to honour\nthat scenario.\n\nAddresses https://bugzilla.kernel.org/show_bug.cgi?id\u003d42979 and\n http://bugs.debian.org/665420\n\nReported-by: Romain Francoise \u003cromain@orebokech.com\u003e # kernel panic\nReported-by: Chris Holland \u003cbandidoirlandes@gmail.com\u003e # disk detection trouble\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nCc: stable@vger.kernel.org\nTested-by: Hatem Masmoudi \u003chatem.masmoudi@gmail.com\u003e # Dell Latitude E5520\nTested-by: janek \u003cjan0x6c@gmail.com\u003e # pata_jmicron with JMB362/JMB363\n[jn: with more symptoms in log message]\nSigned-off-by: Jonathan Nieder \u003cjrnieder@gmail.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "475c77edf826333aa61625f49d6a2bec26ecb5a6", "tree": "8e1c6c319e347cd3c649fdb0b3ab45971c6b19e7", "parents": [ "934e18b5cb4531cc6e81865bf54115cfd21d1ac6", "1488d5158dcd612fcdaf6b642451b026ee8bbcbb" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 23 14:02:12 2012 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 23 14:02:12 2012 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci\n\nPull PCI changes (including maintainer change) from Jesse Barnes:\n \"This pull has some good cleanups from Bjorn and Yinghai, as well as\n some more code from Yinghai to better handle resource re-allocation\n when enabled.\n\n There\u0027s also a new initcall_debug feature from Arjan which will print\n out quirk timing information to help identify slow quirks for fixing\n or refinement (Yinghai sent in a few patches to do just that once the\n new debug code landed).\n\n Beyond that, I\u0027m handing off PCI maintainership to Bjorn Helgaas.\n He\u0027s been a core PCI and Linux contributor for some time now, and has\n kindly volunteered to take over. I just don\u0027t feel I have the time\n for PCI review and work that it deserves lately (I\u0027ve taken on some\n other projects), and haven\u0027t been as responsive lately as I\u0027d like, so\n I approached Bjorn asking if he\u0027d like to manage things. He\u0027s going\n to give it a try, and I\u0027m confident he\u0027ll do at least as well as I\n have in keeping the tree managed, patches flowing, and keeping things\n stable.\"\n\nFix up some fairly trivial conflicts due to other cleanups (mips device\nresource fixup cleanups clashing with list handling cleanup, ppc iseries\nremoval clashing with pci_probe_only cleanup etc)\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci: (112 commits)\n PCI: Bjorn gets PCI hotplug too\n PCI: hand PCI maintenance over to Bjorn Helgaas\n unicore32/PCI: move \u003casm-generic/pci-bridge.h\u003e include to asm/pci.h\n sparc/PCI: convert devtree and arch-probed bus addresses to resource\n powerpc/PCI: allow reallocation on PA Semi\n powerpc/PCI: convert devtree bus addresses to resource\n powerpc/PCI: compute I/O space bus-to-resource offset consistently\n arm/PCI: don\u0027t export pci_flags\n PCI: fix bridge I/O window bus-to-resource conversion\n x86/PCI: add spinlock held check to \u0027pcibios_fwaddrmap_lookup()\u0027\n PCI / PCIe: Introduce command line option to disable ARI\n PCI: make acpihp use __pci_remove_bus_device instead\n PCI: export __pci_remove_bus_device\n PCI: Rename pci_remove_behind_bridge to pci_stop_and_remove_behind_bridge\n PCI: Rename pci_remove_bus_device to pci_stop_and_remove_bus_device\n PCI: print out PCI device info along with duration\n PCI: Move \"pci reassigndev resource alignment\" out of quirks.c\n PCI: Use class for quirk for usb host controller fixup\n PCI: Use class for quirk for ti816x class fixup\n PCI: Use class for quirk for intel e100 interrupt fixup\n ...\n" }, { "commit": "4949be16822e92a18ea0cc1616319926628092ee", "tree": "51bc0b8620f0e5e0b788803d36d2d71aff7e4e73", "parents": [ "4f262acfde22b63498b5e4f165e53d3bb4e96400" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Tue Mar 06 13:41:49 2012 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Mar 07 20:26:47 2012 -0800" }, "message": "PCI: ignore pre-1.1 ASPM quirking when ASPM is disabled\n\nRight now we won\u0027t touch ASPM state if ASPM is disabled, except in the case\nwhere we find a device that appears to be too old to reliably support ASPM.\nRight now we\u0027ll clear it in that case, which is almost certainly the wrong\nthing to do. The easiest way around this is just to disable the blacklisting\nwhen ASPM is disabled.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nCc: stable@vger.kernel.org\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7570a333d8b00e7fd4b05d898e353000a70210ce", "tree": "0454e2690a7efb093ffe7764ea9dd235e9babf9b", "parents": [ "34a4876e3071ddebf3c98c99ba01c14b059a1361" ], "author": { "name": "MUNEDA Takahiro", "email": "muneda.takahiro@jp.fujitsu.com", "time": "Thu Feb 02 11:09:22 2012 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Feb 23 12:29:35 2012 -0800" }, "message": "PCI: Add pcie_hp\u003dnomsi to disable MSI/MSI-X for pciehp driver\n\nAdd a parameter to avoid using MSI/MSI-X for PCIe native hotplug; it\u0027s\nknown to be buggy on some platforms.\n\nIn my environment, while shutting down, following stack trace is shown\nsometimes.\n\n irq 16: nobody cared (try booting with the \"irqpoll\" option)\n Pid: 1081, comm: reboot Not tainted 3.2.0 #1\n Call Trace:\n \u003cIRQ\u003e [\u003cffffffff810cec1d\u003e] __report_bad_irq+0x3d/0xe0\n [\u003cffffffff810cee1c\u003e] note_interrupt+0x15c/0x210\n [\u003cffffffff810cc485\u003e] handle_irq_event_percpu+0xb5/0x210\n [\u003cffffffff810cc621\u003e] handle_irq_event+0x41/0x70\n [\u003cffffffff810cf675\u003e] handle_fasteoi_irq+0x55/0xc0\n [\u003cffffffff81015356\u003e] handle_irq+0x46/0xb0\n [\u003cffffffff814fbe9d\u003e] do_IRQ+0x5d/0xe0\n [\u003cffffffff814f146e\u003e] common_interrupt+0x6e/0x6e\n [\u003cffffffff8106b040\u003e] ? __do_softirq+0x60/0x210\n [\u003cffffffff8108aeb1\u003e] ? hrtimer_interrupt+0x151/0x240\n [\u003cffffffff814fb5ec\u003e] call_softirq+0x1c/0x30\n [\u003cffffffff810152d5\u003e] do_softirq+0x65/0xa0\n [\u003cffffffff8106ae9d\u003e] irq_exit+0xbd/0xe0\n [\u003cffffffff814fbf8e\u003e] smp_apic_timer_interrupt+0x6e/0x99\n [\u003cffffffff814f9e5e\u003e] apic_timer_interrupt+0x6e/0x80\n \u003cEOI\u003e [\u003cffffffff814f0fb1\u003e] ? _raw_spin_unlock_irqrestore+0x11/0x20\n [\u003cffffffff812629fc\u003e] pci_bus_write_config_word+0x6c/0x80\n [\u003cffffffff81266fc2\u003e] pci_intx+0x52/0xa0\n [\u003cffffffff8127de3d\u003e] pci_intx_for_msi+0x1d/0x30\n [\u003cffffffff8127e4fb\u003e] pci_msi_shutdown+0x7b/0x110\n [\u003cffffffff81269d34\u003e] pci_device_shutdown+0x34/0x50\n [\u003cffffffff81326c4f\u003e] device_shutdown+0x2f/0x140\n [\u003cffffffff8107b981\u003e] kernel_restart_prepare+0x31/0x40\n [\u003cffffffff8107b9e6\u003e] kernel_restart+0x16/0x60\n [\u003cffffffff8107bbfd\u003e] sys_reboot+0x1ad/0x220\n [\u003cffffffff814f4b90\u003e] ? do_page_fault+0x1e0/0x460\n [\u003cffffffff811942d0\u003e] ? __sync_filesystem+0x90/0x90\n [\u003cffffffff8105c9aa\u003e] ? __cond_resched+0x2a/0x40\n [\u003cffffffff814ef090\u003e] ? _cond_resched+0x30/0x40\n [\u003cffffffff81169e17\u003e] ? iterate_supers+0xb7/0xd0\n [\u003cffffffff814f9382\u003e] system_call_fastpath+0x16/0x1b\n handlers:\n [\u003cffffffff8138a0f0\u003e] usb_hcd_irq\n [\u003cffffffff8138a0f0\u003e] usb_hcd_irq\n [\u003cffffffff8138a0f0\u003e] usb_hcd_irq\n Disabling IRQ #16\n\nAn un-wanted interrupt is generated when PCI driver switches from\nMSI/MSI-X to INTx while shutting down the device. The interrupt does\nnot happen if MSI/MSI-X is not used on the device.\nI confirmed that this problem does not happen if pcie_hp\u003dnomsi was\nspecified and hotplug operation worked fine as usual.\n\nv2: Automatically disable MSI/MSI-X against following device:\n PCI bridge: Integrated Device Technology, Inc. Device 807f (rev 02)\nv3: Based on the review comment, combile the if statements.\nv4: Removed module parameter.\n Move some code to build pciehp as a module.\n Move device specific code to driver/pci/quirks.c.\nv5: Drop a device specific code until getting a vendor statement.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: MUNEDA Takahiro \u003cmuneda.takahiro@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ad71c96213a68dfe6d761e3ff7ac7ac267fd612a", "tree": "e1586751c7249035c128de60a5721aafa997e2d5", "parents": [ "f67fd55fa96f7d7295b43ffbc4a97d8f55e473aa" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Fri Feb 03 10:18:13 2012 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Feb 17 09:22:03 2012 -0800" }, "message": "PCI: pcie: Add support for setting default ASPM policy\n\nDistributions may wish to provide different defaults for PCIE ASPM\ndepending on their target audience. Provide a configuration option for\nchoosing the default policy.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "90ab5ee94171b3e28de6bb42ee30b527014e0be7", "tree": "fcf89889f6e881f2b231d3d20287c08174ce4b54", "parents": [ "476bc0015bf09dad39d36a8b19f76f0c181d1ec9" ], "author": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Fri Jan 13 09:32:20 2012 +1030" }, "committer": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Fri Jan 13 09:32:20 2012 +1030" }, "message": "module_param: make bool parameters really bool (drivers \u0026 misc)\n\nmodule_param(bool) used to counter-intuitively take an int. In\nfddd5201 (mid-2009) we allowed bool or int/unsigned int using a messy\ntrick.\n\nIt\u0027s time to remove the int/unsigned int option. For this version\nit\u0027ll simply give a warning, but it\u0027ll break next kernel version.\n\nAcked-by: Mauro Carvalho Chehab \u003cmchehab@redhat.com\u003e\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\n" }, { "commit": "d56641c7723c92487fb4bbcd995ad74169e2329b", "tree": "5d5d0b1d9f060f9bb2f585efb129513b0416f067", "parents": [ "85b8582d7ca516030efb84d94fa29a73c1d9a125" ], "author": { "name": "P. Christeas", "email": "xrg@linux.gr", "time": "Tue Dec 06 20:48:35 2011 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:11:17 2012 -0800" }, "message": "PCI: kconfig: English typo in pci/pcie/Kconfig\n\nJust fix this help text.\n\nSigned-off-by: P. Christeas \u003cxrg@linux.gr\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "10f6dc7eede9a8895626e9c1b4f2c3b75fbf2850", "tree": "f99d7357cad3d11aad7870d5d528d8602ab0c65d", "parents": [ "cfa4d8cc56853ec945956d182ecb4c99102b110a" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Thu Nov 10 16:38:33 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:26 2012 -0800" }, "message": "PCI: Rework ASPM disable code\n\nRight now we forcibly clear ASPM state on all devices if the BIOS indicates\nthat the feature isn\u0027t supported. Based on the Microsoft presentation\n\"PCI Express In Depth for Windows Vista and Beyond\", I\u0027m starting to think\nthat this may be an error. The implication is that unless the platform\ngrants full control via _OSC, Windows will not touch any PCIe features -\nincluding ASPM. In that case clearing ASPM state would be an error unless\nthe platform has granted us that control.\n\nThis patch reworks the ASPM disabling code such that the actual clearing\nof state is triggered by a successful handoff of PCIe control to the OS.\nThe general ASPM code undergoes some changes in order to ensure that the\nability to clear the bits isn\u0027t overridden by ASPM having already been\ndisabled. Further, this theoretically now allows for situations where\nonly a subset of PCIe roots hand over control, leaving the others in the\nBIOS state.\n\nIt\u0027s difficult to know for sure that this is the right thing to do -\nthere\u0027s zero public documentation on the interaction between all of these\ncomponents. But enough vendors enable ASPM on platforms and then set this\nbit that it seems likely that they\u0027re expecting the OS to leave them alone.\n\nMeasured to save around 5W on an idle Thinkpad X220.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "379021d5c0899fcf9410cae4ca7a59a5a94ca769", "tree": "9c91ffb80fcb143b94c20922cb27d60d2c7e6654", "parents": [ "3e309cdf07c930f29a4e0f233e47d399bea34c68" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Oct 03 23:16:33 2011 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 14 09:05:31 2011 -0700" }, "message": "PCI / PM: Extend PME polling to all PCI devices\n\nThe land of PCI power management is a land of sorrow and ugliness,\nespecially in the area of signaling events by devices. There are\ndevices that set their PME Status bits, but don\u0027t really bother\nto send a PME message or assert PME#. There are hardware vendors\nwho don\u0027t connect PME# lines to the system core logic (they know\nwho they are). There are PCI Express Root Ports that don\u0027t bother\nto trigger interrupts when they receive PME messages from the devices\nbelow. There are ACPI BIOSes that forget to provide _PRW methods for\ndevices capable of signaling wakeup. Finally, there are BIOSes that\ndo provide _PRW methods for such devices, but then don\u0027t bother to\ncall Notify() for those devices from the corresponding _Lxx/_Exx\nGPE-handling methods. In all of these cases the kernel doesn\u0027t have\na chance to receive a proper notification that it should wake up a\ndevice, so devices stay in low-power states forever. Worse yet, in\nsome cases they continuously send PME Messages that are silently\nignored, because the kernel simply doesn\u0027t know that it should clear\nthe device\u0027s PME Status bit.\n\nThis problem was first observed for \"parallel\" (non-Express) PCI\ndevices on add-on cards and Matthew Garrett addressed it by adding\ncode that polls PME Status bits of such devices, if they are enabled\nto signal PME, to the kernel. Recently, however, it has turned out\nthat PCI Express devices are also affected by this issue and that it\nis not limited to add-on devices, so it seems necessary to extend\nthe PME polling to all PCI devices, including PCI Express and planar\nones. Still, it would be wasteful to poll the PME Status bits of\ndevices that are known to receive proper PME notifications, so make\nthe kernel (1) poll the PME Status bits of all PCI and PCIe devices\nenabled to signal PME and (2) disable the PME Status polling for\ndevices for which correct PME notifications are received.\n\nTested-by: Sarah Sharp \u003csarah.a.sharp@linux.intel.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f85f19de90a9997583bb26e6f1f9297a4e152c18", "tree": "2dfe61dab6c39ca202f114cb68c68978da1624e3", "parents": [ "b993fdbc7fe26f96b59003a3552c418a71aa0a9f", "7b87c9df5602efd6c7edeb291bbd104d49a6babf" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 29 23:35:05 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 29 23:35:05 2011 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: remove printks about disabled bridge windows\n PCI: fold pci_calc_resource_flags() into decode_bar()\n PCI: treat mem BAR type \"11\" (reserved) as 32-bit, not 64-bit, BAR\n PCI: correct pcie_set_readrq write size\n PCI: pciehp: change wait time for valid configuration access\n x86/PCI: Preserve existing pci\u003dbfsort whitelist for Dell systems\n PCI: ARI is a PCIe v2 feature\n x86/PCI: quirks: Use pci_dev-\u003erevision\n PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.\n PCI hotplug: cpqphp: use pci_dev-\u003evendor\n PCI hotplug: cpqphp: use pci_dev-\u003esubsystem_{vendor|device}\n x86/PCI: config space accessor functions should not ignore the segment argument\n PCI: Assign values to \u0027pci_obff_signal_type\u0027 enumeration constants\n x86/PCI: reduce severity of host bridge window conflict warnings\n PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI\n PCI: PCIe AER: add aer_recover_queue\n x86/PCI: select direct access mode for mmconfig option\n PCI hotplug: Rename is_ejectable which also exists in dock.c\n" }, { "commit": "0918472ceeffad234df5589e45b646a94476f835", "tree": "3afd05b7710a56056cdf8273545990949dd553fa", "parents": [ "0aba496fc820d7c36775f2fd0ef81994e1af67a8" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue May 17 16:08:37 2011 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 08:25:37 2011 -0700" }, "message": "PCI: PCIe AER: add aer_recover_queue\n\nIn addition to native PCIe AER, now APEI (ACPI Platform Error\nInterface) GHES (Generic Hardware Error Source) can be used to report\nPCIe AER errors too. To add support to APEI GHES PCIe AER recovery,\naer_recover_queue is added to export the recovery function in native\nPCIe AER driver.\n\nRecoverable PCIe AER errors are reported via NMI in APEI GHES. Then\nAPEI GHES uses irq_work to delay the error processing into an IRQ\nhandler. But PCIe AER recovery can be very time-consuming, so\naer_recover_queue, which can be used in IRQ handler, delays the real\nrecovery action into the process context, that is, work queue.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8072ba1ba7fe9f48ad9f424829863214484dfc2f", "tree": "9d27e70791e9d0a346e1e7dc0390a2cc5c986caa", "parents": [ "0c4986388a814ef4e85ea62d10b247dd7dc7783d" ], "author": { "name": "Michael Witten", "email": "mfwitten@gmail.com", "time": "Tue Jun 28 06:15:05 2011 +0000" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Wed Jun 29 14:24:14 2011 +0200" }, "message": "PCIe ASPM: forcedly -\u003e forcibly\n\nMerriam-Webster tells us that the word exists. However ...\n\n * Google suggests `forcibly\u0027 because it doesn\u0027t recognize `forcedly\u0027.\n * Google lists 494 thousand results for `forcedly\u0027.\n * Google lists 13.7 million results for `forcibly\u0027.\n * Linus\u0027s repo contains 1 occurrence of `forcedly\u0027 ( 0 after my change).\n * Linus\u0027s repo contains 60 occurrences of `forcibly\u0027 (61 after my change).\n\nSigned-off-by: Michael Witten \u003cmfwitten@gmail.com\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "cbfddd20937ed890ce7027fa08a7c84e977128cf", "tree": "43f271efc1fd1853778d6fc6f33190679957b3e7", "parents": [ "dc2c2c9dd513dec6c17df04e8abff795e20a5271" ], "author": { "name": "Chen Gong", "email": "gong.chen@linux.intel.com", "time": "Fri May 20 13:36:01 2011 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:17:14 2011 -0700" }, "message": "PCI: remove unused AER functions\n\nIn the commit 28eb5f2, aer_osc_setup is removed but corresponding\ndefiniton information in the aerdrv.h is missed.\n\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Chen Gong \u003cgong.chen@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9f728f53dd70396f3183d2f0861022259471824b", "tree": "e5591f2bec0d94c0eb753958c511a21b6bd00d8e", "parents": [ "a3170c1f924ce2565c4e160b9b095e65c03b2dc6" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu May 12 17:11:47 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:16:44 2011 -0700" }, "message": "PCI/e1000e: Add and use pci_disable_link_state_locked()\n\nNeed to use it in _e1000e_disable_aspm. This routine is used for error\nrecovery, where the pci_bus_sem is already held, and we don\u0027t want\npci_disable_link_state to try to take it again. So add a locked variant\nfor use in cases like this.\n\nFound lock up:\n\n[ 2374.654557] kworker/32:1 D ffff881027f6b0f0 0 6075 2 0x00000000\n[ 2374.654816] ffff88503f099a68 0000000000000046 ffff88503f098000 0000000000004000\n[ 2374.654837] 00000000001d1ec0 ffff88503f099fd8 00000000001d1ec0 ffff88503f099fd8\n[ 2374.654860] 0000000000004000 00000000001d1ec0 ffff88503dcc8000 ffff88503f090000\n[ 2374.654880] Call Trace:\n[ 2374.654898] [\u003cffffffff810b1302\u003e] ? __lock_acquired+0x3a/0x224\n[ 2374.654914] [\u003cffffffff81c2b59c\u003e] ? _raw_spin_unlock_irq+0x30/0x36\n[ 2374.654925] [\u003cffffffff810b069d\u003e] ? trace_hardirqs_on_caller+0x1f/0x178\n[ 2374.654936] [\u003cffffffff81c2ab24\u003e] rwsem_down_failed_common+0xd3/0x103\n[ 2374.654945] [\u003cffffffff810b158f\u003e] ? __lock_contended+0x3a/0x2a2\n[ 2374.654955] [\u003cffffffff81c2ab7b\u003e] rwsem_down_read_failed+0x12/0x14\n[ 2374.654967] [\u003cffffffff813371e4\u003e] call_rwsem_down_read_failed+0x14/0x30\n[ 2374.654981] [\u003cffffffff8135df20\u003e] ? pci_disable_link_state+0x5f/0xf5\n[ 2374.654990] [\u003cffffffff81c2a0e6\u003e] ? down_read+0x7e/0x91\n[ 2374.654999] [\u003cffffffff8135df20\u003e] ? pci_disable_link_state+0x5f/0xf5\n[ 2374.655008] [\u003cffffffff8135df20\u003e] pci_disable_link_state+0x5f/0xf5\n[ 2374.655024] [\u003cffffffff81661796\u003e] e1000e_disable_aspm+0x55/0x5a\n[ 2374.655037] [\u003cffffffff816677eb\u003e] e1000_io_slot_reset+0x59/0xea\n[ 2374.655048] [\u003cffffffff8135fe0d\u003e] ? report_mmio_enabled+0x5d/0x5d\n[ 2374.655057] [\u003cffffffff8135fe3b\u003e] report_slot_reset+0x2e/0x5d\n[ 2374.655072] [\u003cffffffff8135369e\u003e] pci_walk_bus+0x8a/0xb7\n[ 2374.655081] [\u003cffffffff8135fe0d\u003e] ? report_mmio_enabled+0x5d/0x5d\n[ 2374.655091] [\u003cffffffff813603be\u003e] broadcast_error_message+0xa4/0xb2\n[ 2374.655101] [\u003cffffffff81352c71\u003e] ? pci_bus_read_config_dword+0x72/0x80\n[ 2374.655110] [\u003cffffffff813606df\u003e] do_recovery+0x9e/0xf9\n[ 2374.655120] [\u003cffffffff81360786\u003e] handle_error_source+0x4c/0x51\n[ 2374.655129] [\u003cffffffff81360974\u003e] aer_isr_one_error+0x1e9/0x21a\n[ 2374.655138] [\u003cffffffff81360a6c\u003e] aer_isr+0xc7/0xcc\n[ 2374.655147] [\u003cffffffff813609a5\u003e] ? aer_isr_one_error+0x21a/0x21a\n[ 2374.655159] [\u003cffffffff81096d9f\u003e] process_one_work+0x237/0x3ec\n[ 2374.655168] [\u003cffffffff81096d10\u003e] ? process_one_work+0x1a8/0x3ec\n[ 2374.655178] [\u003cffffffff8109728d\u003e] worker_thread+0x17c/0x240\n[ 2374.655186] [\u003cffffffff810b0803\u003e] ? trace_hardirqs_on+0xd/0xf\n[ 2374.655196] [\u003cffffffff81097111\u003e] ? manage_workers+0xab/0xab\n[ 2374.655209] [\u003cffffffff8109c8ed\u003e] kthread+0xa0/0xa8\n[ 2374.655223] [\u003cffffffff81c332d4\u003e] kernel_thread_helper+0x4/0x10\n[ 2374.655232] [\u003cffffffff81c2b880\u003e] ? retint_restore_args+0xe/0xe\n[ 2374.655243] [\u003cffffffff8109c84d\u003e] ? __init_kthread_worker+0x5b/0x5b\n[ 2374.655252] [\u003cffffffff81c332d0\u003e] ? gs_change+0xb/0xb\n\nwhen aer happens,\npci_walk_bus already have down_read(\u0026pci_bus_sem)...\nthen report_slot_reset\n \u003d\u003d\u003e e1000_io_slot_reset\n \u003d\u003d\u003e e1000e_disable_aspm\n \u003d\u003d\u003e pci_disable_link_state...\n\nWe can not use pci_disable_link_state, and it will try to hold pci_bus_sem again.\n\nTry to have __pci_disable_link_state that will not need to hold pci_bus_sem.\n\n-v2: change name to pci_disable_link_state_locked() according to Jesse.\n\n[jbarnes: make sure new function is exported for modules]\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "40294d8f14384780a61a2dea8c92a231176ae301", "tree": "3f77092858a965b10827bd10b2a9171489a6f343", "parents": [ "0e8ede5351b53610363215f750e576ca1db1d0cd" ], "author": { "name": "Wanlong Gao", "email": "wanlong.gao@gmail.com", "time": "Mon Apr 04 17:12:59 2011 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 10 15:43:30 2011 -0700" }, "message": "PCI: Fix uninitialized variable bug in AER injection code\n\nIf it was preempted, and the variable aer_mask_override is changed\nafter the spin_unlock_irqrestore it will write an uninitialized\nvariable by the pci_write_config_dword() function.\n\nSigned-off-by: Wanlong Gao \u003cwanlong.gao@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3504e47ffca5ed3f9e2cc7d37b428fbf1e00ad1b", "tree": "55e7d8afa09731383560eca6dd5f0ef5e026ef5e", "parents": [ "2f666bcf757cb72549f360ef6da02f03620a48b6" ], "author": { "name": "Alex Williamson", "email": "alex.williamson@redhat.com", "time": "Thu Mar 10 11:54:16 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 10 15:43:28 2011 -0700" }, "message": "PCI: Enable ASPM state clearing regardless of policy\n\nCommit 2f671e2d allowed us to clear ASPM state when the FADT\ntells us it isn\u0027t supported, but we don\u0027t put this into effect\nif the aspm_policy is set to POLICY_POWERSAVE. Enable the\nstate to be cleared regardless of policy.\n\nSigned-off-by: Alex Williamson \u003calex.williamson@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5aafdea448fb86412a6f8e46df518c1545d32436", "tree": "c8e7b57382628873a26b15fbda1f41b527ad1c0b", "parents": [ "56a9ccb7ba5ffd5f285e3a9628cb446192c8639c", "eca67315e0e0d5fd91264d79c88694006dbc7d31" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 25 21:01:43 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 25 21:01:43 2011 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: Disable ASPM when _OSC control is not granted for PCIe services\n PCI: Changing ASPM policy, via /sys, to POWERSAVE could cause NMIs\n PCI: PCIe links may not get configured for ASPM under POWERSAVE mode\n PCI/ACPI: Report ASPM support to BIOS if not disabled from command line\n" }, { "commit": "02e2407858fd62053bf60349c0e72cd1c7a4a60e", "tree": "0ebdbddc97d3abbc675916010e7771065b70c137", "parents": [ "96e1c408ea8a556c5b51e0e7d56bd2afbfbf5fe9", "6447f55da90b77faec1697d499ed7986bb4f6de6" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Mar 23 02:34:54 2011 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Mar 23 02:34:54 2011 -0400" }, "message": "Merge branch \u0027linus\u0027 into release\n\nConflicts:\n\tarch/x86/kernel/acpi/sleep.c\n\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "c413d7682020a127f54744a1b30f597692aea1fd", "tree": "b495af23b2f81b6ab0080925aa988ea9a8068e4e", "parents": [ "b64a44146540a4761bb1cf8047fffd9dbf0c3090" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Mon Feb 21 13:54:43 2011 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Mon Mar 21 22:59:08 2011 -0400" }, "message": "ACPI, APEI, Add PCIe AER error information printing support\n\nThe AER error information printing support is implemented in\ndrivers/pci/pcie/aer/aer_print.c. So some string constants, functions\nand macros definitions can be re-used without being exported.\n\nThe original PCIe AER error information printing function is not\nre-used directly because the overall format is quite different. And\nchanging the original printing format may make some original users\u0027\nscripts broken.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nCC: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCC: Zhang Yanmin \u003cyanmin.zhang@intel.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "b64a44146540a4761bb1cf8047fffd9dbf0c3090", "tree": "2a6fd718db4c5885eab7b41e1c8139f7b259cf00", "parents": [ "885b976fada5bc6595a9fd3e67e3cb1a3d11f50b" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Mon Feb 21 13:54:42 2011 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Mon Mar 21 22:59:08 2011 -0400" }, "message": "PCIe, AER, use pre-generated prefix in error information printing\n\nWhen printing PCIe AER error information, each line is prefixed with\nPCIe device and driver information. In original implementation, the\nprefix is generated when each line is printed. In fact, all lines\nshare the same prefix. So this patch pre-generated the prefix, and\nuse that one when each line is printed.\n\nIn addition to common prefix can be pre-generated, the trailing white\nspaces in string constants and NULLs in char * array constants can be\nremoved too. These can reduce the object file size further.\n\nThe size of object file before and after changing is as follow:\n\n text data bss dec\nbefore: 3038 0 0 3038\nafter: 2118 0 0 2118\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nCC: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCC: Zhang Yanmin \u003cyanmin.zhang@intel.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "eca67315e0e0d5fd91264d79c88694006dbc7d31", "tree": "4a68e41c0ea71cbbff8d72827d6e39f8f222c0cf", "parents": [ "bbfa306a1e5d9618231aa0de3d52a8eb1219d0c3" ], "author": { "name": "Naga Chumbalkar", "email": "nagananda.chumbalkar@hp.com", "time": "Mon Mar 21 03:29:20 2011 +0000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Mar 21 09:41:08 2011 -0700" }, "message": "PCI: Disable ASPM when _OSC control is not granted for PCIe services\n\nv3 -\u003e v2: Added text to describe the problem\nv2 -\u003e v1: Split this patch from v1\nv1\t: Part of: http://marc.info/?l\u003dlinux-pci\u0026m\u003d130042212003242\u0026w\u003d2\n\nDisable ASPM when no _OSC control for PCIe services is granted\nby the BIOS. This is to protect systems with a buggy BIOS that\ndid not set the ACPI FADT \"ASPM Controls\" bit even though the\nunderlying HW can\u0027t do ASPM.\n\nTo turn \"on\" ASPM the minimum the BIOS needs to do:\n1. Clear the ACPI FADT \"ASPM Controls\" bit.\n2. Support _OSC appropriately\n\nThere is no _OSC Control bit for ASPM. However, we expect the BIOS to\nsupport _OSC for a Root Bridge that originates a PCIe hierarchy. If this\nis not the case - we are better off not enabling ASPM on that server.\n\nCommit 852972acff8f10f3a15679be2059bb94916cba5d (ACPI: Disable ASPM if the\nPlatform won\u0027t provide _OSC control for PCIe) describes the above scenario.\nTo quote verbatim from there:\n[The PCI SIG documentation for the _OSC OS/firmware handshaking interface\nstates:\n\n\"If the _OSC control method is absent from the scope of a host bridge\ndevice, then the operating system must not enable or attempt to use any\nfeatures defined in this section for the hierarchy originated by the host\nbridge.\"\n\nThe obvious interpretation of this is that the OS should not attempt to use\nPCIe hotplug, PME or AER - however, the specification also notes that an\n_OSC method is *required* for PCIe hierarchies, and experimental validation\nwith An Alternative OS indicates that it doesn\u0027t use any PCIe functionality\nif the _OSC method is missing. That arguably means we shouldn\u0027t be using\nMSI or extended config space, but right now our problems seem to be limited\nto vendors being surprised when ASPM gets enabled on machines when other\nOSs refuse to do so. So, for now, let\u0027s just disable ASPM if the _OSC\nmethod doesn\u0027t exist or refuses to hand over PCIe capability control.]\n\nSigned-off-by: Naga Chumbalkar \u003cnagananda.chumbalkar@hp.com\u003e\nCc: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nCc: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bbfa306a1e5d9618231aa0de3d52a8eb1219d0c3", "tree": "8228863e124a9733eefb30845e6a2d01617de69e", "parents": [ "1a680b7c325882188865f05b9a88d32f75f26495" ], "author": { "name": "Naga Chumbalkar", "email": "nagananda.chumbalkar@hp.com", "time": "Mon Mar 21 03:29:14 2011 +0000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Mar 21 09:40:57 2011 -0700" }, "message": "PCI: Changing ASPM policy, via /sys, to POWERSAVE could cause NMIs\n\nv3 -\u003e v2: Modified the text that describes the problem\nv2 -\u003e v1: Returned -EPERM\nv1 : http://marc.info/?l\u003dlinux-pci\u0026m\u003d130013194803727\u0026w\u003d2\n\nFor servers whose hardware cannot handle ASPM the BIOS ought to set the\nFADT bit shown below:\nIn Sec 5.2.9.3 (IA-PC Boot Arch. Flags) of ACPI4.0a Specification, please\nsee Table 5-11:\nPCIe ASPM Controls: If set, indicates to OSPM that it must not enable\nOPSM ASPM control on this platform.\n\nHowever there are shipping servers whose BIOS did not set this bit. (An\nexample is the HP ProLiant DL385 G6. A Maintenance BIOS will fix that).\nFor such servers even if a call is made via pci_no_aspm(), based on _OSC\nsupport in the BIOS, it may be too late because the ASPM code may have\nalready allocated and filled its \"link_list\".\n\nSo if a user sets the ASPM \"policy\" to \"powersave\" via /sys then\npcie_aspm_set_policy() will run through the \"link_list\" and re-configure\nASPM policy on devices that advertise ASPM L0s/L1 capability:\n# echo powersave \u003e /sys/module/pcie_aspm/parameters/policy\n# cat /sys/module/pcie_aspm/parameters/policy\ndefault performance [powersave]\n\nThat can cause NMIs since the hardware doesn\u0027t play well with ASPM:\n[ 1651.906015] NMI: PCI system error (SERR) for reason b1 on CPU 0.\n[ 1651.906015] Dazed and confused, but trying to continue\n\nIdeally, the BIOS should have set that FADT bit in the first place but we\ncould be more robust - especially given the fact that Windows doesn\u0027t\ncause NMIs in the above scenario.\n\nThere should be a sanity check to not allow a user to modify ASPM policy\nwhen aspm_disabled is set.\n\nSigned-off-by: Naga Chumbalkar \u003cnagananda.chumbalkar@hp.com\u003e\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nCc: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1a680b7c325882188865f05b9a88d32f75f26495", "tree": "eb3844655f9ff01630157e4b2c039759970b1a94", "parents": [ "8b8bae901ce23addbdcdb54fa1696fb2d049feb5" ], "author": { "name": "Naga Chumbalkar", "email": "nagananda.chumbalkar@hp.com", "time": "Mon Mar 21 03:29:08 2011 +0000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Mar 21 09:40:43 2011 -0700" }, "message": "PCI: PCIe links may not get configured for ASPM under POWERSAVE mode\n\nv3 -\u003e v2: Moved ASPM enabling logic to pci_set_power_state()\nv2 -\u003e v1: Preserved the logic in pci_raw_set_power_state()\n\t: Added ASPM enabling logic after scanning Root Bridge\n\t: http://marc.info/?l\u003dlinux-pci\u0026m\u003d130046996216391\u0026w\u003d2\nv1\t: http://marc.info/?l\u003dlinux-pci\u0026m\u003d130013164703283\u0026w\u003d2\n\nThe assumption made in commit 41cd766b065970ff6f6c89dd1cf55fa706c84a3d\n(PCI: Don\u0027t enable aspm before drivers have had a chance to veto it) that\npci_enable_device() will result in re-configuring ASPM when aspm_policy is\nPOWERSAVE is no longer valid. This is due to commit\n97c145f7c87453cec90e91238fba5fe2c1561b32 (PCI: read current power state\nat enable time) which resets dev-\u003ecurrent_state to D0. Due to this the\ncall to pcie_aspm_pm_state_change() is never made. Note the equality check\n(below) that returns early:\n./drivers/pci/pci.c: pci_raw_set_pci_power_state()\n546 /* Check if we\u0027re already there */\n547 if (dev-\u003ecurrent_state \u003d\u003d state)\n548 return 0;\n\nTherefore OSPM never configures the PCIe links for ASPM to turn them \"on\".\n\nFix it by configuring ASPM from the pci_enable_device() code path. This\nalso allows a driver such as the e1000e networking driver a chance to\ndisable ASPM (L0s, L1), if need be, prior to enabling the device. A\ndriver may perform this action if the device is known to mis-behave\nwrt ASPM.\n\nSigned-off-by: Naga Chumbalkar \u003cnagananda.chumbalkar@hp.com\u003e\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nCc: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8b8bae901ce23addbdcdb54fa1696fb2d049feb5", "tree": "4b95885dc5ba5b6105231289501e83ef429987c2", "parents": [ "a44f99c7efdb88fa41128065c9a9445c19894e34" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Mar 05 13:21:51 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Mar 21 09:38:02 2011 -0700" }, "message": "PCI/ACPI: Report ASPM support to BIOS if not disabled from command line\n\nWe need to distinguish the situation in which ASPM support is\ndisabled from the command line or through .config from the situation\nin which it is disabled, because the hardware or BIOS can\u0027t handle\nit. In the former case we should not report ASPM support to the BIOS\nthrough ACPI _OSC, but in the latter case we should do that.\n\nIntroduce pcie_aspm_support_enabled() that can be used by\nacpi_pci_root_add() to determine whether or not it should report ASPM\nsupport to the BIOS through _OSC.\n\nCc: stable@kernel.org\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d29722\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d20232\nReported-and-tested-by: Ortwin Glück \u003codi@odi.ch\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "457d9d088b026e26dbab98cad9d299c1faf4c343", "tree": "654406ce3724d90fe784446ef38c12605adb692e", "parents": [ "3449248c8731e8474980856d76bbf9bac9b0682f" ], "author": { "name": "Prarit Bhargava", "email": "prarit@redhat.com", "time": "Tue Jan 11 15:34:35 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 04 10:41:02 2011 -0800" }, "message": "PCI: aer-inject: Override PCIe AER Mask Registers\n\nI have several systems which have the same problem: The PCIe AER\ncorrected and uncorrected masks have all the error bits set. This\nresults in the inablility to test with the aer_inject module \u0026 utility\non those systems.\n\nAdd the \u0027aer_mask_override\u0027 module parameter which will override the\ncorrected or uncorrected masks for a PCI device. The mask will have the\nbit corresponding to the status passed into the aer_inject() function.\n\nAfter this patch it is possible to successfully use the aer_inject\nutility on those PCI slots.\n\nSuccessfully tested by me on a Dell and Intel whitebox which exhibited\nthe mask problem.\n\nSigned-off-by: Prarit Bhargava \u003cprarit@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6a108a14fa356ef607be308b68337939e56ea94e", "tree": "1bf260572bd8f95ed867307a2bcf5d881c8ae4a6", "parents": [ "12fcdba1b7ae8b25696433f420b775aeb556d89b" ], "author": { "name": "David Rientjes", "email": "rientjes@google.com", "time": "Thu Jan 20 14:44:16 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 20 17:02:05 2011 -0800" }, "message": "kconfig: rename CONFIG_EMBEDDED to CONFIG_EXPERT\n\nThe meaning of CONFIG_EMBEDDED has long since been obsoleted; the option\nis used to configure any non-standard kernel with a much larger scope than\nonly small devices.\n\nThis patch renames the option to CONFIG_EXPERT in init/Kconfig and fixes\nreferences to the option throughout the kernel. A new CONFIG_EMBEDDED\noption is added that automatically selects CONFIG_EXPERT when enabled and\ncan be used in the future to isolate options that should only be\nconsidered for embedded systems (RISC architectures, SLOB, etc).\n\nCalling the option \"EXPERT\" more accurately represents its intention: only\nexpert users who understand the impact of the configuration changes they\nare making should enable it.\n\nReviewed-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nAcked-by: David Woodhouse \u003cdavid.woodhouse@intel.com\u003e\nSigned-off-by: David Rientjes \u003crientjes@google.com\u003e\nCc: Greg KH \u003cgregkh@suse.de\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Jens Axboe \u003caxboe@kernel.dk\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Robin Holt \u003cholt@sgi.com\u003e\nCc: \u003clinux-arch@vger.kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "0f953bf6b4efa0daddb7c418130a9bd3ee97f7ed", "tree": "4a24901b0ff701e80787e39d87603bdd4b762876", "parents": [ "b6e335aeeb114dccb07eaa09e8b62ff9510cf745" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Dec 29 13:22:08 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:55:43 2011 -0800" }, "message": "PCI/PM: Report wakeup events before resuming devices\n\nMake wakeup events be reported by the PCI subsystem before attempting to\nresume devices or queuing up runtime resume requests for them, because\nwakeup events should be reported as soon as they have been detected.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "415e12b2379239973feab91850b0dce985c6058a", "tree": "aa79c7a87fd30ac13ae3fd146aad5a44e854c4bc", "parents": [ "6e8af08dfa40b747002207d3ce8e8b43a050d99f" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Jan 07 00:55:09 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 14 08:55:41 2011 -0800" }, "message": "PCI/ACPI: Request _OSC control once for each root bridge (v3)\n\nMove the evaluation of acpi_pci_osc_control_set() (to request control of\nPCI Express native features) into acpi_pci_root_add() to avoid calling\nit many times for the same root complex with the same arguments.\nAdditionally, check if all of the requisite _OSC support bits are set\nbefore calling acpi_pci_osc_control_set() for a given root complex.\n\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d20232\nReported-by: Ozan Caglayan \u003cozan@pardus.org.tr\u003e\nTested-by: Ozan Caglayan \u003cozan@pardus.org.tr\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fe31e69740eddc7316071ed5165fed6703c8cd12", "tree": "b58f193d7176bfe19ae975fec7ff42d7e242e359", "parents": [ "99a0fadf561e1f553c08f0a29f8b2578f55dd5f0" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sun Dec 19 15:57:16 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Dec 23 12:54:03 2010 -0800" }, "message": "PCI/PCIe: Clear Root PME Status bits early during system resume\n\nI noticed that PCI Express PMEs don\u0027t work on my Toshiba Portege R500\nafter the system has been woken up from a sleep state by a PME\n(through Wake-on-LAN). After some investigation it turned out that\nthe BIOS didn\u0027t clear the Root PME Status bit in the root port that\nreceived the wakeup PME and since the Requester ID was also set in\nthe port\u0027s Root Status register, any subsequent PMEs didn\u0027t trigger\ninterrupts.\n\nThis problem can be avoided by clearing the Root PME Status bits in\nall PCI Express root ports during early resume. For this purpose,\nadd an early resume routine to the PCIe port driver and make this\ndriver be always registered, even if pci_ports_disable is set (in\nwhich case the driver\u0027s only function is to provide the early\nresume callback).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2f671e2dbff6eb5ef4e2600adbec550c13b8fe72", "tree": "fb5debb042218dcf1cbdf11eb4d8d603208c219f", "parents": [ "8d805286968811223cca002134ba3d81244d5313" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Mon Dec 06 14:00:56 2010 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Dec 23 12:53:08 2010 -0800" }, "message": "PCI: Disable ASPM if BIOS asks us to\n\nWe currently refuse to touch the ASPM registers if the BIOS tells us that\nASPM isn\u0027t supported. This can cause problems if the BIOS has (for any\nreason) enabled ASPM on some devices anyway. Change the code such that we\nexplicitly clear ASPM if the FADT indicates that ASPM isn\u0027t supported,\nand make sure we tidy up appropriately on device removal in order to deal\nwith the hotplug case. If ASPM is disabled because the BIOS doesn\u0027t hand\nover control then we won\u0027t touch the registers.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e9f29c9a56ca06d0effa557823a737cbe7ec09f7", "tree": "c331c4aa741a8f384ee13d0b08bd340c23164b16", "parents": [ "800416f799e0723635ac2d720ad4449917a1481c", "1af3c2e45e7a641e774bbb84fa428f2f0bf2d9c9" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Oct 28 11:59:52 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Oct 28 11:59:52 2010 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (27 commits)\n x86: allocate space within a region top-down\n x86: update iomem_resource end based on CPU physical address capabilities\n x86/PCI: allocate space from the end of a region, not the beginning\n PCI: allocate bus resources from the top down\n resources: support allocating space within a region from the top down\n resources: handle overflow when aligning start of available area\n resources: ensure callback doesn\u0027t allocate outside available space\n resources: factor out resource_clip() to simplify find_resource()\n resources: add a default alignf to simplify find_resource()\n x86/PCI: MMCONFIG: fix region end calculation\n PCI: Add support for polling PME state on suspended legacy PCI devices\n PCI: Export some PCI PM functionality\n PCI: fix message typo\n PCI: log vendor/device ID always\n PCI: update Intel chipset names and defines\n PCI: use new ccflags variable in Makefile\n PCI: add PCI_MSIX_TABLE/PBA defines\n PCI: add PCI vendor id for STmicroelectronics\n x86/PCI: irq and pci_ids patch for Intel Patsburg DeviceIDs\n PCI: OLPC: Only enable PCI configuration type override on XO-1\n ...\n" }, { "commit": "b22c3d82757109fa107ce17ba9484d45273eed05", "tree": "a8652b72298487d7938baec4836abc44dee22dbc", "parents": [ "42b219322a97ccef347388b233aceaafe3fa517d" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Sep 20 18:50:00 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 15 13:09:50 2010 -0700" }, "message": "PCI/PCIe/AER: Disable native AER service if BIOS has precedence\n\nThere is a design issue related to PCIe AER and _OSC that the BIOS\nmay be asked to grant control of the AER service even if some\nHardware Error Source Table (HEST) entries contain information\nmeaning that the BIOS really should control it. Namely,\npcie_port_acpi_setup() calls pcie_aer_get_firmware_first() that\ndetermines whether or not the AER service should be controlled by\nthe BIOS on the basis of the HEST information for the given PCIe\nport. The BIOS is asked to grant control of the AER service for\na PCIe Root Complex if pcie_aer_get_firmware_first() returns \u0027false\u0027\nfor at least one root port in that complex, even if all of the other\nroot ports\u0027 HEST entries have the FIRMWARE_FIRST flag set (and none\nof them has the GLOBAL flag set). However, if the AER service is\ncontrolled by the kernel, that may interfere with the BIOS\u0027 handling\nof the error sources having the FIRMWARE_FIRST flag. Moreover,\nthere may be PCIe endpoints that have the FIRMWARE_FIRST flag set in\nHEST and are attached to the root ports in question, in which case it\nalso may be unsafe to ask the BIOS for control of the AER service.\n\nFor this reason, introduce a function checking if there\u0027s at least\none PCIe-related HEST entry with the FIRMWARE_FIRST flag set and\ndisable the native AER service altogether if this function returns\n\u0027true\u0027.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "50c1126ee1990920705a067a6f3f9bb892369b08", "tree": "fc03a50f887a8bd72329e49f01b347b9df5b23a2", "parents": [ "991f739544a0923b70fb69b115edb880ff9fcc4a" ], "author": { "name": "Bill Pemberton", "email": "wfp5p@virginia.edu", "time": "Tue Aug 03 15:18:43 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 15 13:09:48 2010 -0700" }, "message": "PCI: aerdrv: fix uninitialized variable warning\n\nquiet the warning about use of uninitialized e_src in\naer_isr() e_src is initialized by get_e_source()\n\nSigned-off-by: Bill Pemberton \u003cwfp5p@virginia.edu\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6038f373a3dc1f1c26496e60b6c40b164716f07e", "tree": "a0d3bbd026eea41b9fc36b8c722cbaf56cd9f825", "parents": [ "1ec5584e3edf9c4bf2c88c846534d19cf986ba11" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sun Aug 15 18:52:59 2010 +0200" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Fri Oct 15 15:53:27 2010 +0200" }, "message": "llseek: automatically add .llseek fop\n\nAll file_operations should get a .llseek operation so we can make\nnonseekable_open the default for future file operations without a\n.llseek pointer.\n\nThe three cases that we can automatically detect are no_llseek, seq_lseek\nand default_llseek. For cases where we can we can automatically prove that\nthe file offset is always ignored, we use noop_llseek, which maintains\nthe current behavior of not returning an error from a seek.\n\nNew drivers should normally not use noop_llseek but instead use no_llseek\nand call nonseekable_open at open time. Existing drivers can be converted\nto do the same when the maintainer knows for certain that no user code\nrelies on calling seek on the device file.\n\nThe generated code is often incorrectly indented and right now contains\ncomments that clarify for each added line why a specific variant was\nchosen. In the version that gets submitted upstream, the comments will\nbe gone and I will manually fix the indentation, because there does not\nseem to be a way to do that using coccinelle.\n\nSome amount of new code is currently sitting in linux-next that should get\nthe same modifications, which I will do at the end of the merge window.\n\nMany thanks to Julia Lawall for helping me learn to write a semantic\npatch that does all this.\n\n\u003d\u003d\u003d\u003d\u003d begin semantic patch \u003d\u003d\u003d\u003d\u003d\n// This adds an llseek\u003d method to all file operations,\n// as a preparation for making no_llseek the default.\n//\n// The rules are\n// - use no_llseek explicitly if we do nonseekable_open\n// - use seq_lseek for sequential files\n// - use default_llseek if we know we access f_pos\n// - use noop_llseek if we know we don\u0027t access f_pos,\n// but we still want to allow users to call lseek\n//\n@ open1 exists @\nidentifier nested_open;\n@@\nnested_open(...)\n{\n\u003c+...\nnonseekable_open(...)\n...+\u003e\n}\n\n@ open exists@\nidentifier open_f;\nidentifier i, f;\nidentifier open1.nested_open;\n@@\nint open_f(struct inode *i, struct file *f)\n{\n\u003c+...\n(\nnonseekable_open(...)\n|\nnested_open(...)\n)\n...+\u003e\n}\n\n@ read disable optional_qualifier exists @\nidentifier read_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\nexpression E;\nidentifier func;\n@@\nssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)\n{\n\u003c+...\n(\n *off \u003d E\n|\n *off +\u003d E\n|\n func(..., off, ...)\n|\n E \u003d *off\n)\n...+\u003e\n}\n\n@ read_no_fpos disable optional_qualifier exists @\nidentifier read_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\n@@\nssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)\n{\n... when !\u003d off\n}\n\n@ write @\nidentifier write_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\nexpression E;\nidentifier func;\n@@\nssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)\n{\n\u003c+...\n(\n *off \u003d E\n|\n *off +\u003d E\n|\n func(..., off, ...)\n|\n E \u003d *off\n)\n...+\u003e\n}\n\n@ write_no_fpos @\nidentifier write_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\n@@\nssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)\n{\n... when !\u003d off\n}\n\n@ fops0 @\nidentifier fops;\n@@\nstruct file_operations fops \u003d {\n ...\n};\n\n@ has_llseek depends on fops0 @\nidentifier fops0.fops;\nidentifier llseek_f;\n@@\nstruct file_operations fops \u003d {\n...\n .llseek \u003d llseek_f,\n...\n};\n\n@ has_read depends on fops0 @\nidentifier fops0.fops;\nidentifier read_f;\n@@\nstruct file_operations fops \u003d {\n...\n .read \u003d read_f,\n...\n};\n\n@ has_write depends on fops0 @\nidentifier fops0.fops;\nidentifier write_f;\n@@\nstruct file_operations fops \u003d {\n...\n .write \u003d write_f,\n...\n};\n\n@ has_open depends on fops0 @\nidentifier fops0.fops;\nidentifier open_f;\n@@\nstruct file_operations fops \u003d {\n...\n .open \u003d open_f,\n...\n};\n\n// use no_llseek if we call nonseekable_open\n////////////////////////////////////////////\n@ nonseekable1 depends on !has_llseek \u0026\u0026 has_open @\nidentifier fops0.fops;\nidentifier nso ~\u003d \"nonseekable_open\";\n@@\nstruct file_operations fops \u003d {\n... .open \u003d nso, ...\n+.llseek \u003d no_llseek, /* nonseekable */\n};\n\n@ nonseekable2 depends on !has_llseek @\nidentifier fops0.fops;\nidentifier open.open_f;\n@@\nstruct file_operations fops \u003d {\n... .open \u003d open_f, ...\n+.llseek \u003d no_llseek, /* open uses nonseekable */\n};\n\n// use seq_lseek for sequential files\n/////////////////////////////////////\n@ seq depends on !has_llseek @\nidentifier fops0.fops;\nidentifier sr ~\u003d \"seq_read\";\n@@\nstruct file_operations fops \u003d {\n... .read \u003d sr, ...\n+.llseek \u003d seq_lseek, /* we have seq_read */\n};\n\n// use default_llseek if there is a readdir\n///////////////////////////////////////////\n@ fops1 depends on !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier readdir_e;\n@@\n// any other fop is used that changes pos\nstruct file_operations fops \u003d {\n... .readdir \u003d readdir_e, ...\n+.llseek \u003d default_llseek, /* readdir is present */\n};\n\n// use default_llseek if at least one of read/write touches f_pos\n/////////////////////////////////////////////////////////////////\n@ fops2 depends on !fops1 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier read.read_f;\n@@\n// read fops use offset\nstruct file_operations fops \u003d {\n... .read \u003d read_f, ...\n+.llseek \u003d default_llseek, /* read accesses f_pos */\n};\n\n@ fops3 depends on !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier write.write_f;\n@@\n// write fops use offset\nstruct file_operations fops \u003d {\n... .write \u003d write_f, ...\n+\t.llseek \u003d default_llseek, /* write accesses f_pos */\n};\n\n// Use noop_llseek if neither read nor write accesses f_pos\n///////////////////////////////////////////////////////////\n\n@ fops4 depends on !fops1 \u0026\u0026 !fops2 \u0026\u0026 !fops3 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier read_no_fpos.read_f;\nidentifier write_no_fpos.write_f;\n@@\n// write fops use offset\nstruct file_operations fops \u003d {\n...\n .write \u003d write_f,\n .read \u003d read_f,\n...\n+.llseek \u003d noop_llseek, /* read and write both use no f_pos */\n};\n\n@ depends on has_write \u0026\u0026 !has_read \u0026\u0026 !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier write_no_fpos.write_f;\n@@\nstruct file_operations fops \u003d {\n... .write \u003d write_f, ...\n+.llseek \u003d noop_llseek, /* write uses no f_pos */\n};\n\n@ depends on has_read \u0026\u0026 !has_write \u0026\u0026 !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier read_no_fpos.read_f;\n@@\nstruct file_operations fops \u003d {\n... .read \u003d read_f, ...\n+.llseek \u003d noop_llseek, /* read uses no f_pos */\n};\n\n@ depends on !has_read \u0026\u0026 !has_write \u0026\u0026 !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\n@@\nstruct file_operations fops \u003d {\n...\n+.llseek \u003d noop_llseek, /* no read or write fn */\n};\n\u003d\u003d\u003d\u003d\u003d End semantic patch \u003d\u003d\u003d\u003d\u003d\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Julia Lawall \u003cjulia@diku.dk\u003e\nCc: Christoph Hellwig \u003chch@infradead.org\u003e\n" }, { "commit": "a9d2a6df11f5b9dc19ad4147374e8b67c4438158", "tree": "44595bbe685feb81e3730895e1edfbc8e3a9572a", "parents": [ "271fb719cc472af3b1e96d8c527bb0da7060a172" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Sat Aug 21 01:59:10 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 24 13:47:49 2010 -0700" }, "message": "PCI: PCIe: Remove the port driver module exit routine\n\nThe PCIe port driver\u0027s module exit routine is never used, so drop it.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "271fb719cc472af3b1e96d8c527bb0da7060a172", "tree": "7ca665285206b6868040f41bba7693d2de157c0a", "parents": [ "2bd50dd800b52245294cfceb56be62020cdc7515" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Aug 21 01:58:22 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 24 13:47:48 2010 -0700" }, "message": "PCI: PCIe: Move PCIe PME code to the pcie directory\n\nThe PCIe PME code only consists of one file, so it doesn\u0027t need to\noccupy its own directory. Move it to drivers/pci/pcie/pme.c and\nremove the contents of drivers/pci/pcie/pme .\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2bd50dd800b52245294cfceb56be62020cdc7515", "tree": "ffefb8e50f9e454f332f318c415085ca2911991b", "parents": [ "28eb5f274a305bf3a13b2c80c4804d4515d05c64" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Aug 21 01:57:39 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 24 13:47:47 2010 -0700" }, "message": "PCI: PCIe: Disable PCIe port services during port initialization\n\nIn principle PCIe port services may be enabled by the BIOS, so it\u0027s\nbetter to disable them during port initialization to avoid spurious\nevents from being generated.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28eb5f274a305bf3a13b2c80c4804d4515d05c64", "tree": "c878c8a90a8f8e59b90460eb2f47bbbddfbd5483", "parents": [ "75fb60f26befb59dbfa05cb122972642b7bdd219" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Aug 21 22:02:38 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 24 13:47:33 2010 -0700" }, "message": "PCI: PCIe: Ask BIOS for control of all native services at once\n\nAfter commit 852972acff8f10f3a15679be2059bb94916cba5d (ACPI: Disable\nASPM if the platform won\u0027t provide _OSC control for PCIe) control of\nthe PCIe Capability Structure is unconditionally requested by\nacpi_pci_root_add(), which in principle may cause problems to\nhappen in two ways. First, the BIOS may refuse to give control of\nthe PCIe Capability Structure if it is not asked for any of the\n_OSC features depending on it at the same time. Second, the BIOS may\nassume that control of the _OSC features depending on the PCIe\nCapability Structure will be requested in the future and may behave\nincorrectly if that doesn\u0027t happen. For this reason, control of\nthe PCIe Capability Structure should always be requested along with\ncontrol of any other _OSC features that may depend on it (ie. PCIe\nnative PME, PCIe native hot-plug, PCIe AER).\n\nRework the PCIe port driver so that (1) it checks which native PCIe\nport services can be enabled, according to the BIOS, and (2) it\nrequests control of all these services simultaneously. In\nparticular, this causes pcie_portdrv_probe() to fail if the BIOS\nrefuses to grant control of the PCIe Capability Structure, which\nmeans that no native PCIe port services can be enabled for the PCIe\nRoot Complex the given port belongs to. If that happens, ASPM is\ndisabled to avoid problems with mishandling it by the part of the\nPCIe hierarchy for which control of the PCIe Capability Structure\nhas not been received.\n\nMake it possible to override this behavior using \u0027pcie_ports\u003dnative\u0027\n(use the PCIe native services regardless of the BIOS response to the\ncontrol request), or \u0027pcie_ports\u003dcompat\u0027 (do not use the PCIe native\nservices at all).\n\nAccordingly, rework the existing PCIe port service drivers so that\nthey don\u0027t request control of the services directly.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "75fb60f26befb59dbfa05cb122972642b7bdd219", "tree": "be015dd00e7748e45f3691f04a16c204546b3026", "parents": [ "2b8fd9186d9275b07aef43e5bb4e98cd571f9a7d" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Aug 23 23:53:11 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 24 13:44:40 2010 -0700" }, "message": "ACPI/PCI: Negotiate _OSC control bits before requesting them \n\nIt is possible that the BIOS will not grant control of all _OSC\nfeatures requested via acpi_pci_osc_control_set(), so it is\nrecommended to negotiate the final set of _OSC features with the\nquery flag set before calling _OSC to request control of these\nfeatures.\n\nTo implement it, rework acpi_pci_osc_control_set() so that the caller\ncan specify the mask of _OSC control bits to negotiate and the mask\nof _OSC control bits that are absolutely necessary to it. Then,\nacpi_pci_osc_control_set() will run _OSC queries in a loop until\nthe mask of _OSC control bits returned by the BIOS is equal to the\nmask passed to it. Also, before running the _OSC request\nacpi_pci_osc_control_set() will check if the caller\u0027s required\ncontrol bits are present in the final mask.\n\nUsing this mechanism we will be able to avoid situations in which the\nBIOS doesn\u0027t grant control of certain _OSC features, because they\ndepend on some other _OSC features that have not been requested.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "79dd9182db2072d63ccf160bb9a3463b1c952723", "tree": "89069b3803a4e07924c6fd4414bbd2a771a432e9", "parents": [ "f1a7bfaf6bb9cb195577e674c0ab2fd0a55d9014" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Aug 21 01:51:44 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 24 13:43:15 2010 -0700" }, "message": "PCI: PCIe: Introduce commad line switch for disabling port services\n\nIntroduce kernel command line switch pcie_ports\u003d allowing one to\ndisable all of the native PCIe port services, so that PCIe ports\nare treated like PCI-to-PCI bridges.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f1a7bfaf6bb9cb195577e674c0ab2fd0a55d9014", "tree": "8150335e1d70d026704f39c28921615d5af9701e", "parents": [ "23b90cfd7bcf8ae1c0711df1cae7dfec3c01aec8" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Aug 21 01:50:52 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 24 13:43:08 2010 -0700" }, "message": "PCI: PCIe AER: Introduce pci_aer_available()\n\nIntroduce a function allowing the caller to check whether to try to\nenable PCIe AER.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1cfd2bda8c486ae0e7a8005354758ebb68172bca", "tree": "76ce15f377d8d6eb3ae4aa8b8b0b415457e38d36", "parents": [ "b57bdda58cda0aaf6def042d101dd85977a286ed", "763e9db9994e27a7d2cb3701c8a097a867d0e0b4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 06 11:44:36 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 06 11:44:36 2010 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (30 commits)\n PCI: update for owner removal from struct device_attribute\n PCI: Fix warnings when CONFIG_DMI unset\n PCI: Do not run NVidia quirks related to MSI with MSI disabled\n x86/PCI: use for_each_pci_dev()\n PCI: use for_each_pci_dev()\n PCI: MSI: Restore read_msi_msg_desc(); add get_cached_msi_msg_desc()\n PCI: export SMBIOS provided firmware instance and label to sysfs\n PCI: Allow read/write access to sysfs I/O port resources\n x86/PCI: use host bridge _CRS info on ASRock ALiveSATA2-GLAN\n PCI: remove unused HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_{SIZE|BOUNDARY}\n PCI: disable mmio during bar sizing\n PCI: MSI: Remove unsafe and unnecessary hardware access\n PCI: Default PCIe ASPM control to on and require !EMBEDDED to disable\n PCI: kernel oops on access to pci proc file while hot-removal\n PCI: pci-sysfs: remove casts from void*\n ACPI: Disable ASPM if the platform won\u0027t provide _OSC control for PCIe\n PCI hotplug: make sure child bridges are enabled at hotplug time\n PCI hotplug: shpchp: Removed check for hotplug of display devices\n PCI hotplug: pciehp: Fixed return value sign for pciehp_unconfigure_device\n PCI: Don\u0027t enable aspm before drivers have had a chance to veto it\n ...\n" }, { "commit": "ea5f9fc5899660dd26c1ccf3fab183bd041140ee", "tree": "b0d0517ee4064cfb587651b195ee5d2be864a8cc", "parents": [ "8cc2bfd87fdd2f4a31f39c86f59df4b4be2c0adc" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Tue Jun 22 17:03:03 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:34 2010 -0700" }, "message": "PCI: Default PCIe ASPM control to on and require !EMBEDDED to disable\n\nThe CONFIG_PCIEASPM option is confusing and potentially dangerous. ASPM is\na hardware mediated feature rather than one under direct OS control, and\neven if the config option is disabled the system firmware may have turned\non ASPM on various bits of hardware. This can cause problems later -\nvarious hardware that claims to support ASPM does a poor job of it and may\nhang or cause other difficulties. The kernel is able to recognise this in\nmany cases and disable the ASPM functionality, but only if CONFIG_PCIEASPM\nis enabled.\n\nGiven that in its default configuration this option will either leave the\nhardware as it was originally or disable hardware functionality that may\ncause problems, it should by default y. The only reason to disable it\nought to be to reduce code size, so make it dependent on CONFIG_EMBEDDED.\n\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nCc: lrodriguez@atheros.com\nCc: maximlevitsky@gmail.com\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "41cd766b065970ff6f6c89dd1cf55fa706c84a3d", "tree": "f52a7346daaaad331dbd260f0e21bcf9d108b2e6", "parents": [ "4302e0fb7fa5b071e30f3cfb68e85155b3d69d9b" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Wed Jun 09 16:05:07 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:15 2010 -0700" }, "message": "PCI: Don\u0027t enable aspm before drivers have had a chance to veto it\n\nThe aspm code will currently set the configured aspm policy before drivers\nhave had an opportunity to indicate that their hardware doesn\u0027t support it.\nUnfortunately, putting some hardware in L0 or L1 can result in the hardware\nno longer responding to any requests, even after aspm is disabled. It makes\nmore sense to leave aspm policy at the BIOS defaults at initial setup time,\nreconfiguring it after pci_enable_device() is called. This allows the\ndriver to blacklist individual devices beforehand.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f6735590e9f441762ab5afeff64ded99e5b19a68", "tree": "58e15ba0d4c00195da9e9b199b7fc73de7f51e64", "parents": [ "73cd3b43f08cc9a9bcb168994b8e9ebd983ff573" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu May 27 11:21:11 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:10 2010 -0700" }, "message": "PCI aerdrv: fix annoying warnings\n\nSome compiler generates following warnings:\n\n In function \u0027aer_isr\u0027:\n warning: \u0027e_src.id\u0027 may be used uninitialized in this function\n warning: \u0027e_src.status\u0027 may be used uninitialized in this function\n\nAvoid status flag \"int ret\" and return constants instead, so that\ngcc sees the return value matching \"it is initialized\" better.\n\nAcked-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c125e96f044427f38d106fab7bc5e4a5e6a18262", "tree": "d9bbd40cc933fe522dbdf8ca2f7edf7b6f2f7ca4", "parents": [ "b14e033e17d0ea0ba12668d0d2f371cd31586994" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jul 05 22:43:53 2010 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jul 19 01:58:48 2010 +0200" }, "message": "PM: Make it possible to avoid races between wakeup and system sleep\n\nOne of the arguments during the suspend blockers discussion was that\nthe mainline kernel didn\u0027t contain any mechanisms making it possible\nto avoid races between wakeup and system suspend.\n\nGenerally, there are two problems in that area. First, if a wakeup\nevent occurs exactly when /sys/power/state is being written to, it\nmay be delivered to user space right before the freezer kicks in, so\nthe user space consumer of the event may not be able to process it\nbefore the system is suspended. Second, if a wakeup event occurs\nafter user space has been frozen, it is not generally guaranteed that\nthe ongoing transition of the system into a sleep state will be\naborted.\n\nTo address these issues introduce a new global sysfs attribute,\n/sys/power/wakeup_count, associated with a running counter of wakeup\nevents and three helper functions, pm_stay_awake(), pm_relax(), and\npm_wakeup_event(), that may be used by kernel subsystems to control\nthe behavior of this attribute and to request the PM core to abort\nsystem transitions into a sleep state already in progress.\n\nThe /sys/power/wakeup_count file may be read from or written to by\nuser space. Reads will always succeed (unless interrupted by a\nsignal) and return the current value of the wakeup events counter.\nWrites, however, will only succeed if the written number is equal to\nthe current value of the wakeup events counter. If a write is\nsuccessful, it will cause the kernel to save the current value of the\nwakeup events counter and to abort the subsequent system transition\ninto a sleep state if any wakeup events are reported after the write\nhas returned.\n\n[The assumption is that before writing to /sys/power/state user space\nwill first read from /sys/power/wakeup_count. Next, user space\nconsumers of wakeup events will have a chance to acknowledge or\nveto the upcoming system transition to a sleep state. Finally, if\nthe transition is allowed to proceed, /sys/power/wakeup_count will\nbe written to and if that succeeds, /sys/power/state will be written\nto as well. Still, if any wakeup events are reported to the PM core\nby kernel subsystems after that point, the transition will be\naborted.]\n\nAdditionally, put a wakeup events counter into struct dev_pm_info and\nmake these per-device wakeup event counters available via sysfs,\nso that it\u0027s possible to check the activity of various wakeup event\nsources within the kernel.\n\nTo illustrate how subsystems can use pm_wakeup_event(), make the\nlow-level PCI runtime PM wakeup-handling code use it.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nAcked-by: markgross \u003cmarkgross@thegnar.org\u003e\nReviewed-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\n" }, { "commit": "b27759f880018b0cd43543dc94c921341b64b5ec", "tree": "486e63a80e0f11d93f9f8ee3a5780b5030154cd0", "parents": [ "7e27d6e778cd87b6f2415515d7127eba53fe5d02" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Jun 18 17:04:22 2010 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jun 18 09:36:37 2010 -0700" }, "message": "PCI/PM: Do not use native PCIe PME by default\n\nCommit c7f486567c1d0acd2e4166c47069835b9f75e77b\n(PCI PM: PCIe PME root port service driver) causes the native PCIe\nPME signaling to be used by default, if the BIOS allows the kernel to\ncontrol the standard configuration registers of PCIe root ports.\nHowever, the native PCIe PME is coupled to the native PCIe hotplug\nand calling pcie_pme_acpi_setup() makes some BIOSes expect that\nthe native PCIe hotplug will be used as well. That, in turn, causes\nproblems to appear on systems where the PCIe hotplug driver is not\nloaded. The usual symptom, as reported by Jaroslav Kameník and\nothers, is that the ACPI GPE associated with PCIe hotplug keeps\nfiring continuously causing kacpid to take substantial percentage\nof CPU time.\n\nTo work around this issue, change the default so that the native\nPCIe PME signaling is only used if directly requested with the help\nof the pcie_pme\u003d command line switch.\n\nFixes https://bugzilla.kernel.org/show_bug.cgi?id\u003d15924 , which is\na listed regression from 2.6.33.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nReported-by: Jaroslav Kameník \u003cjaroslav@kamenik.cz\u003e\nTested-by: Antoni Grzymala \u003cantekgrzymala@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9a90e09854a3c7cc603ab8fc9163f77bb1f66cfa", "tree": "c8c5f767dd2351c9db440f003cc14401583bafd3", "parents": [ "d372e7fe4698bde3a00b718f7901a0025dda47ef", "d3b383338f105f50724c10a7d81b04a3930e886b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "message": "Merge branch \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (27 commits)\n ACPI: Don\u0027t let acpi_pad needlessly mark TSC unstable\n drivers/acpi/sleep.h: Checkpatch cleanup\n ACPI: Minor cleanup eliminating redundant PMTIMER_TICKS to NS conversion\n ACPI: delete unused c-state promotion/demotion data strucutures\n ACPI: video: fix acpi_backlight\u003dvideo\n ACPI: EC: Use kmemdup\n drivers/acpi: use kasprintf\n ACPI, APEI, EINJ injection parameters support\n Add x64 support to debugfs\n ACPI, APEI, Use ERST for persistent storage of MCE\n ACPI, APEI, Error Record Serialization Table (ERST) support\n ACPI, APEI, Generic Hardware Error Source memory error support\n ACPI, APEI, UEFI Common Platform Error Record (CPER) header\n Unified UUID/GUID definition\n ACPI Hardware Error Device (PNP0C33) support\n ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n ACPI, APEI, Document for APEI\n ACPI, APEI, EINJ support\n ACPI, APEI, HEST table parsing\n ACPI, APEI, APEI supporting infrastructure\n ...\n" }, { "commit": "affb72c3a8984ba55e055b0a0228c3ea1a056758", "tree": "a6d4c9051110c03f9222bde9c3dcea7822f8570c", "parents": [ "ea8c071cad789b1919355fc7a67182a5c9994e6b" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue May 18 14:35:16 2010 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed May 19 22:40:14 2010 -0400" }, "message": "ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n\nNow, a dedicated HEST tabling parsing code is used for PCIE AER\nfirmware_first setup. It is rebased on general HEST tabling parsing\ncode of APEI. The firmware_first setup code is moved from PCI core to\nAER driver too, because it is only AER related.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "caa5afbd4831c649b951ae1227a7985f47547e31", "tree": "5000986023ae83933a94795ab1bc22519f9d4e80", "parents": [ "f6d3780061283039de33b402c35c3bf9322afe14" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:23:17 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:40 2010 -0700" }, "message": "PCI: aerdrv: trivial cleanup for aerdrv_core.c\n\nStyle cleanup for pci_{en,dis}able_pcie_error_reporting().\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f6d3780061283039de33b402c35c3bf9322afe14", "tree": "67ec48ba847e45e372d20f93facb658c4d6f2b4f", "parents": [ "89713422a768458a0d375f0c2f3586cd5ccde6a1" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:22:11 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:39 2010 -0700" }, "message": "PCI: aerdrv: trivial cleanup for aerdrv.c\n\nSkip zero-ing in aer_alloc_rpc() since it is allocated by kzalloc().\nThe closing comment marker \"*/\" is recommended for kernel-doc comments.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "89713422a768458a0d375f0c2f3586cd5ccde6a1", "tree": "c446440123602cdb5320617ac7a8c2dbf514ff41", "parents": [ "517cae3829ae8cc3033c24f60e64eb251b2f0d14" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:21:27 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:38 2010 -0700" }, "message": "PCI: aerdrv: introduce default_downstream_reset_link\n\nI noticed that when I inject a fatal error to an endpoint via\naer-inject, aer_root_reset() is called as reset_link for a\ndownstream port at upstream of the endpoint:\n\n pcieport 0000:00:06.0: AER: Uncorrected (Fatal) error received: id\u003d5401\n :\n pcieport 0000:52:02.0: Root Port link has been reset\n\nIt externally appears to be working, but internally issues some\naccesses to PCI_ERR_ROOT_COMMAND/STATUS registers that is for\nroot port so not available on downstream port.\n\nThis patch introduces default_downstream_reset_link that is\na version of aer_root_reset() with no accesses to root port\u0027s\nregister. It is used for downstream ports that has no reset_link\nfunction its specific.\n\nThis patch also updates related description in pcieaer-howto.txt.\nSome minor fixes are included.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "517cae3829ae8cc3033c24f60e64eb251b2f0d14", "tree": "90f54b8aa311e16e3549bda1e1d7148bd631ddd9", "parents": [ "4f7ccf6a6085eefd2517b8c7090608c64b01ab67" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:20:43 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:38 2010 -0700" }, "message": "PCI: aerdrv: rework find_aer_service\n\nThe structure find_aer_service_data is no longer useful.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Jin Dongming \u003cjin.dongming@np.css.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4f7ccf6a6085eefd2517b8c7090608c64b01ab67", "tree": "41d6a5d595bb14cc537333e278f1a3ed4fc19cc4", "parents": [ "e167bfcaa4cd44b4c66206a3c06b2aafb3f1260e" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:19:48 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:37 2010 -0700" }, "message": "PCI: aerdrv: remove is_downstream\n\nThe pcie-\u003eport of port service device points the port associated\nthe service with. The find_aer_service iterates over children of\ngiven port udev.\n\nSo it is clear that the pcie-\u003eport of port service of given port\nudev must always point the udev.\n\nTherefore we can know the type of udev without checking its children.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e167bfcaa4cd44b4c66206a3c06b2aafb3f1260e", "tree": "cc21ae9a6f9efb3271b130e4e69ade52e71be871", "parents": [ "f647a44f5725b0e6c8211096f4b49900164123ee" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:18:26 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:37 2010 -0700" }, "message": "PCI: aerdrv: remove magical ROOT_ERR_STATUS_MASKS\n\nMake it clear that we only interest in 2 *_RCV bits.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f647a44f5725b0e6c8211096f4b49900164123ee", "tree": "dc5e677d978435159dd62e1faf0824fb01e44aa0", "parents": [ "17e21854bd59862f4ee47d1c7e828549f782711b" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:17:33 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:34 2010 -0700" }, "message": "PCI: aerdrv: redefine PCI_ERR_ROOT_*_SRC\n\nThe Error Source Identification Register (Offset 34h) is 4 byte\nwhich contains a couple of 2 byte field, \"[15:0] ERR_COR Source\nIdentification\" and \"[31:16] ERR_FATAL/NONFATAL Source Identification.\"\n\nThis patch defines PCI_ERR_ROOT_ERR_SRC to make dword access sensible.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "17e21854bd59862f4ee47d1c7e828549f782711b", "tree": "b1d7db096b4fa24e0522aa33de2710d2039924d0", "parents": [ "88da13bfabbffb8f89574eb168b9da9a0abc693f" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:16:52 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:33 2010 -0700" }, "message": "PCI: aerdrv: rework do_recovery\n\nMove dev_printks for debug into do_recovery().\nThis allows do_recovery() to return void.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "88da13bfabbffb8f89574eb168b9da9a0abc693f", "tree": "0d618bd5c2ddab8ba03d9b0c21b3998f2928d282", "parents": [ "7c4ec94f72cefec1c1b42219469794a34864a1ee" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:16:16 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:33 2010 -0700" }, "message": "PCI: aerdrv: rework get_e_source()\n\nCurrent get_e_source() returns pointer to an element of array.\nHowever since it also progress consume counter, it is possible\nthat the element is overwritten by newly produced data before\nthe element is really consumed.\n\nThis patch changes get_e_source() to copy contents of the element\nto address pointed by its caller. Once copied the element in\narray can be consumed.\n\nAnd relocate this function to more innocuous place.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7c4ec94f72cefec1c1b42219469794a34864a1ee", "tree": "349c45d1e61680926af565d234fa852cc88c17ed", "parents": [ "4a0c096efd4383fc98aa40e195363f600ba814f8" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:15:08 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:16 2010 -0700" }, "message": "PCI: aerdrv: rework aer_isr_one_error()\n\nDivide tricky for-loop into readable if-blocks.\n\nThe logic to set multi_error_valid (to force walking pci bus\nhierarchy to find 2nd~ error devices) is changed too, to check\nMULTI_{,_UN}COR_RCV bit individually and to force walk only when\nit is required.\n\nAnd rework setting e_info-\u003eseverity for uncorrectable, not to use\nmagic numbers.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4a0c096efd4383fc98aa40e195363f600ba814f8", "tree": "61f7f4aa18e7905b227f2de3622dd43403fc0551", "parents": [ "bd17d4742d5a8cbedd41a1d44c0cdee84a532363" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:14:17 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:15 2010 -0700" }, "message": "PCI: aerdrv: rework add_error_device\n\nStop iteration if we cannot register any more.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd17d4742d5a8cbedd41a1d44c0cdee84a532363", "tree": "5df159b4dbd4ce1eaae5799ecc227e8e368c359e", "parents": [ "c887275e6a5b857b72c798e4a6019160a860e2ef" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:13:41 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:15 2010 -0700" }, "message": "PCI: aerdrv: remove compare_device_id\n\nInline too-simple subroutine only used here.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c887275e6a5b857b72c798e4a6019160a860e2ef", "tree": "8e8629859adcb9fcaacfd334f408d2949e1840b3", "parents": [ "98ca3964fe8da0d742331af80952443af5cff464" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:12:21 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:14 2010 -0700" }, "message": "PCI: aerdrv: introduce is_error_source\n\nTake core part of find_device_iter() to make a new function\nis_error_source() that checks given device has report an error\nor not.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "98ca3964fe8da0d742331af80952443af5cff464", "tree": "35c1b803496ca97322d88754de804117114a7c11", "parents": [ "843f4697eea576c24f057bbdb199115bbb6b10bc" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:11:42 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:14 2010 -0700" }, "message": "PCI: aerdrv: rework find_source_device\n\nReturn bool to indicate that the source device is found or not.\nThis allows us to skip calling aer_process_err_devices() if we can.\n\nAnd move dev_printk for debug into this function.\n\nv2: return bool instead of int\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "843f4697eea576c24f057bbdb199115bbb6b10bc", "tree": "889c40b06c3ca033733cf90f93184ec7917f9076", "parents": [ "460d298d521910483dcdc09920ca4c4a63b16730" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:10:53 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:13 2010 -0700" }, "message": "PCI: aerdrv: make aer_{en,dis}able_rootport static\n\nThese functions are only called from init/remove path of aerdrv,\nso move them from aerdrv_core.c to aerdrv.c, to make them static.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "460d298d521910483dcdc09920ca4c4a63b16730", "tree": "271ff70a7fa27992055de90da9dfeefd7ea5d0f4", "parents": [ "c6d34eddecb34fd84f9fb2ea26a63cfde5662f49" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:10:03 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:13 2010 -0700" }, "message": "PCI: aerdrv: cleanup inconsistent functions\n\nThis cleanup solves some minor naming issues by removing unuseful\nfunction aer_delete_rootport() and by renaming disable_root_aer()\nto aer_disable_rootport().\n\n- Inconsistent location of alloc \u0026 free:\n The struct rpc is allocated in aer_alloc_rpc() at aerdrv.c\n while it is implicitly freed in aer_delete_rootport() at\n aerdrv_core.c.\n\n- Inconsistent function name:\n It makes a bit confusion that aer_delete_rootport() is seemed\n to be paired with aer_enable_rootport(), i.e. there is neither\n \"add\" against \"delete\" nor \"disable\" against \"enable\".\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c6d34eddecb34fd84f9fb2ea26a63cfde5662f49", "tree": "a80ed52485693d649158621edcd8bd2d9431d3c9", "parents": [ "d4dfd7278eade24c4aa4b36b8df981fab04f2f26" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Apr 15 13:09:13 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 11 12:01:12 2010 -0700" }, "message": "PCI: aerdrv: RsvdP of PCI_ERR_ROOT_COMMAND\n\nHandle preserved bits properly.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4352aa5bbf1d0080c2dcf904ce1e4be0a1cb5937", "tree": "cf30890e45bd359380a610444bd36ca7d96528dc", "parents": [ "73a0e614580fb650846be1e9315f6b7b6069b9cc" ], "author": { "name": "Alexander Duyck", "email": "alexander.h.duyck@intel.com", "time": "Thu Mar 25 13:03:30 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Apr 08 09:24:11 2010 -0700" }, "message": "PCI aerdrv: use correct bit defines and add 2ms delay to aer_root_reset\n\nWhile testing completion timeouts I found that hardware was not recovering.\nIt looks like the hot reset was never being propagated to the endpoint\ndevices on the bus due to the fact that we were clearing the bit too\nquickly.\n\nThe documentation I have states that we should be transmitting hot reset\nTS1s for 2ms. To achieve this I have added a 2ms delay from the time we\nset the secondary bus reset bit to the time we clear it. In addition I\nchanged the define used for the secondary bus reset bit to match the\nregister define that was being used.\n\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Alexander Duyck \u003calexander.h.duyck@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "a1e4d72cd3024999bfb6703092ea271438805c89", "tree": "853a289d73ad9ffb04038fc493d209e980a3ef9b", "parents": [ "09c09bc618a4ceec387c57542031b4fc35826e16" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Feb 08 19:16:33 2010 +0100" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Feb 26 20:39:12 2010 +0100" }, "message": "PM: Allow PCI devices to suspend/resume asynchronously\n\nSet power.async_suspend for all PCI devices and PCIe port services,\nso that they can be suspended and resumed in parallel with other\ndevices they don\u0027t depend on in a known way (i.e. devices which are\nnot their parents or children).\n\nThis only affects the \"regular\" suspend and resume stages, which\nmeans in particular that the restoration of the PCI devices\u0027 standard\nconfiguration registers during resume will still be carried out\nsynchronously (at the \"early\" resume stage).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "b16694f70c40ea8d539cdc93a422039771e85870", "tree": "2ac80b596bff438d84c13224076aa474a3c8053c", "parents": [ "6cbf82148ff286ec22a55be6836c3a5bffc489c1" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Feb 22 14:13:39 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:21 2010 -0800" }, "message": "PCIe PME: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe\ncapability offset. This reduces redundant search in PCI configuration\nspace.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "552be54cc4232dc5acc49ccb372129d6f1b6923f", "tree": "65739c06da3ce6a68dfe8fa27d4438d0eb8166d4", "parents": [ "b67ea76172d4b1922c4b3c46c8ea8e9fec1ff38c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Feb 22 14:12:24 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:10 2010 -0800" }, "message": "PCIe PME: use pci_is_pcie()\n\nUse pci_is_pcie() instead of looking at obsolete is_pcie field in\nstruct pci_dev.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c39fae1416d59fd565606793f090cebe3720d50d", "tree": "f53b3dc3202706c328c2306f168058ec2e9ae859", "parents": [ "c7f486567c1d0acd2e4166c47069835b9f75e77b" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:40:07 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:20:39 2010 -0800" }, "message": "PCI PM: Make it possible to force using INTx for PCIe PME signaling\n\nApparently, some machines may have problems with PCI run-time power\nmanagement if MSIs are used for the native PCIe PME signaling. In\nparticular, on the MSI Wind U-100 PCIe PME interrupts are not\ngenerated by a PCIe root port after a resume from suspend to RAM, if\nthe system wake-up was triggered by a PME from the device attached to\nthis port. [It doesn\u0027t help to free the interrupt on suspend and\nrequest it back on resume, even if that is done along with disabling\nthe MSI and re-enabling it, respectively.] However, if INTx\ninterrupts are used for this purpose on the same machine, everything\nworks just fine.\n\nFor this reason, add a kernel command line switch allowing one to\nrequest that MSIs be not used for the native PCIe PME signaling,\nintroduce a DMI table allowing us to blacklist machines that need\nthis switch to be set by default and put the MSI Wind U-100 into this\ntable.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7f486567c1d0acd2e4166c47069835b9f75e77b", "tree": "5552890ac80fc53f61dd9c53a6211610375efa1f", "parents": [ "58ff463396ad00828e922d50998787e97fd32512" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:39:08 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:20:31 2010 -0800" }, "message": "PCI PM: PCIe PME root port service driver\n\nPCIe native PME detection mechanism is based on interrupts generated\nby root ports or event collectors every time a PCIe device sends a\nPME message upstream.\n\nOnce a PME message has been sent by an endpoint device and received\nby its root port (or event collector in the case of root complex\nintegrated endpoints), the Requester ID from the message header is\nregistered in the root port\u0027s Root Status register. At the same\ntime, the PME Status bit of the Root Status register is set to\nindicate that there\u0027s a PME to handle. If PCIe PME interrupt is\nenabled for the root port, it generates an interrupt once the PME\nStatus has been set. After receiving the interrupt, the kernel can\nidentify the PCIe device that generated the PME using the Requester\nID from the root port\u0027s Root Status register. [For details, see PCI\nExpress Base Specification, Rev. 2.0.]\n\nImplement a driver for the PCIe PME root port service working in\naccordance with the above description.\n\nBased on a patch from Shaohua Li \u003cshaohua.li@intel.com\u003e.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd1f46deba615971a58193afd0202878cadf19a7", "tree": "1a197e82ad0f6314f0ff0507c04030aaad933c7c", "parents": [ "61c39bb354a1f791ba6f562b766a72e508a036ee" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Fri Jan 22 14:06:53 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 25 10:42:52 2010 -0800" }, "message": "PCI: fix nested spinlock hang in aer_inject\n\nThe aer_inject module hangs in aer_inject() when checking the device\u0027s\nerror masks. The hang is due to a recursive use of the aer_inject lock.\nThe aer_inject() routine grabs the lock while processing the error and then\ncalls pci_read_config_dword to read the masks. The pci_read_config_dword\nroutine is earlier overridden by pci_read_aer, which among other things,\ngrabs the aer_inject lock.\n\nFixed by moving the pci_read_config_dword calls to read the masks to before\nthe lock is taken.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b49bfd32901625e4adcfee011d2b32a43b4db67d", "tree": "2a83d0d739df23b96b094de83880defc05ea0a6a", "parents": [ "1ae861e652b5457e7fa98ccbc55abea1e207916e" ], "author": { "name": "Youquan,Song", "email": "youquan.song@linux.intel.com", "time": "Thu Dec 17 08:22:48 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:52:49 2010 -0800" }, "message": "PCIe AER: prevent AER injection if hardware masks error reporting\n\nThe Correcteable/Uncorrectable Error Mask Registers are used by PCIe AER\ndriver which will controls the reporting of individual errors to PCIe RC\nvia PCIe error messages.\n\nIf hardware masks special error reporting to RC, the aer_inject driver\nshould not inject aer error.\n\nAcked-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Youquan, Song \u003cyouquan.song@intel.com\u003e\nAcked-by: Ying, Huang \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "46256f83d0d066f99ffde547f27473dfd2a78009", "tree": "b70c070f59d510d3d0e974009199a1c175d753d3", "parents": [ "40da4186a53e59d801130156ecb89fc5830ff227" ], "author": { "name": "Youquan,Song", "email": "youquan.song@linux.intel.com", "time": "Fri Dec 11 18:42:35 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 08:31:46 2010 -0800" }, "message": "PCI: AER: fix aer inject result in kernel oops\n\nIf the BIOS does not export _OSC to allow OS take over the PCIe AER, the\npcie aer driver will not initialize the aer service. However, the\naer_inject driver does not check this scenario, which results in a kernel\noops when injecting an aer error into OS. For example:\n\nBUG: unable to handle kernel NULL pointer dereference at 0000000000000350\nIP: [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\nPGD 155c41067 PUD 157fe0067 PMD 0\nOops: 0002 [#1] SMP\nPid: 5119, comm: aer-inject Not tainted 2.6.32-rc8-mce #2\nRIP: 0010:[\u003cffffffff812e08f7\u003e] [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\nRSP: 0018:ffff880157f81e28 EFLAGS: 00010096\nRAX: 0000000000000296 RBX: 0000000000000000 RCX: 0000000000000100\nRDX: 0000000000010000 RSI: 0000000000000246 RDI: 0000000000000350\nRBP: ffff880157f81e28 R08: 0000000000000004 R09: ffff880157f81dac\nR10: ffff88015a666f60 R11: ffff88015a666f40 R12: ffff88015758cc00\nR13: 0000000000000350 R14: 0000000000000000 R15: 0000000000000100\nFS: 00007f4d4a66e6f0(0000) GS:ffff8800282e0000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b\nCR2: 0000000000000350 CR3: 000000015661a000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess aer-inject (pid: 5119, threadinfo ffff880157f80000, task ffff8801585f4340)\nStack:\n ffff880157f81e78 ffffffff811b1615 ffff880157f81e78 ffffffff81222823\nCall Trace:\n [\u003cffffffff811b1615\u003e] aer_irq+0x38/0x117\n [\u003cffffffff81222823\u003e] ? device_for_each_child+0x5f/0x6f\n [\u003cffffffffa00967bf\u003e] aer_inject_write+0x409/0x45e [aer_inject]\n [\u003cffffffff810eb80e\u003e] vfs_write+0xae/0x16a\n [\u003cffffffff810eb98e\u003e] sys_write+0x47/0x6e\n [\u003cffffffff8100ba2b\u003e] system_call_fastpath+0x16/0x1b\nRIP [\u003cffffffff812e08f7\u003e] _spin_lock_irqsave+0xc/0x23\n RSP \u003cffff880157f81e28\u003e\nCR2: 0000000000000350\n\nSo check the _OSC before assuming that AER is available to the OS.\n\nSigned-off-by: Youquan, Song \u003cyouquan.song@intel.com\u003e\nAcked-by: Ying, Huang \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "40da4186a53e59d801130156ecb89fc5830ff227", "tree": "8eab64b223ca9657a65fb0650f10dce68ff6420f", "parents": [ "45d28b097280a78893ce25a5d0db41e6a2717853" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Tue Dec 15 11:38:04 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 08:29:37 2010 -0800" }, "message": "PCI: pcie portdrv: style cleanup\n\nNo change in logic.\n\nBefore:\n drivers/pci/pcie/portdrv_core.c:\n total: 7 errors, 2 warnings, 508 lines checked\n drivers/pci/pcie/portdrv_pci.c:\n total: 4 errors, 2 warnings, 300 lines checked\n\nAfter:\n drivers/pci/pcie/portdrv_core.c:\n total: 0 errors, 0 warnings, 506 lines checked\n drivers/pci/pcie/portdrv_pci.c:\n total: 0 errors, 0 warnings, 299 lines checked\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7e8af37a9a71b479f58d2fd5f0ddaa6780c51f11", "tree": "c83fc67ebf0df900bf7ac3c30cd282f28a13b8a6", "parents": [ "45e829ea412760d2404d7dfc42528df46aedbf62" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Thu Dec 03 18:00:10 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:54 2009 -0800" }, "message": "PCI: change PCI nomenclature in drivers/pci/ (non-comment changes)\n\nChanging occurrences of variants of PCI-X and PCIe to the PCI-SIG\nterms listed in the \"Trademark and Logo Usage Guidelines\".\nhttp://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf\n\nPatch is limited to drivers/pci/ and changes concern non-comment parts or\nanything that might be visible to the user.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45e829ea412760d2404d7dfc42528df46aedbf62", "tree": "869581b5828f9eb16a5ce38231b58a80a30be67c", "parents": [ "5714868812b563ba8816c1d974f4f07c76941c30" ], "author": { "name": "Stefan Assmann", "email": "sassmann@redhat.com", "time": "Thu Dec 03 06:49:24 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 13:37:53 2009 -0800" }, "message": "PCI: change PCI nomenclature in drivers/pci/ (comment changes)\n\nChanging occurrences of variants of PCI-X and PCIe to the PCI-SIG\nterms listed in the \"Trademark and Logo Usage Guidelines\".\nhttp://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf\n\nPatch is limited to drivers/pci/ and changes concern comments only.\n\nSigned-off-by: Stefan Assmann \u003csassmann@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "471452104b8520337ae2fb48c4e61cd4896e025d", "tree": "8594ae4a8362014e3cccf72a4e8834cdbb610bdd", "parents": [ "0ead0f84e81a41c3e98aeceab04af8ab1bb08d1f" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Dec 14 18:00:08 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 15 08:53:25 2009 -0800" }, "message": "const: constify remaining dev_pm_ops\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "b26a34aa4792b3db2500b8a98cb7702765c1a92e", "tree": "2a34bad3bce325dabc1a3aafbe225c62cee3dd77", "parents": [ "638bba08282fb50ba4ebde073ad70551b929e0f2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Fri Nov 06 11:25:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:09:59 2009 -0800" }, "message": "PCI: fix BUG_ON triggered by logical PCIe root port removal\n\nThis problem happened when removing PCIe root port using PCI logical\nhotplug operation.\n\nThe immediate cause of this problem is that the pointer to invalid\ndata structure is passed to pcie_update_aspm_capable() by\npcie_aspm_exit_link_state(). When pcie_aspm_exit_link_state() received\na pointer to root port link, it unconfigures the root port link and\nfrees its data structure at first. At this point, there are not links\nto configure under the root port and the data structure for root port\nlink is already freed. So pcie_aspm_exit_link_state() must not call\npcie_update_aspm_capable() and pcie_config_aspm_path().\n\nThis patch fixes the problem by changing pcie_aspm_exit_link_state()\nnot to call pcie_update_aspm_capable() and pcie_config_aspm_path() if\nthe specified link is root port link.\n\n------------[ cut here ]------------\nkernel BUG at drivers/pci/pcie/aspm.c:606!\ninvalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC\nlast sysfs file: /sys/devices/pci0000:40/0000:40:13.0/remove\nCPU 1\nModules linked in: shpchp\nPid: 9345, comm: sysfsd Not tainted 2.6.32-rc5 #98 ProLiant DL785 G6\nRIP: 0010:[\u003cffffffff811df69b\u003e] [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\nRSP: 0018:ffff88082a2f5ca0 EFLAGS: 00010202\nRAX: 0000000000000e77 RBX: ffff88182cc3e000 RCX: ffff88082a33d006\nRDX: 0000000000000001 RSI: ffffffff811dff4a RDI: ffff88182cc3e000\nRBP: ffff88082a2f5cc0 R08: ffff88182cc3e000 R09: 0000000000000000\nR10: ffff88182fc00180 R11: ffff88182fc00198 R12: ffff88182cc3e000\nR13: 0000000000000000 R14: ffff88182cc3e000 R15: ffff88082a2f5e20\nFS: 00007f259a64b6f0(0000) GS:ffff880864600000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b\nCR2: 00007feb53f73da0 CR3: 000000102cc94000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess sysfsd (pid: 9345, threadinfo ffff88082a2f4000, task ffff88082a33cf00)\nStack:\n ffff88182cc3e000 ffff88182cc3e000 0000000000000000 ffff88082a33cf00\n\u003c0\u003e ffff88082a2f5cf0 ffffffff811dff52 ffff88082a2f5cf0 ffff88082c525168\n\u003c0\u003e ffff88402c9fd2f8 ffff88402c9fd2f8 ffff88082a2f5d20 ffffffff811d7db2\nCall Trace:\n [\u003cffffffff811dff52\u003e] pcie_aspm_exit_link_state+0xf5/0x11e\n [\u003cffffffff811d7db2\u003e] pci_stop_bus_device+0x76/0x7e\n [\u003cffffffff811d7d67\u003e] pci_stop_bus_device+0x2b/0x7e\n [\u003cffffffff811d7e4f\u003e] pci_remove_bus_device+0x15/0xb9\n [\u003cffffffff811dcb8c\u003e] remove_callback+0x29/0x3a\n [\u003cffffffff81135aeb\u003e] sysfs_schedule_callback_work+0x15/0x6d\n [\u003cffffffff81072790\u003e] worker_thread+0x19d/0x298\n [\u003cffffffff8107273b\u003e] ? worker_thread+0x148/0x298\n [\u003cffffffff81135ad6\u003e] ? sysfs_schedule_callback_work+0x0/0x6d\n [\u003cffffffff810765c0\u003e] ? autoremove_wake_function+0x0/0x38\n [\u003cffffffff810725f3\u003e] ? worker_thread+0x0/0x298\n [\u003cffffffff8107629e\u003e] kthread+0x7d/0x85\n [\u003cffffffff8102eafa\u003e] child_rip+0xa/0x20\n [\u003cffffffff8102e4bc\u003e] ? restore_args+0x0/0x30\n [\u003cffffffff81076221\u003e] ? kthread+0x0/0x85\n [\u003cffffffff8102eaf0\u003e] ? child_rip+0x0/0x20\nCode: 89 e5 8a 50 48 31 c0 c0 ea 03 83 e2 07 e8 b2 de fe ff c9 48 98 c3 55 48 89 e5 41 56 49 89 fe 41 55 41 54 53 48 83 7f 10 00 74 04 \u003c0f\u003e 0b eb fe 48 8b 05 da 7d 63 00 4c 8d 60 e8 4c 89 e1 eb 24 4c\nRIP [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\n RSP \u003cffff88082a2f5ca0\u003e\n---[ end trace 6ae0f65bdeab8555 ]---\n\nReported-by: Alex Chiang \u003cachiang@hp.com\u003e\nTested-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "638bba08282fb50ba4ebde073ad70551b929e0f2", "tree": "ba517f15b67b9f5329d6167df27d6198d1a798b0", "parents": [ "6cdfd995a65a52e05b99e3a72a9b979abe73b312" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Thu Dec 03 10:28:25 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:03:19 2009 -0800" }, "message": "PCI: remove ifdefed pci_cleanup_aer_correct_error_status\n\nThe pci_cleanup_aer_correct_error_status() function has been\n#if 0\u0027d out since 2.6.25. Time to remove the dead code.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6cdfd995a65a52e05b99e3a72a9b979abe73b312", "tree": "37b4f67ea9c156710976ad47ec79431c1320551b", "parents": [ "575939cf548951dde8df0786899ea5a91bb669b2" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Thu Dec 03 10:28:20 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:03:11 2009 -0800" }, "message": "PCI: unconditionally clear AER uncorr status register during cleanup\n\nThe current implementation of pci_cleanup_aer_uncorrect_error_status\nonly clears either fatal or non-fatal error status bits depending\non the state of the I/O channel. This implementation will then often\nleave some bits set after PCI error recovery completes. The uncleared bit\nsettings will then be falsely reported the next time an AER interrupt is\ngenerated for that hierarchy. An easy way to illustrate this issue is to\nuse the aer-inject module to simultaneously inject both an uncorrectable\nnon-fatal and uncorrectable fatal error. One of the errors will not be\ncleared.\n\nThis patch resolves this issue by unconditionally clearing all bits in\nthe AER uncorrectable status register. All settings and corrective action\nstrategies are saved and determined before\npci_cleanup_aer_uncorrect_error_status is called, so this change should not\naffect errory handling functionality.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f9f45604edcf87ac86a9d68ca54106c5fb743719", "tree": "1983255e2df44203e0ae7ce8d3aa2c1c9c67b548", "parents": [ "694f88ef7ada0d99e304f687ba92e268a594358b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:06:51 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:24 2009 -0800" }, "message": "PCI: portdrv: remove redundant definitions\n\nRemove unnecessary definitions from portdrv.h and use generic\ndefinitions instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "694f88ef7ada0d99e304f687ba92e268a594358b", "tree": "f7095c20f3a6111947a0edaa99dfddd366dbf4b2", "parents": [ "40717c39b1e6c064f48a263a27e58642221e8661" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:06:15 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:19 2009 -0800" }, "message": "PCI: portdrv: remove unnecessary struct pcie_port_data\n\nRemove \u0027port_type\u0027 field in struct pcie_port_data(), because we can\nget port type information from struct pci_dev. With this change, this\npatch also does followings:\n\n - Remove struct pcie_port_data because it no longer has any field.\n - Remove portdrv private definitions about port type (PCIE_RC_PORT,\n PCIE_SW_UPSTREAM_PORT and PCIE_SW_DOWNSTREAM_PORT), and use generic\n definitions instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "40717c39b1e6c064f48a263a27e58642221e8661", "tree": "62c92897f5370900b5cfd6769bfa193ae1a61320", "parents": [ "fbb5de70bbe13ecbebb04226dd6d52b1258dc247" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:05:35 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:10 2009 -0800" }, "message": "PCI: portdrv: minor cleanup for pcie_port_device_register\n\nMinor cleanups for pcie_port_device_register().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fbb5de70bbe13ecbebb04226dd6d52b1258dc247", "tree": "0298455195db5d154718fad4cc411125080a9e3a", "parents": [ "1ce5e83063bf388a2c9fa1e3d4d3122146ad305d" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:05:01 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:56:06 2009 -0800" }, "message": "PCI: portdrv: add missing irq cleanup\n\nAdd missing service irqs cleanup in the error code path of\npcie_port_device_register().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ce5e83063bf388a2c9fa1e3d4d3122146ad305d", "tree": "10528a2c8dd991a7c6ad6e55058469d96aa335d5", "parents": [ "dc5351784eb36f1fec4efa88e01581be72c0b711" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:04:30 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:59 2009 -0800" }, "message": "PCI: portdrv: enable device before irq initialization\n\nCall pci_enable_device() before initializing service irqs, because\nlegacy interrupt is initialized in pci_enable_device() on some\narchitectures.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dc5351784eb36f1fec4efa88e01581be72c0b711", "tree": "b91a30f23149bbf7d243c63f68af43bc0e46dc6f", "parents": [ "d013598d9a46befebdfd37195829ce411e4878ea" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:04:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:51 2009 -0800" }, "message": "PCI: portdrv: cleanup service irqs initialization\n\nThis patch cleans up the service irqs initialization as follows:\n\n - Remove \u0027irq_mode\u0027 field in pcie_port_data and related definitions,\n which is not needed because we can get the same information from\n \u0027is_msix\u0027, \u0027is_msi\u0027 and \u0027pin\u0027 fields in struct pci_dev.\n\n - Change the name of \u0027vectors\u0027 argument of assign_interrupt_mode() to\n \u0027irqs\u0027 because it holds irq numbers actually. People might confuse\n it with CPU vector or MSI/MSI-X vector.\n\n - Change function name assign_interrupt_mode() to init_service_irqs()\n becasuse we no longer have \u0027irq_mode\u0027 data structure, and new name\n is more straightforward (IMO).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d013598d9a46befebdfd37195829ce411e4878ea", "tree": "92d461ff66a29cbf9b23af2570de4a99ad9a16c6", "parents": [ "9e5d0b16dada536dfe2f1e893b6ad0225ff8a2c9" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:03:27 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:44 2009 -0800" }, "message": "PCI: portdrv: check capabilities first\n\nMove capability check capability to the beginning of\npcie_port_device_register() prevents redundant execution path.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9e5d0b16dada536dfe2f1e893b6ad0225ff8a2c9", "tree": "1861e7d3d52a5aeb91284ca6b1e310811adb2eb3", "parents": [ "2dd60e96b4d52bccd2dd585e776a3449d7b34b8f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:02:51 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:37 2009 -0800" }, "message": "PCI: portdrv: move PME capability check\n\nNo reason to check PME capability outside get_port_device_capability().\nDo it in get_port_device_capability().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2dd60e96b4d52bccd2dd585e776a3449d7b34b8f", "tree": "917f339b7542be53ec3b64c12a221d5e6700eec1", "parents": [ "52a0f24beabe9e89223e367c65a0156dff17265c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:02:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:26 2009 -0800" }, "message": "PCI: portdrv: remove redundant pcie type calculation\n\nPCIe port type is already stored in \u0027pcie_type\u0027 field of struct\npci_dev. So we don\u0027t need to get it from pci configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "52a0f24beabe9e89223e367c65a0156dff17265c", "tree": "d6249304150228dcb15052781cb9f26afae05be4", "parents": [ "898294c97500b1cdff6edce52fd34e024eb070ec" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:01:28 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:18 2009 -0800" }, "message": "PCI: portdrv: cleanup pcie_device registration\n\nIn the current port bus driver implementation, pcie_device allocation,\ninitialization and registration are done in separated functions. Doing\nthose in one function make the code simple and easier to read.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "898294c97500b1cdff6edce52fd34e024eb070ec", "tree": "0f5faec54c06f3775c164b48a1c48659c6ceeb4c", "parents": [ "59353ea30e65ab3ae181d6175e3212e1361c3787" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 25 21:00:53 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 15:55:12 2009 -0800" }, "message": "PCI: portdrv: remove redundant pcie_port_device_probe\n\nWe don\u0027t need pcie_port_device_probe() because we can get pci\ndevice/port type using pci_is_pcie() and \u0027pcie_type\u0027 fields in struct\npci_dev. Remove pcie_port_device_probe().\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b44d7db36480a3b27e78141fc9d6597aa577744b", "tree": "76780c8f3ed3644fafa3e8c38b8d5608bed83be3", "parents": [ "8b06477dc4fcdfc21442ad334d3f3e335225ea0c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:37:24 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:17 2009 -0800" }, "message": "PCIe AER: use pci_is_pcie()\n\nChanges for PCIe AER driver to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8b06477dc4fcdfc21442ad334d3f3e335225ea0c", "tree": "77a614b6b702e884944f2bf7e2b44bef922e4633", "parents": [ "5f4d91a1228ac85c75b099efd36fff1a3407335c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:36:52 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:17 2009 -0800" }, "message": "PCIe ASPM: use pci_is_pcie()\n\nChange for PCIe ASPM driver to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "db9538a7495e33f3571c0e791c7678bc0c6ef50f", "tree": "690c5977a83e5c7f0423870dd208784afcd4b159", "parents": [ "dba90dfe48e2e00e79a15c95940730b6926ee176" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:33:30 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:14 2009 -0800" }, "message": "PCIe ASPM: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCIe ASPM driver. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dba90dfe48e2e00e79a15c95940730b6926ee176", "tree": "af32687abec213653a6432842a8962adcf3a9e8c", "parents": [ "39a53062cb5b2ceca6035f3ed67317672f0bcf3b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:32:42 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:13 2009 -0800" }, "message": "PCIe port bus: use pci_pcie_cap()\n\nUse pci_pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI Express Port Bus driver. This avoids unnecessary serarch\nin PCI configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "39a53062cb5b2ceca6035f3ed67317672f0bcf3b", "tree": "cafbfa800f85c28abad3504787555009ebd97dd0", "parents": [ "06a1cbafb253c4c60d6a54a994887f5fbceabcc0" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:31:38 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:13 2009 -0800" }, "message": "PCIe AER: use pci_pcie_cap()\n\nUse pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCIe AER driver. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "476f644edf7c22b47e6a118e4a1e138112a5ef14" }