)]}' { "log": [ { "commit": "0cbaa57d828aa0a067e06d3c6d795b12ae9fb776", "tree": "871e08f70566b16736ae228eddac018c77ca1144", "parents": [ "99662dd1ce05dbe6394771fcb6ca21bd2aa35987", "284f5f9dbac170b054c1e386ef92cbf654e91bba" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon May 07 09:23:27 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon May 07 09:23:27 2012 -0600" }, "message": "Merge branch \u0027topic/stratus\u0027 into next\n" }, { "commit": "284f5f9dbac170b054c1e386ef92cbf654e91bba", "tree": "74cacc94070d5590378c368fa7378d37319d07be", "parents": [ "66f75a5d028beaf67c931435fdc3e7823125730c" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 15:21:02 2012 -0600" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 15:21:02 2012 -0600" }, "message": "PCI: work around Stratus ftServer broken PCIe hierarchy\n\nA PCIe downstream port is a P2P bridge. Its secondary interface is\na link that should lead only to device 0 (unless ARI is enabled)[1], so\nwe don\u0027t probe for non-zero device numbers.\n\nSome Stratus ftServer systems have a PCIe downstream port (02:00.0) that\nleads to both an upstream port (03:00.0) and a downstream port (03:01.0),\nand 03:01.0 has important devices below it:\n\n [0000:02]-+-00.0-[03-3c]--+-00.0-[04-09]--...\n \\-01.0-[0a-0d]--+-[USB]\n +-[NIC]\n +-...\n\nPreviously, we didn\u0027t enumerate device 03:01.0, so USB and the network\ndidn\u0027t work. This patch adds a DMI quirk to scan all device numbers,\nnot just 0, below a downstream port.\n\nBased on a patch by Prarit Bhargava.\n\n[1] PCIe spec r3.0, sec 7.3.1\n\nCC: Myron Stowe \u003cmstowe@redhat.com\u003e\nCC: Don Dutile \u003cddutile@redhat.com\u003e\nCC: James Paradis \u003cjames.paradis@stratus.com\u003e\nCC: Matthew Wilcox \u003cmatthew.r.wilcox@intel.com\u003e\nCC: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCC: Prarit Bhargava \u003cprarit@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "4fa2649a01a4357a82dcc60ef8fb7b8c441e64ed", "tree": "dfe8dd728396fd3034f20de91bb610422a9bc4e6", "parents": [ "7b54366358008241f88228f02cc80ab352265eac" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Mon Apr 02 18:31:53 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 14:52:43 2012 -0600" }, "message": "PCI: add host bridge release support\n\nWe need a hook to release host bridge resources allocated when creating\nroot bus.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "7b54366358008241f88228f02cc80ab352265eac", "tree": "4de6ae8ce83afabf1b4405cba6895b09d1bc790d", "parents": [ "459f58ce51e2e11235b7bb4b1732ebf3c17d86f7" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Mon Apr 02 18:31:53 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 13:53:42 2012 -0600" }, "message": "PCI: add generic device into pci_host_bridge struct\n\nUse that device for pci_root_bus bridge pointer.\n\nUse pci_release_bus_bridge_dev() to release allocated pci_host_bridge in\nremove path.\n\nUse root bus bridge pointer to get host bridge pointer instead of searching\nhost bridge list. That leaves the host bridge list unused, so remove it.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "610929e119b2166167f4f8fce85408472e77a16a", "tree": "a9d178fade610b5eacf5fa534d578f29afaab888", "parents": [ "66f75a5d028beaf67c931435fdc3e7823125730c" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Mon Apr 02 18:31:53 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Mon Apr 30 13:36:14 2012 -0600" }, "message": "PCI: move host bridge-related code to host-bridge.c\n\nMove host bridge-related code from probe.c to a new host-bridge.c.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e" }, { "commit": "cf48fb6a2bf2e59990e1438d0dedc706df911996", "tree": "ece7583684a8a3e7a97d471db9a6984ababf100b", "parents": [ "63ab387ca0d1576edef35ef68e4b8ea5e0757b7a" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Mar 16 17:47:59 2012 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Mar 20 10:41:27 2012 -0700" }, "message": "PCI: fix bridge I/O window bus-to-resource conversion\n\nIn 5bfa14ed9f3c, I forgot to initialize res2.flags before calling\npcibios_bus_to_resource(), which depends on the resource type to locate the\ncorrect aperture. This bug won\u0027t hurt x86, which currently never has an\noffset between bus and CPU addresses, but will affect other architectures.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2069ecfbe14ebd71a6f98e8a00724e9adf4fe4ee", "tree": "5a0328d6e545a6488e85face05b0a4d78676bedf", "parents": [ "8474ecd9231434d71a39cd1ba118629e1b036137" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Wed Feb 15 21:40:31 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Feb 24 14:37:26 2012 -0800" }, "message": "PCI: Move \"pci reassigndev resource alignment\" out of quirks.c\n\nThis isn\u0027t really a quirk; calling it directly from pci_add_device makes\nmore sense.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fb127cb9de791d62fb393d6e65fa9869bddd2460", "tree": "5cb45ac2fd5139cfc9165fead210a3ad2bb3b2a5", "parents": [ "4ba2aef3157f483fd67ac2616f14dbc32a3f751d" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:04 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:04 2012 -0700" }, "message": "PCI: collapse pcibios_resource_to_bus\n\nEverybody uses the generic pcibios_resource_to_bus() supplied by the core\nnow, so remove the ARCH_HAS_GENERIC_PCI_OFFSETS used during conversion.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "36a66cd6fd0a70ac6848d740d9cf7a4360b5776a", "tree": "7cc903ad9f63e9bd1065b6d722fb86f4196dceea", "parents": [ "5bfa14ed9f3ca21fcecbcfbf4a848c002b740c41" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:00 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:00 2012 -0700" }, "message": "PCI: add generic pcibios_resource_to_bus()\n\nThis replaces the generic versions of pcibios_resource_to_bus() and\npcibios_bus_to_resource() in asm-generic/pci.h with versions that use\npci_resource_to_bus() and pci_bus_to_resource().\n\nThe replacements are equivalent except that they can apply host\nbridge window offsets when the arch has supplied them by using\npci_add_resource_offset().\n\nEach arch can convert to using pci_add_resource_offset() individually by\nremoving its device resource fixups from pcibios_fixup_bus() and supplying\nARCH_HAS_GENERIC_PCI_OFFSETS. ARCH_HAS_GENERIC_PCI_OFFSETS can be removed\nafter all have converted.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "5bfa14ed9f3ca21fcecbcfbf4a848c002b740c41", "tree": "dc28c99c694007fca535b906c1044101241abb73", "parents": [ "0efd5aab41e18a1175f72641696cfda154ba6c87" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:00 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:00 2012 -0700" }, "message": "PCI: convert bus addresses to resource when reading BARs\n\nSome PCI host bridges translate CPU addresses to PCI bus addresses.\nPreviously, we initialized pci_dev resources with PCI bus addresses,\nthen converted them to CPU addresses later in arch-specific code\n(pcibios_fixup_resources()), which leaves a window of time where the\npci_dev resources are incorrect.\n\nThis patch adds support in the core for this address translation.\nWhen the arch creates the root bus, it can supply the host bridge\naddress translation information, and the core can use it to set the\npci_dev resources correctly from the beginning.\n\nThis gives us a way to fix the problem that quirks that run between device\ndiscovery and pcibios_fixup_resources() fail because they use pci_dev\nresources that haven\u0027t been converted. The reference below is to one\nsuch problem that affected ARM and ia64.\n\nNote that this patch has no effect until an arch starts using\npci_add_resource_offset() with a non-zero offset: before that, all\nall host bridge windows have a zero offset and pci_bus_to_resource()\ncopies the pci_bus_region directly to the struct resource.\n\nReference: https://lkml.org/lkml/2009/10/12/405\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "0efd5aab41e18a1175f72641696cfda154ba6c87", "tree": "2480b5ade8937d18104c5ecc1423ca1eac1b154e", "parents": [ "5a21d70dbd33d20713fb735ad9381711b0ae2c9b" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:00 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:19:00 2012 -0700" }, "message": "PCI: add struct pci_host_bridge_window with CPU/bus address offset\n\nSome PCI host bridges apply an address offset, so bus addresses on PCI are\ndifferent from CPU addresses. This patch adds a way for architectures to\ntell the PCI core about this offset. For example:\n\n LIST_HEAD(resources);\n pci_add_resource_offset(\u0026resources, host-\u003eio_space, host-\u003eio_offset);\n pci_add_resource_offset(\u0026resources, host-\u003emem_space, host-\u003emem_offset);\n pci_scan_root_bus(parent, bus, ops, sysdata, \u0026resources);\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "5a21d70dbd33d20713fb735ad9381711b0ae2c9b", "tree": "f3c6c65295f1356f62389fafad777d7be047aca5", "parents": [ "a5390aa6dc3646b08bed421944cef0daf78ab994" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:18:59 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:18:59 2012 -0700" }, "message": "PCI: add struct pci_host_bridge and a list of all bridges found\n\nThis adds a list of all PCI host bridges we find and a way to look up\nthe host bridge from a pci_dev.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "a5390aa6dc3646b08bed421944cef0daf78ab994", "tree": "c7c84410c2db3ca93e912135cd3c1722d4b644ac", "parents": [ "844393f4c5e309dd262b27796471c47e348b57a8" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:18:59 2012 -0700" }, "committer": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Thu Feb 23 20:18:59 2012 -0700" }, "message": "PCI: don\u0027t publish new root bus until it\u0027s fully initialized\n\nWhen pci_create_root_bus() adds the new struct pci_bus to the global\npci_root_buses list, the bus becomes visible to other parts of the\nkernel, so it should be fully initialized.\n\nThis patch delays adding the bus to the pci_root_buses list until after\nall the struct pci_bus initialization is finished.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\n" }, { "commit": "f796841e49fe086176e27ed0e1f3f7a1123a4a6b", "tree": "60d5b1f245ba1a2ca6d81e5e73379cfb26089071", "parents": [ "2dd8ba921d570fcd016f8038c63fa9668892d16b" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sat Feb 11 00:18:30 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Feb 23 12:08:53 2012 -0800" }, "message": "PCI: fix memleak for pci dev removing during hotplug\n\nunreferenced object 0xffff880276d17700 (size 64):\n comm \"swapper/0\", pid 1, jiffies 4294897182 (age 3976.028s)\n hex dump (first 32 bytes):\n 00 00 00 00 00 00 00 00 18 f9 de 76 02 88 ff ff ...........v....\n 10 00 00 00 0e 00 00 00 0f 28 40 00 00 00 00 00 .........(@.....\n backtrace:\n [\u003cffffffff81c8aede\u003e] kmemleak_alloc+0x26/0x43\n [\u003cffffffff811385f0\u003e] __kmalloc+0x121/0x183\n [\u003cffffffff813cf821\u003e] pci_add_cap_save_buffer+0x35/0x7c\n [\u003cffffffff813d12b7\u003e] pci_allocate_cap_save_buffers+0x1d/0x65\n [\u003cffffffff813cdb52\u003e] pci_device_add+0x92/0xf1\n [\u003cffffffff81c8afe6\u003e] pci_scan_single_device+0x9f/0xa1\n [\u003cffffffff813cdbd2\u003e] pci_scan_slot.part.20+0x21/0x106\n [\u003cffffffff813cdce2\u003e] pci_scan_slot+0x2b/0x35\n [\u003cffffffff81c8dae4\u003e] __pci_scan_child_bus+0x51/0x107\n [\u003cffffffff81c8d75b\u003e] pci_scan_bridge+0x376/0x6ae\n [\u003cffffffff81c8db60\u003e] __pci_scan_child_bus+0xcd/0x107\n [\u003cffffffff81c8dbab\u003e] pci_scan_child_bus+0x11/0x2a\n [\u003cffffffff81cca58c\u003e] pci_acpi_scan_root+0x18b/0x21c\n [\u003cffffffff81c916be\u003e] acpi_pci_root_add+0x1e1/0x42a\n [\u003cffffffff81406210\u003e] acpi_device_probe+0x50/0x190\n [\u003cffffffff814a0227\u003e] really_probe+0x99/0x126\n\nNeed to free saved_buffer for capabilities.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2dd8ba921d570fcd016f8038c63fa9668892d16b", "tree": "f2ff01098ed51ee0b6682f91c1b9bf628c84f848", "parents": [ "9ad52e63db1bc588636bc66b9133498c46e6535c" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sun Feb 19 14:50:12 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Feb 23 12:05:59 2012 -0800" }, "message": "PCI: Fix device class print out\n\nFound debug print of class is shifted.\n\n| pci 0000:f8:15.2: [8086:2b56] type 0 class 0x000600\n\nCode is trying to print class with 6 digits, but use shifted class with\n4 digits valid value as variable.\n\nChange to original dev-\u003eclass directly.\n\nAlso remove not needed calculating of local variable class, because it\nwill be updated after pci_fixup_device(pci_fixup_early...)\n\nAlso unify type print out when class and header is not matched.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "efdc87dab1cdf25ba631181ac0ead3fb2023dd10", "tree": "f55b7d0b2e9bbfd9dd280c85166aef423bf68d75", "parents": [ "ac205b7bb72fa4227d2e79979bbe2b4687cdf44d" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Jan 27 10:55:10 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 14 08:44:59 2012 -0800" }, "message": "PCI: Separate pci_bus_read_dev_vendor_id from pci_scan_device\n\nWe can reuse it for pciehp probing.\n\n-v2: according to Kenji, fix crs timeout checking, and export the function\n for later use when pciehp is compiled as a module.\n\nSuggested-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9b03088f955552299f50a1f660372698b07ab339", "tree": "4cc4a7d8059186eca4b20a9733f3c0954ff09d96", "parents": [ "2f320521a0d2d11fb857be09d05e2fbbf3ef8c13" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sat Jan 21 02:08:23 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 14 08:44:53 2012 -0800" }, "message": "PCI: Make pci_rescan_bus handle add_list\n\nThis allows us to allocate resources to hotplug bridges during\nremove/rescan.\n\nWe need to move the function to setup-bus.c so it can use\n__pci_bus_size_bridges and __pci_bus_assign_resources directly to take\nthe add_list resource tracking list.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2f320521a0d2d11fb857be09d05e2fbbf3ef8c13", "tree": "9b8d91f3d64f383405511c33fd4d9c5d4aaa20c2", "parents": [ "8424d7592eab8245b51051ee458e598213bca3b2" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sat Jan 21 02:08:22 2012 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 14 08:44:53 2012 -0800" }, "message": "PCI: Make rescan bus increase bridge resource size if needed\n\nCurrent rescan will not touch bridge MMIO and IO.\n\nTry to reuse pci_assign_unassigned_bridge_resources(bridge) to update bridge\nresources, if child devices need more resources.\n\nOnly do that for bridges whose children are all removed already; i.e. don\u0027t\nrelease resources that could already be in use by drivers on child devices.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "71f6bd4a23130cd2f4b036010c5790b1295290b9", "tree": "fdd218f6102bea21de0a0c5663b4da0f1787a23e", "parents": [ "acb42a3b611d7ad4cb173c3b37674b549df2ffeb" ], "author": { "name": "Yinghai Lu", "email": "yinghai.lu@oracle.com", "time": "Mon Jan 30 12:25:24 2012 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Feb 10 11:34:42 2012 -0800" }, "message": "PCI: workaround hard-wired bus number V2\n\nFixes PCI device detection on IBM xSeries IBM 3850 M2 / x3950 M2\nwhen using ACPI resources (_CRS).\nThis is default, a manual workaround (without this patch)\nwould be pci\u003dnocrs boot param.\n\nV2: Add dev_warn if the workaround is hit. This should reveal\nhow common such setups are (via google) and point to possible\nproblems if things are still not working as expected.\n-\u003e Suggested by Jan Beulich.\n\nCc: stable@vger.kernel.org\nTested-by: garyhade@us.ibm.com\nSigned-off-by: Yinghai Lu \u003cyinghai.lu@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "118faafaf987f521832843d36c6be580983f9a6b", "tree": "56e9146fa7b4777f29977989884f912a68432e9f", "parents": [ "7ec303a7247a46a7a88a4f890466fd12dbdd5dc6" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:28:24 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:11:15 2012 -0800" }, "message": "PCI: remove pci_create_bus()\n\nAll users of pci_create_bus() have been converted to pci_create_root_bus(),\nso remove it.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7e00fe2e53fd3a1540febcb2d2bee9d0b2eea507", "tree": "48af088a8e81080f94159e7988a4c0493d456b8f", "parents": [ "1e39ae9f9035ee02e014b5fe29461674fe19624d" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:26:05 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:55 2012 -0800" }, "message": "PCI: deprecate pci_scan_bus_parented()\n\nUsers of pci_scan_bus_parented() should be converted to use either\n pci_scan_root_bus() (preferred, but also calls pci_bus_add_devices)\nor\n pci_create_root_bus()\n pci_scan_child_bus()\n\nSince pci_scan_bus_parented(), I\u0027m marking it deprecated now and will\nactually remove it later.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1e39ae9f9035ee02e014b5fe29461674fe19624d", "tree": "001fabe45ba74c019c99dca798260792a4400841", "parents": [ "de4b2f76d69673cea08be952dcb4df2f4c81c6e3" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:26:00 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:54 2012 -0800" }, "message": "PCI: convert pci_scan_bus_parented() to use pci_create_root_bus()\n\nThis converts pci_scan_bus_parented() to use pci_create_root_bus()\ninstead of pci_create_bus(). The new bus still has the default (incorrect)\nresources, so this patch doesn\u0027t help fix that problem, but it does remove\none more use of pci_create_bus().\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "de4b2f76d69673cea08be952dcb4df2f4c81c6e3", "tree": "c4ad7b48299c2916117367641dfe1fa09325d8e1", "parents": [ "a2ebb827958a4ab3577443f89037f229683c644a" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:55 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:53 2012 -0800" }, "message": "PCI: convert pci_scan_bus() to use pci_create_root_bus()\n\nI plan to deprecate pci_scan_bus_parented(), so use pci_create_root_bus()\ndirectly instead. pci_scan_bus() itself will be removed as soon as all\ncallers are gone, so this is just an interim step.\n\nv2: export pci_scan_bus\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a2ebb827958a4ab3577443f89037f229683c644a", "tree": "c1e44c472315f75c8ba9d147e3712db1e9017a1e", "parents": [ "166c6370754a0a92386e2ffb0eeb06e50ac8588d" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:50 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:52 2012 -0800" }, "message": "PCI: add pci_scan_root_bus() that accepts resource list\n\n\"Early\" and \"header\" quirks often use incorrect bus resources because they\nsee the default resources assigned by pci_create_bus(), before the\narchitecture fixes them up (typically in pcibios_fixup_bus()). Regions\nreserved by these quirks end up with the wrong parents.\n\nHere\u0027s the standard path for scanning a PCI root bus:\n\n pci_scan_bus or pci_scan_bus_parented\n pci_create_bus \u003c-- A create with default resources\n pci_scan_child_bus\n pci_scan_slot\n pci_scan_single_device\n pci_scan_device\n pci_setup_device\n pci_fixup_device(early) \u003c-- B\n pci_device_add\n pci_fixup_device(header) \u003c-- C\n pcibios_fixup_bus \u003c-- D fill in correct resources\n\nEarly and header quirks at B and C use the default (incorrect) root bus\nresources rather than those filled in at D.\n\nThis patch adds a new pci_scan_root_bus() function that sets the bus\nresources correctly from a supplied list of resources.\n\nI intend to remove pci_scan_bus() and pci_scan_bus_parented() after\nfixing all callers.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "166c6370754a0a92386e2ffb0eeb06e50ac8588d", "tree": "c9bbbf23a0508cd93d546ecbfdb9fcd423a1e461", "parents": [ "a9d9f5276cb3fa08351e8837ab9398bfd8e69a2e" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:45 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:51 2012 -0800" }, "message": "PCI: add pci_create_root_bus() that accepts resource list\n\npci_create_bus() assigns ioport_resource and iomem_resource as the default\nbus resources, i.e., the entire address space. Architectures fix these\nlater, typically in pcibios_fixup_bus() or after pci_scan_bus_parented()\nreturns, but code that runs in the interim sees incorrect resource\ninformation.\n\nThis patch adds a new pci_create_root_bus() that sets the bus resources\ncorrectly from a supplied list of resources.\n\nI intend to remove pci_create_bus() after changing all callers.\n\nBased on original patch by Deng-Cheng Zhu.\n\nReference: http://www.spinics.net/lists/mips/msg41654.html\nReference: https://lkml.org/lkml/2011/8/26/88\nSigned-off-by: Deng-Cheng Zhu \u003cdczhu@mips.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a9d9f5276cb3fa08351e8837ab9398bfd8e69a2e", "tree": "c23406ab8668e176bcb0bdf15d201ce3afc4613b", "parents": [ "45ca9e9730c5acdb482dd95799fd8ac834481897" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Fri Oct 28 16:25:40 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:51 2012 -0800" }, "message": "PCI: show host bridges and root bus resources\n\nShow the bus number and resources for every root bus we create. This\nwill become more interesting when we supply the correct resources\ninstead of using the defaults (ioport_resource and iomem_resource).\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "68e35c9b0b9dfad1ec5d1e2858b9c7e2076763e5", "tree": "b29ecd519677c8a424472a6303e7d0e091b3f331", "parents": [ "82440a8253e09047410ff4df5c202be15645573f" ], "author": { "name": "Zac Storer", "email": "zac.3.14159@gmail.com", "time": "Thu Nov 17 23:07:49 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 06 12:10:31 2012 -0800" }, "message": "PCI: fix a brace coding style issue in probe.c\n\nFixed a brace coding style issue.\n\nSigned-off-by: Zac Storer \u003czac.3.14159@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a513a99a7cebfb452839cc09c9c0586f72d96414", "tree": "566fb8a8fa8c02ede05b2694dd16a8efea5342bb", "parents": [ "a1c473aa11e61bc871be16279c9bf976acf22504" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Fri Oct 14 14:56:16 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Oct 27 12:45:44 2011 -0700" }, "message": "PCI: Clean-up MPS debug output\n\nClean-up MPS debug output to make it a single line and aligned, thus\nmaking it more readable for a large number of buses and devices in a\nsingle system.\n\nSuggested by Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\n\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "62f392ea5b5f87b641e16e61a4cedda21ef7341f", "tree": "3392e1c0b10f851df98b18797c0637608887d624", "parents": [ "d387a8d66670371e6be3b6d6bde2e38b8cade076" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Fri Oct 14 14:56:14 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Oct 27 12:45:43 2011 -0700" }, "message": "PCI: enable MPS \"performance\" setting to properly handle bridge MPS\n\nRework the \"performance\" MPS option to configure the device MPS with the\nsmaller of the device MPSS or the bridge MPS (which is assumed to be\nproperly configured at this point to the largest allowable MPS based on\nits parent bus).\n\nAlso, rework the MRRS setting to report an inability to set the MRRS to\na valid setting.\n\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5f39e6705faade2e89d119958a8c51b9b6e2c53c", "tree": "e9d69f2f465daeca7cdc452a3b19d702f15e98b0", "parents": [ "05faadcf59507e8eea57ffbeea9cbb14c9a2ab3d" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Mon Oct 03 09:50:20 2011 -0500" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 04 09:52:28 2011 -0700" }, "message": "PCI: Disable MPS configuration by default\n\nAdd the ability to disable PCI-E MPS turning and using the BIOS\nconfigured MPS defaults. Due to the number of issues recently\ndiscovered on some x86 chipsets, make this the default behavior.\n\nAlso, add the option for peer to peer DMA MPS configuration. Peer to\npeer DMA is outside the scope of this patch, but MPS configuration could\nprevent it from working by having the MPS on one root port different\nthan the MPS on another. To work around this, simply make the system\nwide MPS the smallest possible value (128B).\n\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "1a4b1a41b8a3d5256019854e851beed063b34344", "tree": "fa62183e093cf032c74cac8149fb69a49b07b7e0", "parents": [ "2f4d3218e95d48de2951dcf2bea619ea49ef93de" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Sep 13 15:16:33 2011 -0300" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Sep 13 16:08:31 2011 -0700" }, "message": "pci: Don\u0027t crash when reading mpss from root complex\n\nIn pcie_find_smpss(), we have the following statement:\n\n \tif (dev-\u003eis_hotplug_bridge \u0026\u0026 (!list_is_singular(\u0026dev-\u003ebus-\u003edevices) ||\n\t dev-\u003ebus-\u003eself-\u003epcie_type !\u003d PCI_EXP_TYPE_ROOT_PORT))\n\nThe problem is that at least on my machine, this gets called for the\nroot complex (virtual P2P bridge), and dev-\u003ebus-\u003eself is NULL since\nthe parent bus for this is not itself anchor to a PCI device.\n\nThis adds the necessary NULL check.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "ed2888e906b56769b4ffabb9c577190438aa68b8", "tree": "81d55511aaa0b2b4074b9432fee3e23beb98b503", "parents": [ "5307f6d5fb12fd01f9f321bc4a8fd77e74858647" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Thu Sep 08 16:41:18 2011 -0500" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 09 19:49:58 2011 -0700" }, "message": "PCI: Remove MRRS modification from MPS setting code\n\nModifying the Maximum Read Request Size to 0 (value of 128Bytes) has\nmassive negative ramifications on some devices. Without knowing which\ndevices have this issue, do not modify from the default value when\nwalking the PCI-E bus in pcie_bus_safe mode. Also, make pcie_bus_safe\nthe default procedure.\n\nTested-by: Sven Schnelle \u003csvens@stackframe.org\u003e\nTested-by: Simon Kirby \u003csim@hostway.ca\u003e\nTested-by: Stephen M. Cameron \u003cscameron@beardog.cce.hp.com\u003e\nReported-and-tested-by: Eric Dumazet \u003ceric.dumazet@gmail.com\u003e\nReported-and-tested-by: Niels Ole Salscheider \u003cniels_ole@salscheider-online.de\u003e\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d42162\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5307f6d5fb12fd01f9f321bc4a8fd77e74858647", "tree": "fa0087ac08c4a914e8c3456741d57ddf27534b9a", "parents": [ "a6a5ed0dd36b4977789e888170f96840cc8b4501" ], "author": { "name": "Shyam Iyer", "email": "shyam.iyer.t@gmail.com", "time": "Thu Sep 08 16:41:17 2011 -0500" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 09 19:49:58 2011 -0700" }, "message": "Fix pointer dereference before call to pcie_bus_configure_settings\n\nCommit b03e7495a862 (\"PCI: Set PCI-E Max Payload Size on fabric\")\nintroduced a potential NULL pointer dereference in calls to\npcie_bus_configure_settings due to attempts to access pci_bus self\nvariables when the self pointer is NULL.\n\nTo correct this, verify that the self pointer in pci_bus is non-NULL\nbefore dereferencing it.\n\nReported-by: Stanislaw Gruszka \u003csgruszka@redhat.com\u003e\nSigned-off-by: Shyam Iyer \u003cshyam_iyer@dell.com\u003e\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "debc3b778508f59696ff188f0feca271dcbfa7d9", "tree": "539664ef0a6ce55aff6a43ae33da149c52090b63", "parents": [ "9e8bf93a7f416a3fa8fb6d76177d90e67bd45496" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Tue Aug 02 00:01:18 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Aug 02 08:53:00 2011 -0700" }, "message": "PCI: export pcie_bus_configure_settings symbol\n\npcie_bus_configure_settings needs to be exported if the PCI hotplug\ndriver is being compiled as a module.\n\nReported-by: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b03e7495a862b028294f59fc87286d6d78ee7fa1", "tree": "836fbfc2b0e34f034cb273c4d065baba3a65178c", "parents": [ "5f66d2b58ca879e70740c82422354144845d6dd3" ], "author": { "name": "Jon Mason", "email": "mason@myri.com", "time": "Wed Jul 20 15:20:54 2011 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Aug 01 11:49:16 2011 -0700" }, "message": "PCI: Set PCI-E Max Payload Size on fabric\n\nOn a given PCI-E fabric, each device, bridge, and root port can have a\ndifferent PCI-E maximum payload size. There is a sizable performance\nboost for having the largest possible maximum payload size on each PCI-E\ndevice. However, if improperly configured, fatal bus errors can occur.\nThus, it is important to ensure that PCI-E payloads sends by a device\nare never larger than the MPS setting of all devices on the way to the\ndestination.\n\nThis can be achieved two ways:\n\n- A conservative approach is to use the smallest common denominator of\n the entire tree below a root complex for every device on that fabric.\n\nThis means for example that having a 128 bytes MPS USB controller on one\nleg of a switch will dramatically reduce performances of a video card or\n10GE adapter on another leg of that same switch.\n\nIt also means that any hierarchy supporting hotplug slots (including\nexpresscard or thunderbolt I suppose, dbl check that) will have to be\nentirely clamped to 128 bytes since we cannot predict what will be\nplugged into those slots, and we cannot change the MPS on a \"live\"\nsystem.\n\n- A more optimal way is possible, if it falls within a couple of\n constraints:\n* The top-level host bridge will never generate packets larger than the\n smallest TLP (or if it can be controlled independently from its MPS at\n least)\n* The device will never generate packets larger than MPS (which can be\n configured via MRRS)\n* No support of direct PCI-E \u003c-\u003e PCI-E transfers between devices without\n some additional code to specifically deal with that case\n\nThen we can use an approach that basically ignores downstream requests\nand focuses exclusively on upstream requests. In that case, all we need\nto care about is that a device MPS is no larger than its parent MPS,\nwhich allows us to keep all switches/bridges to the max MPS supported by\ntheir parent and eventually the PHB.\n\nIn this case, your USB controller would no longer \"starve\" your 10GE\nEthernet and your hotplug slots won\u0027t affect your global MPS.\nAdditionally, the hotplugged devices themselves can be configured to a\nlarger MPS up to the value configured in the hotplug bridge.\n\nTo choose between the two available options, two PCI kernel boot args\nhave been added to the PCI calls. \"pcie_bus_safe\" will provide the\nformer behavior, while \"pcie_bus_perf\" will perform the latter behavior.\nBy default, the latter behavior is used.\n\nNOTE: due to the location of the enablement, each arch will need to add\ncalls to this function. This patch only enables x86.\n\nThis patch includes a number of changes recommended by Benjamin\nHerrenschmidt.\n\nTested-by: Jordan_Hargrave@dell.com\nSigned-off-by: Jon Mason \u003cmason@myri.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f85f19de90a9997583bb26e6f1f9297a4e152c18", "tree": "2dfe61dab6c39ca202f114cb68c68978da1624e3", "parents": [ "b993fdbc7fe26f96b59003a3552c418a71aa0a9f", "7b87c9df5602efd6c7edeb291bbd104d49a6babf" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 29 23:35:05 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 29 23:35:05 2011 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: remove printks about disabled bridge windows\n PCI: fold pci_calc_resource_flags() into decode_bar()\n PCI: treat mem BAR type \"11\" (reserved) as 32-bit, not 64-bit, BAR\n PCI: correct pcie_set_readrq write size\n PCI: pciehp: change wait time for valid configuration access\n x86/PCI: Preserve existing pci\u003dbfsort whitelist for Dell systems\n PCI: ARI is a PCIe v2 feature\n x86/PCI: quirks: Use pci_dev-\u003erevision\n PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.\n PCI hotplug: cpqphp: use pci_dev-\u003evendor\n PCI hotplug: cpqphp: use pci_dev-\u003esubsystem_{vendor|device}\n x86/PCI: config space accessor functions should not ignore the segment argument\n PCI: Assign values to \u0027pci_obff_signal_type\u0027 enumeration constants\n x86/PCI: reduce severity of host bridge window conflict warnings\n PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI\n PCI: PCIe AER: add aer_recover_queue\n x86/PCI: select direct access mode for mmconfig option\n PCI hotplug: Rename is_ejectable which also exists in dock.c\n" }, { "commit": "acb41c0f928fdb84a1c3753ac92c534a2a0f08d2", "tree": "4bf92f1c2b1f36fa68d3e77d646b04b863e1a7e4", "parents": [ "8181780c163e7111f15619067cfa044172d532e1", "ef3b4f8cc20e80c767e47b848fb7512770ab80d7" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 22 14:54:02 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jul 22 14:54:02 2011 -0700" }, "message": "Merge branch \u0027of-pci\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc\n\n* \u0027of-pci\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:\n pci/of: Consolidate pci_bus_to_OF_node()\n pci/of: Consolidate pci_device_to_OF_node()\n x86/devicetree: Use generic PCI \u003c-\u003e OF matching\n microblaze/pci: Move the remains of pci_32.c to pci-common.c\n microblaze/pci: Remove powermac originated cruft\n pci/of: Match PCI devices to OF nodes dynamically\n" }, { "commit": "7b87c9df5602efd6c7edeb291bbd104d49a6babf", "tree": "9fe9167f4492cf05c4e1b38ccf21ab8404900cb4", "parents": [ "28c6821a0f8e686d4f1a6107d970705d37475d87" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 14 13:04:40 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 09:08:07 2011 -0700" }, "message": "PCI: remove printks about disabled bridge windows\n\nI don\u0027t think there\u0027s enough value in the fact of a bridge window\nbeing disabled to justify cluttering the dmesg log with it.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28c6821a0f8e686d4f1a6107d970705d37475d87", "tree": "a62ab9151df067e2976c402944a08b02b8521ee9", "parents": [ "8d6a6a47636648754dc371b01228520a2adaf430" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 14 13:04:35 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 09:08:01 2011 -0700" }, "message": "PCI: fold pci_calc_resource_flags() into decode_bar()\n\ndecode_bar() and pci_calc_resource_flags() both looked at the PCI BAR\ntype information, and it\u0027s simpler to just do it all in one place.\n\ndecode_bar() sets IORESOURCE_IO, IORESOURCE_MEM, and IORESOURCE_MEM_64\nas appropriate, so res-\u003eflags contains all the information pci_bar_type\ndoes, so we don\u0027t need to test the pci_bar_type return value.\n\ndecode_bar() used to return pci_bar_type, which we no longer need. We\ncan simplify it a bit by returning the struct resource flags rather than\nupdating them internally.\n\nIn pci_update_resource(), there\u0027s no need to decode the BAR type bits\nagain; we can just test for IORESOURCE_MEM_64 directly.\n\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8d6a6a47636648754dc371b01228520a2adaf430", "tree": "5bab37b155798d9db8549fe6ee28499b1a5633c5", "parents": [ "c9b378c7cbf623649e4ca64f955f2afd12ef01b2" ], "author": { "name": "Bjorn Helgaas", "email": "bhelgaas@google.com", "time": "Tue Jun 14 13:04:29 2011 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 09:06:58 2011 -0700" }, "message": "PCI: treat mem BAR type \"11\" (reserved) as 32-bit, not 64-bit, BAR\n\nThis fixes a minor regression where broken PCI devices that use the\nreserved \"11\" memory BAR type worked before e354597cce but not after.\n\nThe low four bits of a memory BAR are \"PTT0\" where P\u003d1 for prefetchable\nBARs, and TT is as follows:\n\n 00 32-bit BAR, anywhere in lower 4GB\n 01 anywhere below 1MB (reserved as of PCI 2.2)\n 10 64-bit BAR\n 11 reserved\n\nPrior to e354597cce, we treated \"0100\" as a 64-bit BAR and all others,\nincluding prefetchable 64-bit BARs (\"1100\") as 32-bit BARs. The e354597cce\nfix, which appeared in 2.6.28, treats \"x1x0\" as 64-bit BARs, so the\nreserved \"x110\" types are treated as 64-bit instead of 32-bit.\n\nThis patch returns to treating the reserved \"11\" type as a 32-bit BAR and\nadds a warning if we see it.\n\nIt also logs a note if we see a 1M BAR. This is not a warning, because\nsuch hardware conforms to pre-PCI 2.2 spec, but I think it\u0027s worth noting\nbecause Linux ignores the 1M restriction if it ever has to assign the BAR.\n\nCC: Peter Chubb \u003cpeterc@gelato.unsw.edu.au\u003e\nBugzilla: https://bugzilla.kernel.org/show_bug.cgi?id\u003d35952\nReported-by: Jan Zwiegers \u003cjan@radicalsystems.co.za\u003e\nSigned-off-by: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b1a98b695b4efe10067d0e1cb5b66146a4e517bf", "tree": "102d98bae1ffdd17a2090bcfee6b42c2c4bf39dd", "parents": [ "0918472ceeffad234df5589e45b646a94476f835" ], "author": { "name": "Tiejun Chen", "email": "tiejun.chen@windriver.com", "time": "Thu Jun 02 11:02:50 2011 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 22 08:25:38 2011 -0700" }, "message": "PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI\n\nWhen hot-plugging a root bridge, we always prevent assigning a bus number\nthat already exists. This makes sure we don\u0027t step over an existing bus.\nBut sometimes we only remove PCI device in PCI hieratchy of OS, i,e.\n\necho 1 \u003e /sys/bus/pci/devices/.../remove\n\nbut actually don\u0027t hotplug this device out the platform, so in this case\nwe still should re-scan this bus to enumerate this device when re-scanning\nPCI again.\n\nSigned-off-by: Tiejun Chen \u003ctiejun.chen@windriver.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "98d9f30c820d509145757e6ecbc36013aa02f7bc", "tree": "dd5da915d991352ced56ed849612029339f64198", "parents": [ "1fa7b6a29c61358cc2ca6f64cef4aa0e1a7ca74c" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Mon Apr 11 11:37:07 2011 +1000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Jun 08 09:08:17 2011 +1000" }, "message": "pci/of: Match PCI devices to OF nodes dynamically\n\npowerpc has two different ways of matching PCI devices to their\ncorresponding OF node (if any) for historical reasons. The ppc64 one\ndoes a scan looking for matching bus/dev/fn, while the ppc32 one does a\nscan looking only for matching dev/fn on each level in order to be\nagnostic to busses being renumbered (which Linux does on some\nplatforms).\n\nThis removes both and instead moves the matching code to the PCI core\nitself. It\u0027s the most logical place to do it: when a pci_dev is created,\nwe know the parent and thus can do a single level scan for the matching\ndevice_node (if any).\n\nThe benefit is that all archs now get the matching for free. There\u0027s one\nhook the arch might want to provide to match a PHB bus to its device\nnode. A default weak implementation is provided that looks for the\nparent device device node, but it\u0027s not entirely reliable on powerpc for\nvarious reasons so powerpc provides its own.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Michal Simek \u003cmonstr@monstr.eu\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5aceca9d3cbdacbd017712513387d930f9f944d9", "tree": "026fbf89f4f5e077d865561b631bcc5210f32871", "parents": [ "af0d6a0a3a30946f7df69c764791f1b0643f7cd6" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon May 23 17:12:22 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue May 31 14:29:26 2011 -0700" }, "message": "PCI: Fix warning in drivers/pci/probe.c on sparc64\n\nIO_SPACE_LIMIT is currently used in two ways:\n\n1) As a way to mask I/O port values read out of PCI base address\n registers. This value should be 64-bit.\n\n2) As a value which is the upper limit for all I/O \"ports\" in the\n system.\n\nOn sparc64 we store the full 64-bit physical I/O address in the\nresources. For this reason we define IO_SPACE_LIMIT at a 64-bit\n\"all 1\u0027s\".\n\nThis is the right value to use for ioport_resource.end and for the\ncheck made in drivers/pcmcia/rsrc_nonstatic.c:adjust_io().\n\nBut in driver/pci/probe.c:__pci_read_base() we mask this against\na \"u32\" variable and thus get the following warning:\n\ndrivers/pci/probe.c: In function ¡__pci_read_base¢:\ndrivers/pci/probe.c:207: warning: large integer implicitly truncated to unsigned type\n\nFix this by using an explicit \"u32\" cast.\n\nI considered changing sparc64 to define a 32-bit \"all 1\u0027s\" like\nmost other systems do, but this wouldn\u0027t work because the checks\nin PCMCIA\u0027s rsrc_nonstatic.c would no longer be right since they\nare testing against fully formed 64-bit resources. As described\nabove, on sparc64 such resources will hold full 64-bit physical\nI/O addresses, not bus-centric 32-bit ones.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dc2c2c9dd513dec6c17df04e8abff795e20a5271", "tree": "096e73fc6775edbe389c687df08f96bd85788d02", "parents": [ "b9d320fcb6259baffaeaf93a5fce252cd09333d6" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu May 12 17:11:40 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:17:13 2011 -0700" }, "message": "PCI/sysfs: move bus cpuaffinity to class dev_attrs\n\nRequested by Greg KH to fix a race condition in the creating of PCI bus\ncpuaffinity files.\n\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b9d320fcb6259baffaeaf93a5fce252cd09333d6", "tree": "c5372d704719ff2c6f7b8d2b6bb3c04901cde242", "parents": [ "da7822e5ad71ec9b745b412639f1e5e0ba795a20" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu May 12 17:11:39 2011 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sat May 21 12:17:12 2011 -0700" }, "message": "PCI: add rescan to /sys/.../pci_bus/.../\n\nAfter remove the device from /sys, we have to rescan all or\nfind out the bridge and access /sys../device/rescan there.\n\nthis patch add /sys/.../pci_bus/.../rescan. So user can rescan more easy.\nthat is more clean and easy to understand.\n\nlike after remove 0000:c4:00.0, you can rescan 0000:c4 directly.\n\n-v2: According to Jesse, use function instead of exposing attr, so could hide\n\t#ifdef in header file.\n also add code to remove rescan file in remove path.\n-v3: GregKH pointed out that we should use dev_attrs to avoid racing.\n So add pcibus_attrs and make it to be member of pcibus_attrs.\n-v4: Change name to pcibus_dev_attrs according to GregKH\n\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7c867c8899e873652ef98a890d2e647c092bec25", "tree": "482e3c673dd58243be6ed73915fd0c92dc44ca9a", "parents": [ "c13ff2ff3ad1479f222e18f9caba3db5af68d549" ], "author": { "name": "Jesper Juhl", "email": "jj@chaosbits.net", "time": "Mon Jan 24 21:14:33 2011 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 08 13:08:05 2011 -0800" }, "message": "PCI: Avoid potential NULL pointer dereference in pci_scan_bridge\n\npci_add_new_bus() calls pci_alloc_child_bus() which calls pci_alloc_bus()\nthat allocates memory dynamically with kzalloc(). The return value of\nkzalloc() is the pointer that\u0027s eventually returned from\npci_add_new_bus(), so since kzalloc() can fail and return NULL so can\npci_add_new_bus(). Thus we may end up dereferencing a NULL pointer in\ndrivers/pci/probe.c::pci_scan_bridge(). Seems to me we should test for\nthis and bail out if it happens rather than crashing.\nAlso removed some trailing whitespace that bugged me while looking at\nthis.\n\nSigned-off-by: Jesper Juhl \u003cjj@chaosbits.net\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2c6413aee215a43b1f95e218067abcde50ccbc5e", "tree": "c36c18db030ee0af60642aaac4df78973ab7be97", "parents": [ "cb04e95bdd0bfd618ab731c84a3ab56b56974df8" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Sep 29 12:23:21 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sun Oct 17 20:03:05 2010 -0700" }, "message": "PCI: log vendor/device ID always\n\nPreviously we had to have CONFIG_PCI_DEBUG\u003dy or CONFIG_DYNAMIC_DEBUG\u003dy\nto turn on this printk, but I think the IDs are valuable enough that it\u0027s\nworth putting them in the log always.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "253d2e549818f5a4a52e2db0aba3dacee21e5b38", "tree": "535ff224cb89860809fa5d948e19e1f3342cf7b3", "parents": [ "fcd097f31a6ee207cc0c3da9cccd2a86d4334785" ], "author": { "name": "Jacob Pan", "email": "jacob.jun.pan@linux.intel.com", "time": "Fri Jul 16 10:19:22 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:35 2010 -0700" }, "message": "PCI: disable mmio during bar sizing\n\nIt is a known issue that mmio decoding shall be disabled while doing PCI\nbar sizing. Host bridge and other devices (PCI PIC) shall be excluded for\ncertain platforms. This patch mainly comes from Mathew Willcox\u0027s\npatch in http://kerneltrap.org/mailarchive/linux-kernel/2007/9/13/258969.\n\nA new flag bit \"mmio_alway_on\" is added to pci_dev with the intention that\ndevices with their mmio decoding cannot be disabled during BAR sizing shall\nhave this bit set, preferrablly in their quirks.\n\nWithout this patch, Intel Moorestown platform graphics unit will be\ncorrupted during bar sizing activities.\n\nSigned-off-by: Jacob Pan \u003cjacob.jun.pan@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "affb72c3a8984ba55e055b0a0228c3ea1a056758", "tree": "a6d4c9051110c03f9222bde9c3dcea7822f8570c", "parents": [ "ea8c071cad789b1919355fc7a67182a5c9994e6b" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue May 18 14:35:16 2010 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed May 19 22:40:14 2010 -0400" }, "message": "ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n\nNow, a dedicated HEST tabling parsing code is used for PCIE AER\nfirmware_first setup. It is rebased on general HEST tabling parsing\ncode of APEI. The firmware_first setup code is moved from PCI core to\nAER driver too, because it is only AER related.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "45aa23b4cbd37408678c96cd113241860d3321f6", "tree": "be7881f74ca8c7c1571fe42af09d63493fb5a787", "parents": [ "4352aa5bbf1d0080c2dcf904ce1e4be0a1cb5937" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Thu Apr 22 09:02:43 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Apr 22 16:13:16 2010 -0700" }, "message": "PCI: revert broken device warning\n\nThis reverts c519a5a7dab2d. That change added a warning about devices that\ndidn\u0027t respond correctly when sizing BARs, which helped diagnose broken\ndevices. But the test wasn\u0027t specific enough, so it also complained about\nworking devices with zero-size BARs, e.g.,\nhttps://bugzilla.kernel.org/show_bug.cgi?id\u003d15822\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c519a5a7dab2d8e9a114f003e2d369bcf8e913f3", "tree": "2f0ebf4123b9b66b8068b8532334bad0f5cd0d84", "parents": [ "e1944c6b0fba80a7837c1cbc47dfbf46e1274a4b" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Fri Mar 19 14:56:27 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Mar 24 13:21:36 2010 -0700" }, "message": "PCI: complain about devices that seem to be broken\n\nIf we can tell that a device isn\u0027t working correctly, we should tell\nthe user to make debugging easier. Otherwise, it can take a lot of\nwork to determine whether the problem is in the driver, PCMCIA, PCI,\nhardware, etc., as in http://bugzilla.kernel.org/show_bug.cgi?id\u003d12006\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7b8ff6da028232aadae6bcc7c7406c8966d0b3c4", "tree": "c0bab7d872f6e8907d6bdf473f7fbedcfaf83081", "parents": [ "99ddd552fef7e6e3b7dc76ba8fee9ea5869d1e14" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Mar 16 15:53:03 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Mar 24 13:21:35 2010 -0700" }, "message": "PCI: make disabled window printk style match the enabled ones\n\nNo functional change; this just tweaks the changes from 349e1823a405\nso the new printks for disabled PCI-to-PCI bridge windows match the\nones for the enabled windows.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCC: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "99ddd552fef7e6e3b7dc76ba8fee9ea5869d1e14", "tree": "efdfc780d0993ab3e62888000bd3ff5f38508602", "parents": [ "966f3a7570447c5025d67a618d408e68a3ae3167" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Mar 16 15:52:58 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Mar 24 13:21:35 2010 -0700" }, "message": "PCI: break out primary/secondary/subordinate for readability\n\nNo functional change; just add names for the primary/secondary/subordinate\nbus numbers read from config space rather than repeatedly masking/shifting.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a1e4d72cd3024999bfb6703092ea271438805c89", "tree": "853a289d73ad9ffb04038fc493d209e980a3ef9b", "parents": [ "09c09bc618a4ceec387c57542031b4fc35826e16" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Feb 08 19:16:33 2010 +0100" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Feb 26 20:39:12 2010 +0100" }, "message": "PM: Allow PCI devices to suspend/resume asynchronously\n\nSet power.async_suspend for all PCI devices and PCIe port services,\nso that they can be suspended and resumed in parallel with other\ndevices they don\u0027t depend on in a known way (i.e. devices which are\nnot their parents or children).\n\nThis only affects the \"regular\" suspend and resume stages, which\nmeans in particular that the restoration of the PCI devices\u0027 standard\nconfiguration registers during resume will still be carried out\nsynchronously (at the \"early\" resume stage).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "2fe2abf896c1e7a0ee65faaf3ef0ce654848abbd", "tree": "f066d5c94bbed5ca3556b4d2f0c4b3a9795b6eff", "parents": [ "89a74ecccd1f78e51faf6287e5c0e93a92ac096e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:36 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:37 2010 -0800" }, "message": "PCI: augment bus resource table with a list\n\nPreviously we used a table of size PCI_BUS_NUM_RESOURCES (16) for resources\nforwarded to a bus by its upstream bridge. We\u0027ve increased this size\nseveral times when the table overflowed.\n\nBut there\u0027s no good limit on the number of resources because host bridges\nand subtractive decode bridges can forward any number of ranges to their\nsecondary buses.\n\nThis patch reduces the table to only PCI_BRIDGE_RESOURCE_NUM (4) entries,\nwhich corresponds to the number of windows a PCI-to-PCI (3) or CardBus (4)\nbridge can positively decode. Any additional resources, e.g., PCI host\nbridge windows or subtractively-decoded regions, are kept in a list.\n\nI\u0027d prefer a single list rather than this split table/list approach, but\nthat requires simultaneous changes to every architecture. This approach\nonly requires immediate changes where we set up (a) host bridges with more\nthan four windows and (b) subtractive-decode P2P bridges, and we can\nincrementally change other architectures to use the list.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2adf75160b10bf3f09ed7d3d04e937f923fc557e", "tree": "db2998c5403f6c12bb207fd80a1e1fca2ec4a1b4", "parents": [ "fa27b2d108fa49685129867a8c5b968344d6e197" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:26 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:25 2010 -0800" }, "message": "PCI: read bridge windows before filling in subtractive decode resources\n\nNo functional change; this fills in the bus subtractive decode resources\nafter reading the bridge window information rather than before. Also,\nprint out the subtractive decode resources as we already do for the\npositive decode windows.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fa27b2d108fa49685129867a8c5b968344d6e197", "tree": "442356bc1afa2aacf1afc7e53ebc9aca8a14903d", "parents": [ "b16694f70c40ea8d539cdc93a422039771e85870" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:21 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:17 2010 -0800" }, "message": "PCI: split up pci_read_bridge_bases()\n\nNo functional change; this breaks up pci_read_bridge_bases() into separate\npieces for the I/O, memory, and prefetchable memory windows, similar to how\nYinghai recently split up pci_setup_bridge() in 68e84ff3bdc.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cd81e1ea1a4cda94aa5f3e942301cf0da497c262", "tree": "91f271f961f560e62f1e0790e766f98afc287a00", "parents": [ "568ddef8735d4a51a521ba6af026ee0c32281566" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Jan 22 01:02:22 2010 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:21 2010 -0800" }, "message": "PCI: reject mmio ranges starting at 0 on pci_bridge read\n\nWe already track unassigned resources in struct resource, and this\nprevents us from overwriting resource flags and info in the unassigned\ncase.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4fb88c1a28a8dc302bdc09858e7cdafc97bef794", "tree": "cd2d6ff98626d6d8782edd848c357bc4607ece17", "parents": [ "0bf01c3c86d4b9ea279d6215420484db887f5db5" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Jan 17 14:01:41 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:17 2010 -0800" }, "message": "PCI: Make pci_scan_slot more robust\n\nYinghai pointed out that the new pci_scan_slot() crashes when called\non an ARI-capable slot that is empty. Fix this by exiting early from\npci_scan_slot if there is no device in the slot.\n\nAlso make next_ari_func() robust against devices not existing in case\nthe ARI capability is corrupt. ARI also requires that the devices be\nlisted in order, so if we find a function listed that is out of order,\nstop scanning to prevent loops.\n\nSigned-off-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9dfd97fe12f79ec8b68feb63912a4ef2f31f571a", "tree": "845515c430a3cc48b1d88496d3b8f4d13bd7efb2", "parents": [ "45b4cdd57ef0e57555b2ab61b584784819b39365" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:35 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for reporting PCIe 3.0 speeds\n\nAdd the 8.0 GT/s speed.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45b4cdd57ef0e57555b2ab61b584784819b39365", "tree": "1e08008e0cdc57252022b5ad1a0e3029c7e96f99", "parents": [ "9be60ca0497a2563662fde4c9007841c3b79a742" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:34 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for AGP in cur/max bus speed\n\nTake advantage of some gaps in the table to fit in support for AGP speeds.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9be60ca0497a2563662fde4c9007841c3b79a742", "tree": "d31bc38997f7591d818d478ba91a7f07dee9bede", "parents": [ "3749c51ac6c1560aa1cb1520066bed84c6f8152a" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:33 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:18 2010 -0800" }, "message": "PCI: Add support for detection of PCIe and PCI-X bus speeds\n\nBoth PCIe and PCI-X bridges report their secondary bus speed in their\nrespective capabilities.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3749c51ac6c1560aa1cb1520066bed84c6f8152a", "tree": "3cbfb6a6d2df821e3e80ccce29ede8011b94246e", "parents": [ "536c8cb49eccd4f753b4782e7e975ef87359cb44" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:32 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:17 2010 -0800" }, "message": "PCI: Make current and maximum bus speeds part of the PCI core\n\nMove the max_bus_speed and cur_bus_speed into the pci_bus. Expose the\nvalues through the PCI slot driver instead of the hotplug slot driver.\nUpdate all the hotplug drivers to use the pci_bus instead of their own\ndata structures.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f07852d6442c46c50b59c7e2acc8a1b291f9ab6d", "tree": "d855a7bc7df8f3e84f1d267e060537ec011477c6", "parents": [ "bee415ce427d1eab6cfb30221461c7d20cbf1903" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:10:02 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:16 2010 -0800" }, "message": "PCI: Rewrite pci_scan_slot\n\nThe Alternate Routing-ID Interpretation capability allows a single device\nto have up to 256 functions. They can be populated sparsely, so the\ncurrent technique of scanning every eighth function is not guaranteed\nto find them all. By introducing a \u0027next_fn\u0027 function pointer, we can\nuse the linked list of functions in the ARI capability to scan all the\nfunctions which exist.\n\nWe can then speed up the pci_scan_slot by skipping the scan of subsequent\ndevfns for PCIe devices which are the direct children of Root Ports or\nDownstream Ports. These devices are only permitted to implement device\n0, unless they are ARI devices, in which case they\u0027ll be scanned by the\nARI code above.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bb209c8287d2d55ec4a67e3933346e0a3ee0da76", "tree": "2e444f273e631fa4dded4ee13ac779565e5efb43", "parents": [ "b04da8bfdfbbd79544cab2fadfdc12e87eb01600" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Jan 26 17:10:03 2010 +0000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Jan 29 16:51:10 2010 +1100" }, "message": "powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge()\n\nWe are missing these when building the pci_dev from scratch off\nthe Open Firmware device-tree\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5d990b627537e59a3a2f039ff588a4750e9c1a6a", "tree": "8c0e723c3f9146da52b30c087a80fc417df2b41b", "parents": [ "b26a34aa4792b3db2500b8a98cb7702765c1a92e" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Dec 04 12:15:21 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:19:24 2009 -0800" }, "message": "PCI: add pci_request_acs\n\nCommit ae21ee65e8bc228416bbcc8a1da01c56a847a60c \"PCI: acs p2p upsteram\nforwarding enabling\" doesn\u0027t actually enable ACS.\n\nAdd a function to pci core to allow an IOMMU to request that ACS\nbe enabled. The existing mechanism of using iommu_found() in the pci\ncore to know when ACS should be enabled doesn\u0027t actually work due to\ninitialization order; iommu has only been detected not initialized.\n\nHave Intel and AMD IOMMUs request ACS, and Xen does as well during early\ninit of dom0.\n\nCc: Allen Kay \u003callen.m.kay@intel.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "06a1cbafb253c4c60d6a54a994887f5fbceabcc0", "tree": "e534c369ab1878a5d86996c29d629d1f5d8f9f75", "parents": [ "d7b7e60526d54da4c94afe5f137714cee7d05c41" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:30:56 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:12 2009 -0800" }, "message": "PCI: use pci_pcie_cap() in pci core\n\nUse pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI core code. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0efea0006335a2425b1a12a2ad35efad626fe353", "tree": "d139b06a32665ec1227c06f1c0a14b21e3c0d654", "parents": [ "1e5ad9679016275d422e36b12a98b0927d76f556" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Thu Nov 05 12:05:11 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 13:59:02 2009 -0800" }, "message": "PCI: cache PCIe capability offset\n\nThere are a lot of codes that searches PCI express capability offset\nin the PCI configuration space using pci_find_capability(). Caching it\nin the struct pci_dev will reduce unncecessary search. This patch adds\nan additional \u0027pcie_cap\u0027 fields into struct pci_dev, which is\ninitialized at pci device scan time (in set_pcie_port_type()).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "865df576e8fc70daf297b53e61a4fbefc719d065", "tree": "59abb13e1dd402bf8cb4496ab94bbceb2ac2ee2b", "parents": [ "0207c356ef0e2bae6ce4603080d42c130d7debc6" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:57 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:44 2009 -0800" }, "message": "PCI: improve discovery/configuration messages\n\nThis makes PCI resource management messages more consistent and adds a few\nnew messages to aid debugging.\n\nWhenever we assign resources to a device, update a BAR, or change a\nbridge aperture, it\u0027s worth noting it.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0207c356ef0e2bae6ce4603080d42c130d7debc6", "tree": "504e801b50b3a0a3782f1749e72468c84e788cf7", "parents": [ "2a6bed8301f8b019717504575a3f9c6cce1fe271" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:52 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:44 2009 -0800" }, "message": "PCI: replace pr_debug with dev_dbg\n\nSince we have a struct device, we might as well use dev_printk. Note that\nboth pr_debug() and dev_dbg() are completely compiled out unless DEBUG or\nDYNAMIC_DEBUG is defined.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7dabef8a2c59e6a3de9d66fc35fb6a43ef7172d", "tree": "0f8b0021e693a0e380ef9026083b59d0909dffc6", "parents": [ "4fd8bdc567e70c02fab7eeaaa7d2a64232add789" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Oct 27 13:26:47 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:41 2009 -0800" }, "message": "vsprintf: use %pR, %pr instead of %pRt, %pRf\n\nJesse accidentally applied v1 [1] of the patchset instead of v2 [2]. This\nis the diff between v1 and v2.\n\nThe changes in this patch are:\n - tidied vsprintf stack buffer to shrink and compute size more\n accurately\n - use %pR for decoding and %pr for \"raw\" (with type and flags) instead\n of adding %pRt and %pRf\n\n[1] http://lkml.org/lkml/2009/10/6/491\n[2] http://lkml.org/lkml/2009/10/13/441\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bc577d2bb98cc44371287fce3e892d26ad4050a8", "tree": "801ff1dbf10301bda75879141482eb226192e280", "parents": [ "0584396157ad2d008e2cc76b4ed6254151183a25" ], "author": { "name": "Gabe Black", "email": "gabe.black@ni.com", "time": "Tue Oct 06 10:45:19 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:36 2009 -0800" }, "message": "PCI: populate subsystem vendor and device IDs for PCI bridges\n\nChange to populate the subsystem vendor and subsytem device IDs for\nPCI-PCI bridges that implement the PCI Subsystem Vendor ID capability.\nPreviously bridges left subsystem vendor IDs unpopulated.\n\nSigned-off-by: Gabe Black \u003cgabe.black@ni.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0584396157ad2d008e2cc76b4ed6254151183a25", "tree": "8860a033938b1a01cccf9a203208f741758724ac", "parents": [ "8792e11f1c54bcba34412f03959e70ee217f2231" ], "author": { "name": "Matt Domsch", "email": "Matt_Domsch@dell.com", "time": "Mon Nov 02 11:51:24 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:25 2009 -0800" }, "message": "PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode\n\nFeedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This\ncorrectly handles PCI-X bridges, PCIe root ports and endpoints, and\nprints debug messages when invalid/reserved types are found in the\nHEST. PCI devices not in domain/segment 0 are not represented in\nHEST, thus will be ignored.\n\nToday, the PCIe Advanced Error Reporting (AER) driver attaches itself\nto every PCIe root port for which BIOS reports it should, via ACPI\n_OSC.\n\nHowever, _OSC alone is insufficient for newer BIOSes. Part of ACPI\n4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way\nfor OS and BIOS to handshake over which errors for which components\neach will handle. One table in ACPI 4.0 is the Hardware Error Source\nTable (HEST), where BIOS can define that errors for certain PCIe\ndevices (or all devices), should be handled by BIOS (\"Firmware First\nmode\"), rather than be handled by the OS.\n\nDell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so\nthat it may manage such errors, log them to the System Event Log, and\npossibly take other actions. The aer driver should honor this, and\nnot attach itself to devices noted as such.\n\nFurthermore, Kenji Kaneshige reminded us to disallow changing the AER\nregisters when respecting Firmware First mode. Platform firmware is\nexpected to manage these, and if changes to them are allowed, it could\nbreak that firmware\u0027s behavior.\n\nThe HEST parsing code may be replaced in the future by a more\nfeature-rich implementation. This patch provides the minimum needed\nto prevent breakage until that implementation is available.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ed6743918abbec69c0f0b725fa56e3c3248bbab", "tree": "01ea3d9aaf84746e42c4852c7e3c5295e1b42ce0", "parents": [ "af5a8ee05404112f38fb2904747c688bdc31a746" ], "author": { "name": "Michael S. Tsirkin", "email": "mst@redhat.com", "time": "Thu Oct 29 17:24:59 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:59:40 2009 -0800" }, "message": "PCI: fix nit in ROM BAR size probing\n\nWhen probing for ROM BAR size, we should not change bits 1:10 in this\nBAR, because these bits are marked as \"reserved for future use\" in PCI\nspec, so changing them might have side effects.\n\nNo such issue for I/O or memory, as there is an implementation note in\nPCI spec which explicitly allows writing 0xfffffffff there.\n\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "df0e97c6f1f2fdca686036998fe816cefd8e27d7", "tree": "8cef3a9d3dc141b804507fd8eed195ff8196a7c8", "parents": [ "ae21ee65e8bc228416bbcc8a1da01c56a847a60c" ], "author": { "name": "Allen Kay", "email": "allen.m.kay@intel.com", "time": "Wed Oct 07 10:27:51 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:26 2009 -0800" }, "message": "PCI: add xen dom0 checking before ACS initialization\n\nThis patch is predicated on Jeremy\u0027s patch in include/xen/xen.h. It\u0027ll\nprevent ACS init unless the platform has both an IOMMU and we\u0027re running\nas dom0.\n\nSigned-off-by: Allen Kay \u003callen.m.kay@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ae21ee65e8bc228416bbcc8a1da01c56a847a60c", "tree": "cbcd109c764a8fed06f18a0a4bd3d63208405552", "parents": [ "1ccbf5344c3daef046d2323190cc6807c44f1917" ], "author": { "name": "Allen Kay", "email": "allen.m.kay@intel.com", "time": "Wed Oct 07 10:27:17 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:25 2009 -0800" }, "message": "PCI: acs p2p upsteram forwarding enabling\n\nNote: dom0 checking in v4 has been separated out into 2/2.\n\nThis patch enables P2P upstream forwarding in ACS capable PCIe switches.\nIt solves two potential problems in virtualization environment where a PCIe\ndevice is assigned to a guest domain using a HW iommu such as VT-d:\n\n1) Unintentional failure caused by guest physical address programmed\n into the device\u0027s DMA that happens to match the memory address range\n of other downstream ports in the same PCIe switch. This causes the PCI\n transaction to go to the matching downstream port instead of go to the\n root complex to get translated by VT-d as it should be.\n\n2) Malicious guest software intentionally attacks another downstream\n PCIe device by programming the DMA address into the assigned device\n that matches memory address range of the downstream PCIe port.\n\nWe are in process of implementing device filtering software in KVM/XEN\nmanagement software to allow device assignment of PCIe devices behind a PCIe\nswitch only if it has ACS capability and with the P2P upstream forwarding bits\nenabled. This patch is intended to work for both KVM and Xen environments.\n\nSigned-off-by: Allen Kay \u003callen.m.kay@intel.com\u003e\nReviewed-by: Mathew Wilcox \u003cwilly@linux.intel.com\u003e\nReviewed-by: Chris Wright \u003cchris@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a369c791e881503a6253dafc0d0ad5e41e5557e5", "tree": "20de1e773f328875afbfaf96fedd3991e9288f68", "parents": [ "fd95541e23e2c9acb1e38cd41fc0c7cc37fceb53" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Oct 06 15:33:44 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:18 2009 -0800" }, "message": "PCI: print resources consistently with %pRt\n\nThis uses %pRt to print additional resource information (type, size,\nprefetchability, etc.) consistently.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4b77b0a2ba27d64f58f16d8d4d48d8319dda36ff", "tree": "957f38dc1065e2880197e7ca5ffe1592515010b3", "parents": [ "999cce4a52d5abdda5d2cec6bac241899bc19e4c" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Sep 09 23:49:59 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 13:41:46 2009 -0700" }, "message": "PCI: Clear saved_state after the state has been restored\n\nSome PCI devices fail if their standard configuration registers are\nrestored twice in a row. Prevent this from happening by making\npci_restore_state() clear the saved_state flag of the device right\nafter the device\u0027s standard configuration registers have been\npopulated with the previously saved values.\n\nSimplify PCI PM callbacks by removing the direct clearing of\nstate_saved from them, as it shouldn\u0027t be necessary any more (except\nin pci_pm_thaw(), where it has to be cleared, so that the values saved\nduring the \"freeze\" phase of hibernation are not used later by mistake).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28760489a3f1e136c5ae8581c0fa8f63511f2f4c", "tree": "a3c890e9c8d9e98385691d56f5c007d280514fe5", "parents": [ "0ba379ec0fb182a87b8891c5754abbcd9c035b4f" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@aristanetworks.com", "time": "Wed Sep 09 14:09:24 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:10:24 2009 -0700" }, "message": "PCI: pcie: Ensure hotplug ports have a minimum number of resources\n\nIn general a BIOS may goof or we may hotplug in a hotplug controller.\nIn either case the kernel needs to reserve resources for plugging\nin more devices in the future instead of creating a minimal resource\nassignment.\n\nWe already do this for cardbus bridges I am just adding a variant\nfor pcie bridges.\n\nv2: Make testing for pcie hotplug bridges based on a flag.\n\n So far we only set the flag for pcie but a header_quirk\n could easily be added for the non-standard pci hotplug\n bridges.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@aristanetworks.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d0b8cbed648334924728642eea879878bc930b33", "tree": "2b2efb88e84917b2fa267d8dda97865ca5dca3b7", "parents": [ "6dab62ee5a3bf4f71b8320c09db2e6022a19f40e" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Aug 07 03:53:34 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:27 2009 -0700" }, "message": "PCI: print out pref if mmio is prefetchable\n\nWe already print it out for pci bridges, so also print it out for pci devices.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a7db50405216610c8a0d62b8b400180b6f366733", "tree": "d86aeb344ce4966cf2f7b69c1ec1cd5111372545", "parents": [ "7135a71b19be1faf48b7148d77844d03bc0717d6" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Mon Jun 22 08:08:07 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:18 2009 -0700" }, "message": "PCI: remove pcibios_scan_all_fns()\n\nThis was #define\u0027d as 0 on all platforms, so let\u0027s get rid of it.\n\nThis change makes pci_scan_slot() slightly easier to read.\n\nCc: Yoshinori Sato \u003cysato@users.sourceforge.jp\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nCc: David Howells \u003cdhowells@redhat.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Jeff Dike \u003cjdike@addtoit.com\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nAcked-by: Russell King \u003clinux@arm.linux.org.uk\u003e\nAcked-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nAcked-by: Kyle McMartin \u003ckyle@mcmartin.ca\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9fc39256508c18d2861de11622183dfb6e79de87", "tree": "75c030716b106de4d79e4828f34b8e6b0592b861", "parents": [ "6e3f36df0ffa433e273c89f1447c94382a9db49e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue May 26 16:06:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:31 2009 -0700" }, "message": "PCI: use pci_is_root_bus() in pci_read_bridge_bases()\n\nUse pci_is_root_bus() in pci_read_bridge_bases() to check if the pci\nbus is root, for code consistency.\n\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1f82de10d6b1d845155363c895c552e61b36b51a", "tree": "3e93b9d1c97ae48509133fbbec9c81b4823816a5", "parents": [ "67b5db6502ddd27d65dea43bf036abbd82d0dfc9" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu Apr 23 20:48:32 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:06 2009 -0700" }, "message": "PCI/x86: don\u0027t assume prefetchable ranges are 64bit\n\nWe should not assign 64bit ranges to PCI devices that only take 32bit\nprefetchable addresses.\n\nTry to set IORESOURCE_MEM_64 in 64bit resource of pci_device/pci_bridge\nand make the bus resource only have that bit set when all devices under\nit support 64bit prefetchable memory. Use that flag to allocate\nresources from that range.\n\nReported-by: Yannick \u003cyannick.roehlly@free.fr\u003e\nReviewed-by: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f79b1b146b52765ee38bfb91bb14eb850fa98017", "tree": "6085fffb1442801293b8132b5d3f2aa735d0abdd", "parents": [ "9fa7eb283c5cdc2b0f4a8cfe6387ed82e5e9a3d3" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Thu May 28 00:25:05 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 04 11:29:43 2009 +0100" }, "message": "PCI: use fixed-up device class when configuring device\n\nThe device class may be changed after the fixup, so re-read the class\nvalue from pci_dev when configuring the device. Otherwise some devices\nsuch as JMicron SATA controller won\u0027t work.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nTested-by: Marc Dionne \u003cmarc.c.dionne@gmail.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0bb1be3e30bfc3e09fa0ff1e887ac7da4a16c3a2", "tree": "997b7e0dd0579c3aed6337c9ae24106ccab163b7", "parents": [ "044cd80942e47b9de0915b627902adf05c52377f" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Thu Apr 16 13:31:10 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Apr 22 13:57:36 2009 -0700" }, "message": "x86/PCI: Move set_pci_bus_resources_arch_default into arch/x86\n\nCommit 30a18d6c3f1e774de656ebd8ff219d53e2ba4029 introduced a new\nfunction to set the PCI bus resources. Unfortunately, neither the\nauthor, nor the committers seemed to know that we already have somewhere\nto do that -- pcibios_fixup_bus(). This patch moves the hook (used only\nby the K8 code) into x86-specific code where it should have been in the\nfirst place.\n\nCc: Yinghai Lu \u003cyinghai.lu@sun.com\u003e\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5446a6bdb51e71da7a203e395b0b4c668d559a3a", "tree": "ac403024a02a2285defd433da068dc4415af0fbe", "parents": [ "52a8873ba4e82d6e87f8478b3e7f9c12d8b37c38" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Wed Apr 01 18:24:12 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Apr 06 11:26:07 2009 -0700" }, "message": "PCI: annotate pci_rescan_bus as __ref, not __devinit\n\npci_rescan_bus was annotated as __devinit, which is wrong,\nbecause it will never be part of device initialization.\nHowevever, we can\u0027t simply drop the annotation, because then we\nget section warnings about calling pci_scan_child_bus (which is\ncorrectly marked as __devinit).\n\npci_rescan_bus will only get built when CONFIG_HOTPLUG is set,\nmeaning that __devinit is a nop, so we know that pci_scan_child_bus\nhas not been freed.\n\nAnnotate as __ref to silence modpost.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "853346e4354c948b50a6fb0002f8af2cf5fbf2ae", "tree": "b577bc1e79a44c471635559f0bcbfce424309f73", "parents": [ "ceb93a9ff16612314d757874b6415ffbb2091576" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Mar 21 22:05:11 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Mar 26 15:50:18 2009 -0700" }, "message": "PCI: fix conflict between SR-IOV and config space sizing\n\nNew pci_cfg_space_size() needs invalid pdev-\u003eclass, put it in the\nright place in the pci_setup_device().\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "705b1aaa823e800490f157cd9366ad8cff385f5f", "tree": "634ea8ba227a305074938f49c110fea8e68e8bb3", "parents": [ "3ed4fd96b3188406ac5357d9290bcffa08c65cf6" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Fri Mar 20 14:56:31 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:58 2009 -0700" }, "message": "PCI: Introduce /sys/bus/pci/rescan\n\nThis interface allows the user to force a rescan of all PCI buses\nin system, and rediscover devices that have been removed earlier.\n\npci_bus_attrs implementation from Trent Piepho.\n\nThanks to Vegard Nossum for discovering locking issues with the\nsysfs interface.\n\nCc: Trent Piepho \u003cxyzzy@speakeasy.org\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3ed4fd96b3188406ac5357d9290bcffa08c65cf6", "tree": "1e48401b56c35554e84c8d627c6c04e83a999a9e", "parents": [ "9dd90cafa7a712d283e2e0c625b022e19f746762" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Fri Mar 20 14:56:25 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:44 2009 -0700" }, "message": "PCI: Introduce pci_rescan_bus()\n\nThis API is used by the PCI core to rescan a bus and rediscover\nnewly added devices.\n\nOver time, it is expected that the various PCI hotplug drivers\nwill migrate to this interface and away from the old\npci_do_scan_bus() interface.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "74710ded8e16fc8dacbb702a5bac1a493d88549a", "tree": "274171a30a202a708a6aacbf9e0a693a2b5474ad", "parents": [ "1b69dfc649e6658fc38499cf704750d74cabc73d" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Fri Mar 20 14:56:10 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:21 2009 -0700" }, "message": "PCI: always scan child buses\n\nWhile scanning bridges, we stop our scan if we encounter a bus\nthat we\u0027ve seen before, to work around some buggy chipsets. This\nis a good idea, but prevents us from fully scanning the PCI bus\nat a future time (to find newly hot-added devices, for example).\n\nChange the logic so that we skip _re-adding_ an existing bus\nthat we\u0027ve seen before, but also allow the scan to descend to\nall child buses.\n\nNow that we\u0027re potentially scanning our child buses again, we\nalso need to be sure not to attempt re-initializing their BARs\nso we avoid that.\n\nThis patch lays the groundwork to allow the user to issue a\nrescan of the PCI bus at any time.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1b69dfc649e6658fc38499cf704750d74cabc73d", "tree": "57dd8fff34d6be97a8bb19a733d3dc041ab81d0b", "parents": [ "90bdb3117f4209baa6d712b126f0e7791b24dc3f" ], "author": { "name": "Trent Piepho", "email": "xyzzy@speakeasy.org", "time": "Fri Mar 20 14:56:05 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:05 2009 -0700" }, "message": "PCI: pci_scan_slot() returns newly found devices\n\npci_scan_slot() has been rewritten to be less complex and will now\nreturn the number of *new* devices found.\n\nExisting callers need not worry because they already assume that\nthey can\u0027t call pci_scan_slot() on an already-scanned slot.\n\nThus, there is no semantic change for existing callers: returning\nnewly found devices (this patch) is exactly equal to returning all\nfound devices (before this patch).\n\nThis patch adds some more groundwork to allow us to rescan the\nPCI bus during runtime to discover newly added devices.\n\nSigned-off-by: Trent Piepho \u003cxyzzy@speakeasy.org\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "90bdb3117f4209baa6d712b126f0e7791b24dc3f", "tree": "5c2ca7ae062bc8aef2ce0ceb7f49e78b0329fb8a", "parents": [ "79af72d716cf1bb13b175429cf181a6c4d063ee8" ], "author": { "name": "Trent Piepho", "email": "xyzzy@speakeasy.org", "time": "Fri Mar 20 14:56:00 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:56:45 2009 -0700" }, "message": "PCI: don\u0027t scan existing devices\n\npci_scan_single_device is supposed to add newly discovered\ndevices to pci_bus-\u003edevices, but doesn\u0027t check to see if the\ndevice has already been added. This can cause problems if we ever\nwant to use this interface to rescan the PCI bus.\n\nIf the device is already added, just return it.\n\nSigned-off-by: Trent Piepho \u003cxyzzy@speakeasy.org\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "480b93b7837fb3cf0579a42f4953ac463a5b9e1e", "tree": "39206460a790570d293dc04a64ab3fd3fff736ef", "parents": [ "a28724b0fb909d247229a70761c90bb37b13366a" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:14 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:25 2009 -0700" }, "message": "PCI: centralize device setup code\n\nMove the device setup stuff into pci_setup_device() which will be used\nto setup the Virtual Function later.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a28724b0fb909d247229a70761c90bb37b13366a", "tree": "7c5332004a8f52e676076b39aa03aeb45cb03f2a", "parents": [ "8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:13 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:24 2009 -0700" }, "message": "PCI: reserve bus range for SR-IOV device\n\nReserve the bus number range used by the Virtual Function when\npcibios_assign_all_busses() returns true.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d1b054da8f599905f3c18a218961dcf17f9d5f13", "tree": "99b62e6771c3b73142dd0622463bed0e19724342", "parents": [ "8293b0f629095efbe7c7e3f9b437f8c040c19eb5" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:11 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:22 2009 -0700" }, "message": "PCI: initialize and release SR-IOV capability\n\nIf a device has the SR-IOV capability, initialize it (set the ARI\nCapable Hierarchy in the lowest numbered PF if necessary; calculate\nthe System Page Size for the VF MMIO, probe the VF Offset, Stride\nand BARs). A lock for the VF bus allocation is also initialized if\na PF is the lowest numbered PF.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dfadd9edff498d767008edc6b2a6e86a7a19934d", "tree": "155d439bb862292307b88975bf11cfd9b78d7df2", "parents": [ "745be2e700cdddd5da4e402854a484242c3628df" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sun Mar 08 21:35:37 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:17 2009 -0700" }, "message": "PCI/x86: detect host bridge config space size w/o using quirks\n\nMany host bridges support a 4k config space, so check them directy\ninstead of using quirks to add them.\n\nWe only need to do this extra check for host bridges at this point,\nbecause only host bridges are known to have extended address space\nwithout also having a PCI-X/PCI-E caps. Other devices with this\nproperty could be done with quirks (if there are any).\n\nAs a bonus, we can remove the quirks for AMD host bridges with family\n10h and 11h since they\u0027re not needed any more.\n\nWith this patch, we can get correct pci cfg size of new Intel CPUs/IOHs\nwith host bridges.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nAcked-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6a3b3e26803fc823058fbb05abb5e0d92a52e1bd", "tree": "f868b0ef9c3d5d69f693fb73346f7f71266db092", "parents": [ "32a9a682bef2f6fce7026bd94d1ce20028b0e52d" ], "author": { "name": "Geert Uytterhoeven", "email": "geert@linux-m68k.org", "time": "Sun Mar 15 20:14:37 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:15 2009 -0700" }, "message": "PCI: Use kzalloc() in pci_create_bus()\n\nSigned-off-by: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f92d4e29d785f1d4217dee7f1ae6ff7140547ed5", "tree": "55e272ffb250af61e3de804565d538b0cb92b0eb", "parents": [ "151ab36a2ea0b3181d103f7244636e0d16e685de" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Feb 17 14:15:16 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:04 2009 -0700" }, "message": "PCI: fix wrong assumption in pci_read_bridge_bases\n\nCurrent pci_read_bridge_bases() has an assumption that pci_bus-\u003eself\nis NULL on the pci root bus (It checks pci_bus-\u003eself to see if the pci\nbus is root bus). But is might not true on some platforms. We must\ncheck pci_bus-\u003eparent instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4e9b1c184cadbece3694603de5f880b6e35bd7a7", "tree": "8ae2ab8a4eaab4d46b4460284fd5ee475ce9a42d", "parents": [ "0176260fc30842e358cf34afa7dcd9413db44822", "36c401a44abcc389a00f9cd14892c9cf9bf0780d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 10 06:12:18 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 10 06:12:18 2009 -0800" }, "message": "Merge branch \u0027cpus4096-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027cpus4096-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n [IA64] fix typo in cpumask_of_pcibus()\n x86: fix x86_32 builds for summit and es7000 arch\u0027s\n cpumask: use work_on_cpu in acpi-cpufreq.c for read_measured_perf_ctrs\n cpumask: use work_on_cpu in acpi-cpufreq.c for drv_read and drv_write\n cpumask: use cpumask_var_t in acpi-cpufreq.c\n cpumask: use work_on_cpu in acpi/cstate.c\n cpumask: convert struct cpufreq_policy to cpumask_var_t\n cpumask: replace CPUMASK_ALLOC etc with cpumask_var_t\n x86: cleanup remaining cpumask_t ops in smpboot code\n cpumask: update pci_bus_show_cpuaffinity to use new cpumask API\n cpumask: update local_cpus_show to use new cpumask API\n ia64: cpumask fix for is_affinity_mask_valid()\n" }, { "commit": "eb9c39d031bbcfd4005bd7e0337c3fd3909c1bf7", "tree": "1549b3fb7eb08296b7f7fe72582d7067098059db", "parents": [ "876e501ab25dcd683574a5d3d56d8fe450083ed6" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 17 12:10:05 2008 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:07 2009 -0800" }, "message": "PCI: set device wakeup capable flag if platform support is present\n\nWhen PCI devices are initialized, we check whether they support PCI PM\ncaps and set the device can_wakeup flag if so. However, some devices\nmay have platform provided wakeup events rather than PCI PME signals, so\nwe need to set can_wakeup in that case too. Doing so should allow\nwakeups from many more devices, especially on cost constrained systems.\n\nReported-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\nTested-by: Joseph Chan \u003cJosephChan@via.com.tw\u003e\nAcked-by: \"Rafael J. Wysocki\" \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "3789fa8a2e534523c896a32a9f27f78d52ad7d82" }