)]}' { "log": [ { "commit": "aef7704c6cc36db9618603b22194def441d30432", "tree": "d560e29b90c0fcfadaeb1d41e3ba39a379e8496c", "parents": [ "b5badbaad16b44f1d5508701295fa682308da701" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Mon Apr 23 10:05:22 2012 -0600" }, "committer": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Apr 25 15:21:47 2012 -0600" }, "message": "pinctrl: tegra: error reporting cleanup\n\nPrint an explicit error message in various failure cases to allow\neasier diagnosis.\n\nWARN_ON() some internal failures that users/clients shouldn\u0027t be able to\ntrigger.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\n" }, { "commit": "b5badbaad16b44f1d5508701295fa682308da701", "tree": "75764dbb2f856b30b15cc0df1285153808317b9e", "parents": [ "52f48fe00fcad83cd5fc4c961d851a3530fe032b" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Apr 11 15:42:56 2012 -0600" }, "committer": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Apr 18 14:35:18 2012 -0600" }, "message": "pinctrl: tegra: debugfs enhancements\n\n* Only provide debugfs-relates ops when CONFIG_DEBUG_FS is enabled.\n* Implement pin_config_group_dbg_show op.\n* Implement pin_config_config_dbg_show op.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "52f48fe00fcad83cd5fc4c961d851a3530fe032b", "tree": "68fdb2a2580914f17b74374ad6b390027824c389", "parents": [ "ecc295bbab6b9d1baf0c0a8c2d5a945b201df547" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Apr 11 12:53:09 2012 -0600" }, "committer": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Apr 18 10:26:40 2012 -0600" }, "message": "pinctrl: tegra: refactor probe handling\n\nRather than having a single tegra-pinctrl driver that determines whether\nit\u0027s running on Tegra20 or Tegra30, instead have separate drivers for\neach that call into utility functions to implement the majority of the\ndriver. This change is based on review feedback of the SPEAr pinctrl\ndriver, which had originally copied to Tegra driver structure.\n\nThis requires that the two drivers have unique names. Update a couple\nspots in arch/arm/mach-tegra for the name change.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "f30d12b3ffb321c9d29bd1588940704d9bed2643", "tree": "0842183a866a3b45c1881210e423f4b8932b682b", "parents": [ "3e215d0a19c2a0c389bd9117573b6dd8e46f96a8" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Tue Dec 13 15:21:01 2011 -0700" }, "committer": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Apr 18 10:26:39 2012 -0600" }, "message": "ARM: tegra: Switch to new pinctrl driver\n\n* Rename old pinmux and new pinctrl platform driver and DT match table\n entries, so the new driver gets instantiated.\n* Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the\n pinmux.\n* Re-write board-*-pinmux.c so that the pinmux configuration tables are\n in pinctrl format.\n\nVentana\u0027s pin mux table needed some edits on top of the basic format\nconversion, since some mux options that were previously marked as\nreserved are now valid in the new pinctrl driver. Attempting to use the\nold reserved names will result in a failure. Specifically, groups lpw0,\nlpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya,\nand group pta was changed from function rsvd2 to hdmi.\n\nAll boards\u0027 pin mux tables needed some edits on top of the based format\nconversion, since function i2c was split into i2c1 (first general I2C\ncontroller) and i2cp (power I2C controller) to better align function\ndefinitions with HW blocks.\n\nDue to the split of mux tables into pure mux and pull/tristate tables,\nmany entries in the separate Seaboard/Ventana tables could be merged\ninto the common table, since the entries differed only in the portion\nin one of the tables, not both.\n\nMost pin groups allow configuration of mux, tri-state, and pull. However,\nsome don\u0027t allow pull configuration, which is instead configured by new\ngroups that only allow pull configuration. This is a reflection of the\ntrue HW capabilities, which weren\u0027t fully represented by the old pinmux\ndriver. This required adding new pull table entries for those new groups,\nand setting many other entries\u0027 pull configuration to\nTEGRA_PINCONFIG_DONT_SET.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nAcked-by: Olof Johansson \u003colof@lixom.net\u003e\n" }, { "commit": "60f7f5003d69b92558e9fc0789339f2b1d41f78d", "tree": "eea25d34d9322a1b21d9bb5728f592ea6edb1dbb", "parents": [ "a3c9454e530d51fad49bbc57e19d50a30f94ce14" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Apr 04 09:27:50 2012 -0600" }, "committer": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Wed Apr 18 13:53:12 2012 +0200" }, "message": "pinctrl: tegra: Add complete device tree support\n\nImplement pinctrl_ops dt_node_to_map() and dt_free_map(). These allow\ncomplete specification of the desired pinmux configuration using device\ntree.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Dong Aisheng \u003cdong.aisheng@linaro.org\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "d1e90e9e7467dbfe521b25ba79f520bf676ebc36", "tree": "2c4a2b8bfa2a984cb57a781b034a204a12fcc4b6", "parents": [ "122dbe7e58c7d064a17eefd33205227e6bce85ca" ], "author": { "name": "Viresh Kumar", "email": "viresh.kumar@st.com", "time": "Fri Mar 30 11:25:40 2012 +0530" }, "committer": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Wed Apr 18 13:53:10 2012 +0200" }, "message": "pinctrl: replace list_*() with get_*_count()\n\nMost of the SoC drivers implement list_groups() and list_functions()\nroutines for pinctrl and pinmux. These routines continue returning\nzero until the selector argument is greater than total count of\navailable groups or functions.\n\nThis patch replaces these list_*() routines with get_*_count()\nroutines, which returns the number of available selection for SoC\ndriver. pinctrl layer will use this value to check the range it can\nchoose.\n\nThis patch fixes all user drivers for this change. There are other\nroutines in user drivers, which have checks to check validity of\nselector passed to them. It is also no more required and hence\nremoved.\n\nDocumentation updated as well.\n\nAcked-by: Stephen Warren \u003cswarren@wwwdotorg.org\u003e\nSigned-off-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\n[Folded in fix and fixed a minor merge artifact manually]\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" }, { "commit": "971dac7123c785fdb0d09276b5d459b67585e242", "tree": "bf31a25b47b9b7504e6f0765bf1a97b28d8afa44", "parents": [ "62aa2b537c6f5957afd98e29f96897419ed5ebab" ], "author": { "name": "Stephen Warren", "email": "swarren@nvidia.com", "time": "Wed Feb 01 14:04:47 2012 -0700" }, "committer": { "name": "Linus Walleij", "email": "linus.walleij@linaro.org", "time": "Tue Mar 06 10:51:46 2012 +0100" }, "message": "pinctrl: add a driver for NVIDIA Tegra\n\nThis adds a driver for the Tegra pinmux, and required parameterization\ndata for Tegra20 and Tegra30.\n\nThe driver is initially added with driver name and device tree compatible\nvalue that won\u0027t cause this driver to be used. A later change will switch\nthe pinctrl driver to use the correct values, switch the old pinmux\ndriver to be disabled, and update all code that uses the old pinmux APIs\nto use the new pinctrl APIs.\n\nSigned-off-by: Stephen Warren \u003cswarren@nvidia.com\u003e\nAcked-by: Olof Johansson \u003colof@lixom.net\u003e\n[squashed \"fix case of Tegra30\u0027s foo_groups[] arrays\"]\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\n" } ] }