)]}'
{
  "log": [
    {
      "commit": "4ccf4beab8c447f8cd33d46afb6e10e1aa3befc6",
      "tree": "2291a9cb2b1fa2bbb94bbcb9df3c9cf8588fc176",
      "parents": [
        "e816b57a337ea3b755de72bec38c10c864f23015"
      ],
      "author": {
        "name": "Wolfram Sang",
        "email": "w.sang@pengutronix.de",
        "time": "Wed Aug 31 20:35:40 2011 +0200"
      },
      "committer": {
        "name": "Wolfram Sang",
        "email": "w.sang@pengutronix.de",
        "time": "Fri Apr 20 23:27:08 2012 +0200"
      },
      "message": "lib: add support for stmp-style devices\n\nMX23/28 use IP cores which follow a register layout I have first seen on\nSTMP3xxx SoCs. In this layout, every register actually has four u32:\n\n 1.) to store a value directly\n 2.) a SET register where every 1-bit sets the corresponding bit,\n     others are unaffected\n 3.) same with a CLR register\n 4.) same with a TOG (toggle) register\n\nAlso, the 2 MSBs in register 0 are always the same and can be used to reset\nthe IP core.\n\nAll this is strictly speaking not mach-specific (but IP core specific) and,\nthus, doesn\u0027t need to be in mach-mxs/include. At least mx6 also uses IP cores\nfollowing this stmp-style. So:\n\nIntroduce a stmp-style device, put the code and defines for that in a public\nplace (lib/), and let drivers for stmp-style devices select that code.\nTo avoid regressions and ease reviewing, the actual code is simply copied from\nmach-mxs. It definately wants updates, but those need a seperate patch series.\n\nVoila, mach dependency gone, reusable code introduced. Note that I didn\u0027t\nremove the duplicated code from mach-mxs yet, first the drivers have to be\nconverted.\n\nSigned-off-by: Wolfram Sang \u003cw.sang@pengutronix.de\u003e\nAcked-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nAcked-by: Dong Aisheng \u003cdong.aisheng@linaro.org\u003e\n"
    }
  ]
}