)]}'
{
  "log": [
    {
      "commit": "c211092313b90f898dec61f35207fc282d1eadc3",
      "tree": "30df0c81f207d0babb3fe56a17419f37e71e973a",
      "parents": [
        "f6dff381af01006ffae3c23cd2e07e30584de0ec"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 02 13:52:26 2007 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 13 08:06:18 2007 -0700"
      },
      "message": "dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines\n\nThe Intel(R) IOP series of i/o processors integrate an Xscale core with\nraid acceleration engines.  The capabilities per platform are:\n\niop219:\n (2) copy engines\niop321:\n (2) copy engines\n (1) xor and block fill engine\niop33x:\n (2) copy and crc32c engines\n (1) xor, xor zero sum, pq, pq zero sum, and block fill engine\niop34x (iop13xx):\n (2) copy, crc32c, xor, xor zero sum, and block fill engines\n (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine\n\nThe driver supports the features of the async_tx api:\n* asynchronous notification of operation completion\n* implicit (interupt triggered) handling of inter-channel transaction\n  dependencies\n\nThe driver adapts to the platform it is running by two methods.\n1/ #include \u003casm/arch/adma.h\u003e which defines the hardware specific\n   iop_chan_* and iop_desc_* routines as a series of static inline\n   functions\n2/ The private platform data attached to the platform_device defines the\n   capabilities of the channels\n\n20070626: Callbacks are run in a tasklet.  Given the recent discussion on\nLKML about killing tasklets in favor of workqueues I did a quick conversion\nof the driver.  Raid5 resync performance dropped from 50MB/s to 30MB/s, so\nthe tasklet implementation remains until a generic softirq interface is\navailable.\n\nChangelog:\n* fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few\nslots to be requested eventually leading to data corruption\n* enabled the slot allocation routine to attempt to free slots before\nreturning -ENOMEM\n* switched the cleanup routine to solely use the software chain and the\nstatus register to determine if a descriptor is complete.  This is\nnecessary to support other IOP engines that do not have status writeback\ncapability\n* make the driver iop generic\n* modified the allocation routines to understand allocating a group of\nslots for a single operation\n* added a null xor initialization operation for the xor only channel on\niop3xx\n* support xor operations on buffers larger than the hardware maximum\n* split the do_* routines into separate prep, src/dest set, submit stages\n* added async_tx support (dependent operations initiation at cleanup time)\n* simplified group handling\n* added interrupt support (callbacks via tasklets)\n* brought the pending depth inline with ioat (i.e. 4 descriptors)\n* drop dma mapping methods, suggested by Chris Leech\n* don\u0027t use inline in C files, Adrian Bunk\n* remove static tasklet declarations\n* make iop_adma_alloc_slots easier to read and remove chances for a\n  corrupted descriptor chain\n* fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt\n* convert capabilities over to dma_cap_mask_t\n* fixup sparse warnings\n* add descriptor flush before iop_chan_enable\n* checkpatch.pl fixes\n* gpl v2 only correction\n* move set_src, set_dest, submit to async_tx methods\n* move group_list and phys to async_tx\n\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "de5506e155276d385712c2aa1c2d9a27cd4ed947",
      "tree": "219c30dab27b9aef2597d8735dfc19db8454849e",
      "parents": [
        "db21733488f84a596faaad0d05430b3f51804692"
      ],
      "author": {
        "name": "Chris Leech",
        "email": "christopher.leech@intel.com",
        "time": "Tue May 23 17:50:37 2006 -0700"
      },
      "committer": {
        "name": "David S. Miller",
        "email": "davem@sunset.davemloft.net",
        "time": "Sat Jun 17 21:25:46 2006 -0700"
      },
      "message": "[I/OAT]: Utility functions for offloading sk_buff to iovec copies\n\nProvides for pinning user space pages in memory, copying to iovecs,\nand copying from sk_buffs including fragmented and chained sk_buffs.\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n"
    },
    {
      "commit": "0bbd5f4e97ff9c057b385a1886b4aed1fb0300f1",
      "tree": "0c3d8528c31e8291fb78c2e7a287910987ed2888",
      "parents": [
        "c13c8260da3155f2cefb63b0d1b7dcdcb405c644"
      ],
      "author": {
        "name": "Chris Leech",
        "email": "christopher.leech@intel.com",
        "time": "Tue May 23 17:35:34 2006 -0700"
      },
      "committer": {
        "name": "David S. Miller",
        "email": "davem@sunset.davemloft.net",
        "time": "Sat Jun 17 21:18:46 2006 -0700"
      },
      "message": "[I/OAT]: Driver for the Intel(R) I/OAT DMA engine\n\nAdds a new ioatdma driver\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n"
    },
    {
      "commit": "c13c8260da3155f2cefb63b0d1b7dcdcb405c644",
      "tree": "ecfe02fa44a423a948f5fb5ad76497da2bb7a402",
      "parents": [
        "427abfa28afedffadfca9dd8b067eb6d36bac53f"
      ],
      "author": {
        "name": "Chris Leech",
        "email": "christopher.leech@intel.com",
        "time": "Tue May 23 17:18:44 2006 -0700"
      },
      "committer": {
        "name": "David S. Miller",
        "email": "davem@sunset.davemloft.net",
        "time": "Sat Jun 17 21:18:43 2006 -0700"
      },
      "message": "[I/OAT]: DMA memcpy subsystem\n\nProvides an API for offloading memory copies to DMA devices\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n"
    }
  ]
}