)]}' { "log": [ { "commit": "6de5fc9cf7de334912de4cfd2d06eb2d744d2afe", "tree": "473198b98663f0e84fc69b70f2fca12dad7f9b9c", "parents": [ "7833c66b2d764a3c883c2f5cc60cd8a6266dae15" ], "author": { "name": "Stefan Nilsson XK", "email": "stefan.xk.nilsson@stericsson.com", "time": "Thu Nov 03 09:44:12 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Dec 10 16:18:35 2011 -0500" }, "message": "mmc: core: Add quirk for long data read time\n\nAdds a quirk that sets the data read timeout to a fixed value instead\nof relying on the information in the CSD. The timeout value chosen\nis 300ms since that has proven enough for the problematic cards found,\nbut could be increased if other cards require this.\n\nThis patch also enables this quirk for certain Micron cards known to\nhave this problem.\n\nSigned-off-by: Stefan Nilsson XK \u003cstefan.xk.nilsson@stericsson.com\u003e\nSigned-off-by: Ulf Hansson \u003culf.hansson@stericsson.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "a6029e1f75bb484c1f5bc68b6a8572e4024795bc", "tree": "79b8487c706e93fa4e0be28d3a4297d65851ac35", "parents": [ "336c716ae2272c9a26a6f82976d0e077d8ca824e" ], "author": { "name": "Namjae Jeon", "email": "linkinjeon@gmail.com", "time": "Thu Oct 13 00:43:14 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Thu Oct 27 09:11:34 2011 -0400" }, "message": "mmc: fix compile error when CONFIG_BLOCK is not enabled\n\n\u0027DISK_NAME_LEN\u0027 is undeclared when CONFIG_BLOCK is disabled; its use was\nintroduced via genhd.h by the general purpose partition patch.\n\nTo fix, we just add our own MAX_MMC_PART_NAME_LEN macro instead of using\nDISK_NAME_LEN.\n\nReported-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: Namjae Jeon \u003clinkinjeon@gmail.com\u003e\nAcked-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nAcked-by: Andrei Warkentin \u003candreiw@vmware.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "2bf22b39823c1d173dda31111a4eb2ce36daaf39", "tree": "54575fedfd2b032c3113b55dea5e2fd5d0c7eb38", "parents": [ "b6ad726e3fe69e1ff3c3b2ad272ba3e4c376cd6a" ], "author": { "name": "Paul Walmsley", "email": "paul@pwsan.com", "time": "Thu Oct 06 14:50:33 2011 -0600" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Thu Oct 27 09:10:57 2011 -0400" }, "message": "mmc: core: add workaround for controllers with broken multiblock reads\n\nDue to hardware bugs, some MMC host controllers don\u0027t support\nmultiple-block reads[1]. To resolve, add a new MMC capability flag,\nMMC_CAP2_NO_MULTI_READ, which can be set by affected host controller\ndrivers. When this capability is set, all reads will be issued one\nsector at a time.\n\n1. See for example Advisory 2.1.1.128 \"MMC: Multiple Block Read\nOperation Issue\" in _OMAP3530/3525/3515/3503 Silicon Errata_\nRevision F (October 2010) (SPRZ278F), available from\nhttp://focus.ti.com/lit/er/sprz278f/sprz278f.pdf\n\nSigned-off-by: Paul Walmsley \u003cpaul@pwsan.com\u003e\nCc: Dave Hylands \u003cdhylands@gmail.com\u003e\nTested-by: Steve Sakoman \u003csakoman@gmail.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "b4625dab2c618eb87e177761dda3182b4cfaa604", "tree": "24398081cac8259d99b67dcc7b4e1afe3384df8e", "parents": [ "f2815f68dabbb373fd1c9f0fd4a609d486697c2b" ], "author": { "name": "Bing Zhao", "email": "bzhao@marvell.com", "time": "Thu Oct 20 19:16:32 2011 -0700" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:31 2011 -0400" }, "message": "mmc: recognise SDIO cards with SDIO_CCCR_REV 3.00\n\nTable 6-2: CCCR bit Definitions, address 00h. Part E1 SDIO Simplified\nSpecification Version 3.00, Feb. 25, 2011.\n\nThis patch has been tested with Marvell WLAN device SD8797.\n\nSigned-off-by: Bing Zhao \u003cbzhao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "eb0d8f135b6730d6d0324a064664d121334290e7", "tree": "74876f5d20163bb5e9b185d9357237e1f22a2262", "parents": [ "881d1c25f765938a95def5afe39486ce39f9fc96" ], "author": { "name": "Jaehoon Chung", "email": "jh80.chung@samsung.com", "time": "Tue Oct 18 01:26:42 2011 -0400" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:29 2011 -0400" }, "message": "mmc: core: support HPI send command\n\nHPI command is defined in eMMC4.41.\nThis feature is important for eMMC4.5 devices.\n\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "881d1c25f765938a95def5afe39486ce39f9fc96", "tree": "694d5ea1b3fba2c28cc110123f2ca50b4408f309", "parents": [ "71fe3eb0d006861bdae57e93975b6ae3d9b55e99" ], "author": { "name": "Seungwon Jeon", "email": "tgih.jun@samsung.com", "time": "Fri Oct 14 14:03:21 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:28 2011 -0400" }, "message": "mmc: core: Add cache control for eMMC4.5 device\n\nThis patch adds cache feature of eMMC4.5 Spec.\nIf device supports cache capability, host can utilize some specific\noperations.\n\nSigned-off-by: Seungwon Jeon \u003ctgih.jun@samsung.com\u003e\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "b3bf915308ca2b50f3beec6cc824083870f0f4b5", "tree": "955978242b333e1388358b4b50b5f8f4a5abca04", "parents": [ "d9ddd62943ee07a75d0428ffcf52f1a747a28c39" ], "author": { "name": "Kyungmin Park", "email": "kyungmin.park@samsung.com", "time": "Tue Oct 18 09:34:04 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:27 2011 -0400" }, "message": "mmc: core: new discard feature support at eMMC v4.5\n\nMMC v4.5 supports the DISCARD feature (CMD38). It\u0027s different from\ntrim and there\u0027s no check bit. Currently it\u0027s only supported at v4.5.\n\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "d9ddd62943ee07a75d0428ffcf52f1a747a28c39", "tree": "e4fb8b0b2ba2fe39bf725762b2c04441f1adf3b8", "parents": [ "4e0a5adf46ee7810af2e1b7e4e8c2a298652618e" ], "author": { "name": "Kyungmin Park", "email": "kyungmin.park@samsung.com", "time": "Fri Oct 14 14:15:48 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:26 2011 -0400" }, "message": "mmc: core: mmc sanitize feature support for v4.5\n\nIn the v4.5, there\u0027s no secure erase \u0026 trim support.\nInstead it supports the sanitize feature.\n\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "4e0a5adf46ee7810af2e1b7e4e8c2a298652618e", "tree": "64b60adcedd341a02a8f150ce7257e2b0eb40e0c", "parents": [ "c43fd7746698a10aa6435d62ec28f977dd6246cc" ], "author": { "name": "Jaehoon Chung", "email": "jh80.chung@samsung.com", "time": "Mon Oct 17 19:36:23 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:25 2011 -0400" }, "message": "mmc: dw_mmc: modify DATA register offset\n\nIn dw_mmc 2.40a spec, Data register\u0027s offset is changed.\nBefore we used Data register offset 0x100. but if somebody uses a\n2.40a controller, we must use 0x200 for Data register.\n\nThis patch adds a version-id checking point and uses SDMMC_DATA(x)\ninstead of SDMMC_DATA. It assumes 2.40a is the latest version.\n\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "bec8726abc72bf30d2743a722aa37cd69e7a0580", "tree": "eed4a3c441ff64f5719b021fce419de0fc5196d9", "parents": [ "326adda53a50ece492c3edaa60afc26fba5e3232" ], "author": { "name": "Girish K S", "email": "girish.shivananjappa@linaro.org", "time": "Thu Oct 13 12:04:16 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:23 2011 -0400" }, "message": "mmc: core: Add Power Off Notify Feature eMMC 4.5\n\nThis patch adds support for the power off notify feature, available in\neMMC 4.5 devices. If the host has support for this feature, then the\nmmc core will notify the device by setting the POWER_OFF_NOTIFICATION\nbyte in the extended csd register with a value of 1 (POWER_ON).\n\nFor suspend mode short timeout is used, whereas for the normal poweroff\nlong timeout is used.\n\nSigned-off-by: Girish K S \u003cgirish.shivananjappa@linaro.org\u003e\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "b23cf0bd55b0c6b703982446f679e00d6d929524", "tree": "7701af9bd8b7f35321dfb4a5accf71fc9c04e60d", "parents": [ "66fd8ad5100b5003046aa744a4f12fa31bb831f9" ], "author": { "name": "Seungwon Jeon", "email": "tgih.jun@samsung.com", "time": "Fri Sep 23 14:15:29 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:21 2011 -0400" }, "message": "mmc: core: Add default timeout value for CMD6\n\nEXT_CSD[248] includes the default maximum timeout for CMD6.\nThis field is added at eMMC4.5 Spec. And it can be used for default\ntimeout except for some operations which don\u0027t define the timeout\n(i.e. background operation, sanitize, flush cache) in eMMC4.5 Spec.\n\nSigned-off-by: Seungwon Jeon \u003ctgih.jun@samsung.com\u003e\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "66fd8ad5100b5003046aa744a4f12fa31bb831f9", "tree": "c71aa6ff8b5c4c2919b93630a2315017f4610986", "parents": [ "08a7e1dfaa63bf5132b5b7231fcf9a33473c78f5" ], "author": { "name": "Adrian Hunter", "email": "adrian.hunter@intel.com", "time": "Mon Oct 03 15:33:34 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:20 2011 -0400" }, "message": "mmc: sdhci-pci: add runtime pm support\n\nThs patch allows runtime PM for sdhci-pci, runtime suspending after\ninactivity of 50ms and ensuring runtime resume before SDHC registers\nare accessed. During runtime suspend, interrupts are masked.\nThe host controller state is restored at runtime resume.\n\nFor Medfield, the host controller\u0027s card detect mechanism is\nsupplanted by an always-on GPIO which provides for card detect wake-up.\n\nSigned-off-by: Adrian Hunter \u003cadrian.hunter@intel.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "e0c368d571d946ff40f068344b5c2df90c93dd2e", "tree": "509fdad0059dac018128610723557b4ca12f29d2", "parents": [ "5238acbe36dd5100fb6b035a995ae5fc89dd0708" ], "author": { "name": "Namjae Jeon", "email": "linkinjeon@gmail.com", "time": "Thu Oct 06 23:41:38 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:17 2011 -0400" }, "message": "mmc: core: general purpose MMC partition support.\n\nIt allows gerneral purpose partitions in MMC Device. And I try to simply\nmake mmc_blk_alloc_parts using mmc_part structure suggested by Andrei\nWarkentin. After patching, we see general purpose partitions like this:\n\u003e cat /proc/partitions\n 179 0 847872 mmcblk0\n 179 192 4096 mmcblk0gp3\n 179 160 4096 mmcblk0gp2\n 179 128 4096 mmcblk0gp1\n 179 96 1052672 mmcblk0gp0\n 179 64 1024 mmcblk0boot1\n 179 32 1024 mmcblk0boot0\n\nSigned-off-by: Namjae Jeon \u003clinkinjeon@gmail.com\u003e\nAcked-by: Andrei Warkentin \u003cawarkentin@vmware.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "f7c56ef2af5ae7e4c24c3c79427b38d18ba1d294", "tree": "5590da07839d9a07b7811a8fe0104aaa596e03dc", "parents": [ "0d7d85ca6e5dc7bd426d1d5989a44e93e8c7a0d3" ], "author": { "name": "Adrian Hunter", "email": "adrian.hunter@intel.com", "time": "Fri Sep 23 12:48:21 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:15 2011 -0400" }, "message": "mmc: block: support no access to boot partitions\n\nIntel Medfield platform blocks access to eMMC boot partitions which\nresults in switch errors. Since there is no access, mmcboot0/1\ndevices should not be created. Add a host capability to reflect that.\n\nSigned-off-by: Adrian Hunter \u003cadrian.hunter@intel.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "b87d8dbf6c410b5f2d9b6893c85baa06aa131c7c", "tree": "f478e5378f259bb75158d5cb08cc459c93f30905", "parents": [ "199e3f4b419d045e64d5205a6354c5db04d98553" ], "author": { "name": "Girish K S", "email": "girish.shivananjappa@linaro.org", "time": "Fri Sep 23 20:41:47 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:13 2011 -0400" }, "message": "mmc: core: eMMC 4.5 Power Class Selection Feature\n\nThis patch adds the power class selection feature available for mmc\nversions 4.0 and above. During the enumeration stage before switching\nto the lower data bus, check if the power class is supported for the\ncurrent bus width. If the power class is available then switch to the\npower class and use the higher data bus. If power class is not supported\nthen switch to the lower data bus in a worst case.\n\nSigned-off-by: Girish K S \u003cgirish.shivananjappa@linaro.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "714c4a6e3a0f730834ec8a8bc83b2a6da33f54dc", "tree": "1e2a581b44fab2b92d21fc52d134719dde003c45", "parents": [ "67716327eec7e9d573e7cb2d806545d6f7c1a38d" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Tue Aug 30 18:26:39 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:09 2011 -0400" }, "message": "mmc: sh_mmcif: simplify platform data\n\nProvide platforms with a simplified way to specify MMCIF DMA slave IDs in\na way, similar to SDHI and other sh_dma clients.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "b2499518b5ad7e28bb3ed348fd3f370eeb1e36c0", "tree": "c4c9597d0631554bffeecbcc6a2a7ec3037ea78c", "parents": [ "8e3336b1e4378f7d205af9b25dcc9e645c8a9609" ], "author": { "name": "Adrian Hunter", "email": "adrian.hunter@intel.com", "time": "Mon Aug 29 16:42:11 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:05 2011 -0400" }, "message": "mmc: core: add eMMC hardware reset support\n\neMMC\u0027s may have a hardware reset line. This patch provides a\nhost controller operation to implement hardware reset and\na function to reset and reinitialize the card. Also, for MMC,\nthe reset is always performed before initialization.\n\nThe host must set the new host capability MMC_CAP_HW_RESET\nto enable hardware reset.\n\nSigned-off-by: Adrian Hunter \u003cadrian.hunter@intel.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "7c8a2829c22a270acadc6aa3a937e2e7956b19f5", "tree": "b787b429a1bd01f364e752fe5b52e2f95cb46875", "parents": [ "44669034815a7ad263542ac605c581a10b22d146" ], "author": { "name": "Per Forlin", "email": "per.forlin@linaro.org", "time": "Mon Aug 29 15:35:58 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:04 2011 -0400" }, "message": "mmc: core: clarify how to use post_req in case of errors\n\nThe err condition in post_req() is set to undo a call made to pre_req()\nthat hasn\u0027t been started yet. The err condition is not set if an MMC\nrequest returns an error.\n\nSigned-off-by: Per Forlin \u003cper.forlin@linaro.org\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "9a0da648ff3a5020406ac7784eb3b519014f66f6", "tree": "54e546b73bbba36a2a3277eb8cde2771595b37a4", "parents": [ "329f22371460587c59b866dcbffce5b498b61f38" ], "author": { "name": "Stefan Nilsson XK", "email": "stefan.xk.nilsson@stericsson.com", "time": "Thu Sep 15 17:43:04 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 16:32:02 2011 -0400" }, "message": "mmc: sdio: Workaround for dev with broken CMD53\n\nAdds a quirk which can be turned on for SDIO devices that do not support\n512 byte requests in byte mode during CMD53. These requests will always\nbe sent in block mode instead.\n\nThis patch also enables this quirk for ST-Ericsson CW1200 WLAN device.\n\nSigned-off-by: Stefan Nilsson XK \u003cstefan.xk.nilsson@stericsson.com\u003e\nSigned-off-by: Ulf HANSSON \u003culf.hansson@stericsson.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "d5098cb63b3f13da2a2b230b3566ac7b5dfa4f28", "tree": "b1317ea1339a678b283a0213f5c6647a58099b33", "parents": [ "7729c7a232a95360fa17ffe8beb1adb621bc0ba0" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Fri Aug 26 10:42:39 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 15:43:36 2011 -0400" }, "message": "mmc: sdhi: Allow named IRQs to use specific handlers\n\nAllow named IRQs to use corresponding specific handlers. If named IRQs are\nused, at least an \"sdcard\" IRQ has to be specified by the platform. If\nnames are not used, an arbitrary number of IRQs can be provided by the\nplatform, in which case the generic ISR will be used for each of them.\n\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\n[g.liakhovetski@gmx.de: style and typo corrections, platform data check]\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "1b676f70c108cda90cf9d114d16c677584400efc", "tree": "7f4a18ade6db764ba3c882e294040a91adc2911e", "parents": [ "df87ecbf19109bab04a92df047a9949838206abc" ], "author": { "name": "Per Forlin", "email": "per.forlin@linaro.org", "time": "Fri Aug 19 14:52:37 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Oct 26 15:43:34 2011 -0400" }, "message": "mmc: core: add random fault injection\n\nThis adds support to inject data errors after a completed host transfer.\nThe mmc core will return error even though the host transfer is successful.\nThis simple fault injection proved to be very useful to test the\nnon-blocking error handling in the mmc_blk_issue_rw_rq().\nRandom faults can also test how the host driver handles pre_req()\nand post_req() in case of errors.\n\nSigned-off-by: Per Forlin \u003cper.forlin@linaro.org\u003e\nAcked-by: Akinobu Mita \u003cakinobu.mita@gmail.com\u003e\nReviewed-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "7fd781e8f9b72544a1c7f04456eb33d5ffaed592", "tree": "1f53b5d72f88c2e2bb6f15e0daeaf09a944b94fd", "parents": [ "6daa777866569fc48fe3cfcd6fd01aba37ac06a5" ], "author": { "name": "Jaehoon Chung", "email": "jh80.chung@samsung.com", "time": "Mon Aug 08 18:10:52 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Aug 13 14:50:32 2011 -0400" }, "message": "mmc: remove unused \"ddr\" parameter in struct mmc_ios\n\n\"mmc: dw_mmc: Fix DDR mode support\" removed the last user.\n\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "ca8e99b32e3863c98ac958617cc157a00bf445b8", "tree": "2e8b5d9fc5577ef2c795c9cd4ca40ae21e508699", "parents": [ "ee8a43a51c7681f19fe23b6b936e1d8094a8b7d1" ], "author": { "name": "Philip Rakity", "email": "prakity@marvell.com", "time": "Wed Jul 06 08:51:32 2011 -0700" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:21:16 2011 -0400" }, "message": "mmc: core: Set non-default Drive Strength via platform hook\n\nNon default Drive Strength cannot be set automatically. It is a function\nof the board design and only if there is a specific platform handler can\nit be set. The platform handler needs to take into account the board\ndesign. Pass to the platform code the necessary information.\n\nFor example: The card and host controller may indicate they support HIGH\nand LOW drive strength. There is no way to know what should be chosen\nwithout specific board knowledge. Setting HIGH may lead to reflections\nand setting LOW may not suffice. There is no mechanism (like ethernet\nduplex or speed pulses) to determine what should be done automatically.\n\nIf no platform handler is defined -- use the default value.\n\nSigned-off-by: Philip Rakity \u003cprakity@marvell.com\u003e\nReviewed-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "aa8b683a7d392271ed349c6ab9f36b8c313794b7", "tree": "82c97c089844a03492be55968c1d3cc993aaafa6", "parents": [ "0500f10cc2d624034f350edae2529975c0f1c1f8" ], "author": { "name": "Per Forlin", "email": "per.forlin@linaro.org", "time": "Fri Jul 01 18:55:22 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:21:10 2011 -0400" }, "message": "mmc: core: add non-blocking mmc request function\n\nPreviously there has only been one function mmc_wait_for_req()\nto start and wait for a request. This patch adds:\n\n * mmc_start_req() - starts a request wihtout waiting\n If there is on ongoing request wait for completion\n of that request and start the new one and return.\n Does not wait for the new command to complete.\n\nThis patch also adds new function members in struct mmc_host_ops\nonly called from core.c:\n\n * pre_req - asks the host driver to prepare for the next job\n * post_req - asks the host driver to clean up after a completed job\n\nThe intention is to use pre_req() and post_req() to do cache maintenance\nwhile a request is active. pre_req() can be called while a request is\nactive to minimize latency to start next job. post_req() can be used after\nthe next job is started to clean up the request. This will minimize the\nhost driver request end latency. post_req() is typically used before\nending the block request and handing over the buffer to the block layer.\n\nAdd a host-private member in mmc_data to be used by pre_req to mark the\ndata. The host driver will then check this mark to see if the data is\nprepared or not.\n\nSigned-off-by: Per Forlin \u003cper.forlin@linaro.org\u003e\nAcked-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nReviewed-by: Venkatraman S \u003csvenkatr@ti.com\u003e\nTested-by: Sourav Poddar \u003csourav.poddar@ti.com\u003e\nTested-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "03e8cb534e7cc3f71a07528a44da7ce68e5b5708", "tree": "989d0a96a03d8838de7617f6eb0062ed2a7065e6", "parents": [ "65d13516b2358c38ac56a5f83e989a6837dcf825" ], "author": { "name": "James Hogan", "email": "james.hogan@imgtec.com", "time": "Wed Jun 29 09:28:43 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:21:05 2011 -0400" }, "message": "mmc: dw_mmc: fix stop when fallen back to PIO\n\nThere are several situations when dw_mci_submit_data_dma() decides to\nfall back to PIO mode instead of using DMA, due to a short (to avoid\noverhead) or \"complex\" (e.g. with unaligned buffers) transaction, even\nthough host-\u003euse_dma is set. However dw_mci_stop_dma() decides whether\nto stop DMA or set the EVENT_XFER_COMPLETE event based on host-\u003euse_dma.\nWhen falling back to PIO mode this results in data timeout errors\ngetting missed and the driver locking up.\n\nTherefore add host-\u003eusing_dma to indicate whether the current\ntransaction is using dma or not, and adjust dw_mci_stop_dma() to use\nthat instead.\n\nSigned-off-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nTested-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "e056a1b5b67b4e4bfad00bf143ab14f634777705", "tree": "c9cd3a6144787bcb434e52a4a32dec3c37e9f343", "parents": [ "e8cd77e467f7bb1d4b942037c47b087334a484d4" ], "author": { "name": "Adrian Hunter", "email": "adrian.hunter@intel.com", "time": "Tue Jun 28 17:16:02 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:21:03 2011 -0400" }, "message": "mmc: queue: let host controllers specify maximum discard timeout\n\nSome host controllers will not operate without a hardware\ntimeout that is limited in value. However large discards\nrequire large timeouts, so there needs to be a way to\nspecify the maximum discard size.\n\nA host controller driver may now specify the maximum discard\ntimeout possible so that max_discard_sectors can be calculated.\n\nHowever, for eMMC when the High Capacity Erase Group Size\nis not in use, the timeout calculation depends on clock\nrate which may change. For that case Preferred Erase Size\nis used instead.\n\nSigned-off-by: Adrian Hunter \u003cadrian.hunter@intel.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "34b664a20e2664de0d0d7990ca60276b96c08c75", "tree": "15d2d1ef438f9418bf1ccfadb5ec30bad772d6d1", "parents": [ "b86d825323b4c5d0c406e5b1a85af614acf0cf5a" ], "author": { "name": "James Hogan", "email": "james.hogan@imgtec.com", "time": "Fri Jun 24 13:57:56 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:21:00 2011 -0400" }, "message": "mmc: dw_mmc: handle unaligned buffers and sizes\n\nUpdate functions for PIO pushing and pulling data to and from the FIFO\nso that they can handle unaligned output buffers and unaligned buffer\nlengths. This makes more of the tests in mmc_test pass.\n\nUnaligned lengths in pulls are handled by reading the full FIFO item,\nand storing the remaining bytes in a small internal buffer (part_buf).\nThe next data pull will copy data out of this buffer first before\naccessing the FIFO again. Similarly, for pushes the final bytes that\ndon\u0027t fill a FIFO item are stored in the part_buf (or sent anyway if\nit\u0027s the last transfer), and then the part_buf is included at the\nbeginning of the next buffer pushed.\n\nUnaligned buffers in pulls are handled specially if the architecture\ncannot do efficient unaligned accesses, by reading FIFO items into a\naligned local buffer, and memcpy\u0027ing them into the output buffer, again\nstoring any remaining bytes in the internal buffer. Similarly for pushes\nthe buffer is memcpy\u0027d into an aligned local buffer then written to the\nFIFO.\n\nSigned-off-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "b86d825323b4c5d0c406e5b1a85af614acf0cf5a", "tree": "15d9f279e07948eb0649bafa0c14d9a785afda0a", "parents": [ "892b1e312b179139026e366a9d70065a7f897dbc" ], "author": { "name": "James Hogan", "email": "james.hogan@imgtec.com", "time": "Fri Jun 24 13:57:18 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:20:59 2011 -0400" }, "message": "mmc: dw_mmc: don\u0027t hard code fifo depth, fix usage\n\nThe FIFO_DEPTH hardware configuration parameter can be found from the\npower-on value of RX_WMark in the FIFOTH register. This is used to\ninitialise the watermarks, but when calculating the number of free fifo\nspaces a preprocessor definition is used which is hard coded to 32.\n\nFix reading the value out of FIFOTH (the default value in the RX_WMark\nfield is FIFO_DEPTH-1 not FIFO_DEPTH). Allow the fifo depth to be\noverriden by platform data (since a bootloader may have changed FIFOTH\nmaking auto-detection unreliable). Store the fifo_depth for later use.\nAlso fix the calculation to find the number of free bytes in the fifo to\ninclude the fifo depth in the left shift by the data shift, since the\nfifo depth is measured in fifo items not bytes.\n\nSigned-off-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "1791b13ea4d97a6a7c162edd54485e932ad92f1b", "tree": "0012ece1a9b0bf403f759d5f552fc34c6d8c82d1", "parents": [ "7456caae37396fc1bc6f8e9461d07664b8c2f280" ], "author": { "name": "James Hogan", "email": "james.hogan@imgtec.com", "time": "Fri Jun 24 13:55:55 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:20:58 2011 -0400" }, "message": "mmc: dw_mmc: convert card tasklet to workqueue\n\nConvert the card insert/remove tasklet to a workqueue, and call the\nsetpower platform specific callback without the spinlock held. This\nmeans neither of the setpower or get_cd callbacks are called from atomic\ncontext which allows them to sleep.\n\nSigned-off-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "973ed3af1a570612771ed10dec6506c757767668", "tree": "db993034cacfcc3f3388c43d96459a123adc32a2", "parents": [ "a11862d3389d4304211eed0758f510d5e573f93c" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Tue Jun 21 08:00:10 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:20:57 2011 -0400" }, "message": "mmc: sdhi: Add write16_hook\n\nSome controllers require waiting for the bus to become idle\nbefore writing to some registers. I have implemented this\nby adding a hook to sd_ctrl_write16() and implementing\na hook for SDHI which waits for the bus to become idle.\n\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "95c7348d948dc4832434ddfaeba804ac14732f02", "tree": "f1795c7d0ad42672d0884430f070f2cdaeed07f2", "parents": [ "4c2b8f26eb8b54203e0e7834e0f7a11a7ae15ef1" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Tue Jun 21 08:00:08 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:20:55 2011 -0400" }, "message": "mmc: tmio: name 0xd8 as CTL_DMA_ENABLE\n\nThis reflects at least the current usage of this register\nand I think it improves the readability of the code ever so slightly.\n\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "0a2d4048a22079d7e79d6654bbacbef57bd5728a", "tree": "3de4e928e43786b215271d467e77cf6e20a2e724", "parents": [ "6e83e10d92e12fa0181766a1fbb00d857bfab779" ], "author": { "name": "Russell King - ARM Linux", "email": "linux@arm.linux.org.uk", "time": "Mon Jun 20 20:10:08 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:20:54 2011 -0400" }, "message": "mmc: block: allow get_card_status() to return error status\n\nIf the MMC_SEND_STATUS command is not successful, we should not return\na zero status word, but instead allow the caller to know positively\nthat an error occurred.\n\nConvert the open-coded get_card_status() to use the helper function,\nand provide definitions for the card state field.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nTested-by: Pawel Moll \u003cpawel.moll@arm.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "100e918610b7487fa18db97b3879cd8d1fdd5974", "tree": "ff0d7e3b47af34db77da21f0954c3461918b1ee3", "parents": [ "94cc6a86567cb3c2234807081a46ce5400c36b31" ], "author": { "name": "Robert P. J. Day", "email": "rpjday@crashcourse.ca", "time": "Fri May 27 16:04:03 2011 -0400" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:20:48 2011 -0400" }, "message": "mmc: Standardize header file inclusion checks.\n\nStandardize the checks for multiple MMC header file inclusion,\nincluding adding comments to terminating #endif\u0027s, and fixing\none incorrect comment.\n\nSigned-off-by: Robert P. J. Day \u003crpjday@crashcourse.ca\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "94cc6a86567cb3c2234807081a46ce5400c36b31", "tree": "41d7253d5bc7f05a901277c3f2631ff2da31268b", "parents": [ "38576af1f8cad48446df47dcf404b197c9206dba" ], "author": { "name": "Shawn Guo", "email": "shawn.guo@linaro.org", "time": "Fri May 27 23:48:15 2011 +0800" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:20:48 2011 -0400" }, "message": "mmc: sdhci: merge two sdhci-pltfm.h into one\n\nThe structure sdhci_pltfm_data is not necessarily to be in a public\nheader like include/linux/mmc/sdhci-pltfm.h, so the patch moves it\ninto drivers/mmc/host/sdhci-pltfm.h and eliminates the former one.\n\nSigned-off-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nReviewed-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nReviewed-by: Wolfram Sang \u003cw.sang@pengutronix.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "85d6509dc8ca24b2b652863ef7a75622ddca17d6", "tree": "e564c2d4f80478027abc96cb7d87da952b38409e", "parents": [ "3a5c3743f15f27237ab025736a981e2d0c9fdfed" ], "author": { "name": "Shawn Guo", "email": "shawn.guo@linaro.org", "time": "Fri May 27 23:48:12 2011 +0800" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 20 17:16:06 2011 -0400" }, "message": "mmc: sdhci: make sdhci-pltfm device drivers self registered\n\nThe patch turns the common stuff in sdhci-pltfm.c into functions, and\nadd device drivers their own .probe and .remove which in turn call\ninto the common functions, so that those sdhci-pltfm device drivers\nregister itself and keep all device specific things away from common\nsdhci-pltfm file.\n\nSigned-off-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nReviewed-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nAcked-by: Anton Vorontsov \u003ccbouatmailru@gmail.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "f39b2dd9d065151a04f5996656d1f27a7eb32d45", "tree": "3801f7d6793529d737fcbfd6af05b6900ef2cd06", "parents": [ "c31b55cd4eaf050bb5a15bd8251da1b3c7edeb1c" ], "author": { "name": "Philip Rakity", "email": "prakity@marvell.com", "time": "Thu Jul 07 09:04:55 2011 -0700" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Jul 13 14:54:37 2011 -0400" }, "message": "mmc: core: Bus width testing needs to handle suspend/resume\n\nOn reading the ext_csd for the first time (in 1 bit mode), save the\next_csd information needed for bus width compare.\n\nOn every pass we make re-reading the ext_csd, compare the data\nagainst the saved ext_csd data.\n\nThis fixes a regression introduced in 3.0-rc1 by 08ee80cc397ac1a3\n(\"mmc: core: eMMC bus width may not work on all platforms\"), which\nincorrectly assumed we would be re-reading the ext_csd at resume-\ntime.\n\nSigned-off-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "8c1c77ff9be27137fa7cbbf51efedef1a2ae915b", "tree": "cdbd09cac5f5d1c6eb5ec4257dc478c6acca70c5", "parents": [ "f3ae1c75203535f65448517e46c8dd70a56b6c71", "08ee80cc397ac1a306ca689a22ede954d92d0db1" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 25 16:55:55 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 25 16:55:55 2011 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: (75 commits)\n mmc: core: eMMC bus width may not work on all platforms\n mmc: sdhci: Auto-CMD23 fixes.\n mmc: sdhci: Auto-CMD23 support.\n mmc: core: Block CMD23 support for UHS104/SDXC cards.\n mmc: sdhci: Implement MMC_CAP_CMD23 for SDHCI.\n mmc: core: Use CMD23 for multiblock transfers when we can.\n mmc: quirks: Add/remove quirks conditional support.\n mmc: Add new VUB300 USB-to-SD/SDIO/MMC driver\n mmc: sdhci-pxa: Add quirks for DMA/ADMA to match h/w\n mmc: core: duplicated trial with same freq in mmc_rescan_try_freq()\n mmc: core: add support for eMMC Dual Data Rate\n mmc: core: eMMC signal voltage does not use CMD11\n mmc: sdhci-pxa: add platform code for UHS signaling\n mmc: sdhci: add hooks for setting UHS in platform specific code\n mmc: core: clear MMC_PM_KEEP_POWER flag on resume\n mmc: dw_mmc: fixed wrong regulator_enable in suspend/resume\n mmc: sdhi: allow powering down controller with no card inserted\n mmc: tmio: runtime suspend the controller, where possible\n mmc: sdhi: support up to 3 interrupt sources\n mmc: sdhi: print physical base address and clock rate\n ...\n" }, { "commit": "8edf63710bd43e62d59bfe017df542fa0713bbb3", "tree": "98641f28d6d3ce2ca5c021de20f8dec35fb8affe", "parents": [ "f0d89972b01798cf9d245dfa1cacfa0ee78a3593" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon May 23 15:06:39 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed May 25 16:51:40 2011 -0400" }, "message": "mmc: sdhci: Auto-CMD23 support.\n\nEnables Auto-CMD23 support where available (SDHCI 3.0 controllers)\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nTested-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "f0d89972b01798cf9d245dfa1cacfa0ee78a3593", "tree": "a3e69fc95825971384798eac4281148db837f891", "parents": [ "e89d456fcdde2df008c032bf928e69e628e07a28" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon May 23 15:06:38 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed May 25 16:49:03 2011 -0400" }, "message": "mmc: core: Block CMD23 support for UHS104/SDXC cards.\n\nSD cards operating at UHS104 or better support SET_BLOCK_COUNT.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nReviewed-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "e89d456fcdde2df008c032bf928e69e628e07a28", "tree": "ecc1942bea556086e015bdb6a6a548ad6e3a8957", "parents": [ "d0c97cfb81ebc5b416c0f92fa2fc18d2773e3023" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon May 23 15:06:37 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed May 25 16:49:00 2011 -0400" }, "message": "mmc: sdhci: Implement MMC_CAP_CMD23 for SDHCI.\n\nImplements support for multiblock transfers bounded\nby SET_BLOCK_COUNT (CMD23).\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "d0c97cfb81ebc5b416c0f92fa2fc18d2773e3023", "tree": "dbf0fa49bdad896d283a7f392c156483d9687d4b", "parents": [ "c59de9287993b5c36f9005f745a3ce0b1008131d" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon May 23 15:06:36 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed May 25 16:48:46 2011 -0400" }, "message": "mmc: core: Use CMD23 for multiblock transfers when we can.\n\nCMD23-prefixed instead of open-ended multiblock transfers\nhave a performance advantage on some MMC cards.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "c59de9287993b5c36f9005f745a3ce0b1008131d", "tree": "f9b4017f54beea7657697bd279266aff2b299c7b", "parents": [ "88095e7b473a3d9ec3b9c60429576e9cbd327c89" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon May 23 15:06:35 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:54:01 2011 -0400" }, "message": "mmc: quirks: Add/remove quirks conditional support.\n\nConditional add/remove quirks for MMC and SD.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "4c4cb171054230c2e58ed6574d7faa1871c75bbe", "tree": "8ba336234def08a99ae98d29047da69de41cdcb0", "parents": [ "261bbd463a091b939770255d559bbc89b1bad568" ], "author": { "name": "Philip Rakity", "email": "prakity@marvell.com", "time": "Fri May 13 11:17:18 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:58 2011 -0400" }, "message": "mmc: core: add support for eMMC Dual Data Rate\n\neMMC voltage change not required for 1.8V. 3.3V and 1.8V vcc\nare capable of doing DDR. vccq of 1.8v is not required.\n\nSigned-off-by: Philip Rakity \u003cprakity@marvell.com\u003e\nReviewed-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "2595880481ac894d390365092de9aaf92b44e147", "tree": "4ab065140c59e8b68e661926bfaa588e4a7e2a0a", "parents": [ "7311bef0697bcfbbcb898c3c22e61e23f203ae9d" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed May 11 16:51:15 2011 +0000" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:55 2011 -0400" }, "message": "mmc: sdhi: allow powering down controller with no card inserted\n\nSupply a link to TMIO private data for platforms to implement their\nown card detection.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "06e8935febe687e2a561707d4c7ca4245d261dbe", "tree": "0eef896f5b1614576fb0a1b744b4f87e8124f515", "parents": [ "253d6a280f77a9b61a76f9b1bfb83545fbd58726" ], "author": { "name": "Stefan Nilsson XK", "email": "stefan.xk.nilsson@stericsson.com", "time": "Wed May 11 17:48:05 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:50 2011 -0400" }, "message": "mmc: sdio: optimized SDIO IRQ handling for single irq\n\nIf there is only 1 function interrupt registered it is possible to\nimprove performance by directly calling the irq handler and avoiding\nthe overhead of reading the CCCR registers.\n\nSigned-off-by: Per Forlin \u003cper.forlin@linaro.org\u003e\nAcked-by: Ulf Hansson \u003culf.hansson@stericsson.com\u003e\nReviewed-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "cf2b5eea1ea0ff9b3184bc6771bcb93a9fdcd1d9", "tree": "36288f760fb7556952f8365c3c0cad6b445b04f6", "parents": [ "c3ed3877625f10d600b0eca2ca48a68c46aed660" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:19:07 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:48 2011 -0400" }, "message": "mmc: sdhci: add support for retuning mode 1\n\nHost Controller v3.00 can support retuning modes 1,2 or 3 depending on\nthe bits 46-47 of the Capabilities register. Also, the timer count for\nretuning is indicated by bits 40-43 of the same register. We initialize\ntimer_list for retuning the first time we execute tuning procedure. This\ncondition is indicated by SDHCI_NEEDS_RETUNING not being set. Since\nretuning mode 1 sets a limit of 4MB on the maximum data length, we set\nmax_blk_count appropriately. Once the tuning timer expires, we set\nSDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning\nprocedure before sending the next command. We need to restore mmc_request\nstructure after executing retuning procedure since host-\u003emrq is used\ninside the procedure to send CMD19. We also disable and re-enable this\nflag during suspend and resume respectively, as per the spec v3.00.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "c3ed3877625f10d600b0eca2ca48a68c46aed660", "tree": "d8170541551dca7abcefa118c4681d7294e3456d", "parents": [ "4d55c5a13a189a80d40383f02c8026f9a87d7c87" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:19:06 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:48 2011 -0400" }, "message": "mmc: sdhci: add support for programmable clock mode\n\nHost Controller v3.00 supports programmable clock mode as an optional\nfeature. The support for this mode is indicated by non-zero value in\nbits 48-55 of the Capabilities register. If supported, the actual\nvalue of Clock Multiplier is one more than the value provided in the\nbit fields. We only set Clock Generator Select (bit 5) and SDCLK\nFrequency Select (bits 8-15) of the Clock Control register in case\nPreset Value Enable is not set, otherwise these fields are automatically\nset by the Host Controller based on the UHS mode selected. Also, since\nthe maximum and minimum clock frequency in this mode can be\n(Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively,\nf_max and f_min have been recalculated to reflect this change.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "4d55c5a13a189a80d40383f02c8026f9a87d7c87", "tree": "6151dd86bac16adf96e7aefb6bc0ca6604a0ebc8", "parents": [ "b513ea250eb7c36a8afb3df938d632ca6b4df7cd" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:19:05 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:47 2011 -0400" }, "message": "mmc: sdhci: enable preset value after uhs initialization\n\nAccording to the Host Controller spec v3.00, setting Preset Value Enable\nin the Host Control2 register lets SDCLK Frequency Select, Clock Generator\nSelect and Driver Strength Select to be set automatically by the Host\nController based on the UHS-I mode set. This patch enables this feature.\nSince Preset Value Enable makes sense only for UHS-I cards, we enable this\nfeature after successfull UHS-I initialization. We also reset Preset Value\nEnable next time before initialization.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "b513ea250eb7c36a8afb3df938d632ca6b4df7cd", "tree": "41b597f488ffa21c675f49bd8c8ea00d177125e2", "parents": [ "3a3035114307cd55e024662bb295a87b849f0bd4" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:19:04 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:46 2011 -0400" }, "message": "mmc: sd: add support for tuning during uhs initialization\n\nHost Controller needs tuning during initialization to operate SDR50\nand SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is\nindicated by bit 45 of the Host Controller Capabilities register.\nA new command CMD19 has been defined in the Physical Layer spec\nv3.01 to request the card to send tuning pattern.\n\nWe enable Buffer Read Ready interrupt at the very begining of tuning\nprocedure, because that is the only interrupt generated by the Host\nController during tuning. We program the block size to 64 in the\nBlock Size register. We make sure that DMA Enable and Multi Block\nSelect in the Transfer Mode register are set to 0 before actually\nsending CMD19. The tuning block is sent by the card to the Host\nController using DAT lines, so we set Data Present Select (bit 5) in\nthe Command register. The Host Controller is responsible for doing\nthe verfication of tuning block sent by the card at the hardware\nlevel. After sending CMD19, we wait for Buffer Read Ready interrupt.\nIn case we don\u0027t receive an interrupt after the specified timeout\nvalue, we fall back on fixed sampling clock by setting Execute\nTuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2\nregister to 0. Before exiting the tuning procedure, we disable Buffer\nRead Ready interrupt and re-enable other interrupts.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "3a3035114307cd55e024662bb295a87b849f0bd4", "tree": "764f881c7a677641abaa211128f27a37c9613d90", "parents": [ "5371c927bcd06a5c9dd6785bab2d452b87d9abc6" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:19:03 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:46 2011 -0400" }, "message": "mmc: sd: report correct speed and capacity of uhs cards\n\nSince only UHS-I cards respond with S18A set in response to ACMD41,\nwe set the card as ultra-high-speed after successfull initialization.\nWe need to decide whether a card is SDXC based on the C_SIZE field\nof CSDv2.0 register. According to Physical Layer spec v3.01, the\nminimum value of C_SIZE for SDXC card is 00FFFFh.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "5371c927bcd06a5c9dd6785bab2d452b87d9abc6", "tree": "71add97be08e93fcb5ac2bfcc44fc66d8f2b92df", "parents": [ "49c468fcf878d2c86e31920cf54aa90c88418a66" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:19:02 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:45 2011 -0400" }, "message": "mmc: sd: set current limit for uhs cards\n\nWe decide on the current limit to be set for the card based on the\nCapability of Host Controller to provide current at 1.8V signalling,\nand the maximum current limit of the card as indicated by CMD6\nmode 0. We then set the current limit for the card using CMD6 mode 1.\nAs per the Physical Layer Spec v3.01, the current limit switch is\nonly applicable for SDR50, SDR104, and DDR50 bus speed modes. For\nother UHS-I modes, we set the default current limit of 200mA.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "49c468fcf878d2c86e31920cf54aa90c88418a66", "tree": "d8088bf8fb1a011f05ebbdefef49f2a6f4739432", "parents": [ "758535c4e3cdd2b5b09565d9651aaa541aac3de8" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:19:01 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:45 2011 -0400" }, "message": "mmc: sd: add support for uhs bus speed mode selection\n\nThis patch adds support for setting UHS-I bus speed mode during UHS-I\ninitialization procedure. Since both the host and card can support\nmore than one bus speed, we select the highest speed based on both of\ntheir capabilities. First we set the bus speed mode for the card using\nCMD6 mode 1, and then we program the host controller to support the\nrequired speed mode. We also set High Speed Enable in case one of the\nUHS-I modes is selected. We take care to reset SD clock before setting\nUHS mode in the Host Control2 register, and then re-enable it as per\nthe Host Controller spec v3.00. We then set the clock frequency for\nthe UHS-I mode selected.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "d6d50a15a2897d4133d536dd4343b5cf21163db3", "tree": "b56723c1b3e74ae2ae9e9d7fb39e916cdfa74958", "parents": [ "013909c4ffd16ded4895528b856fd8782df04dc6" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:18:59 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 23:53:24 2011 -0400" }, "message": "mmc: sd: add support for driver type selection\n\nThis patch adds support for setting driver strength during UHS-I\ninitialization procedure. Since UHS-I cards set S18A (bit 24) in\nresponse to ACMD41, we use this as a base for UHS-I initialization.\nWe modify the parameter list of mmc_sd_get_cid() so that we can\nsave the ROCR from ACMD41 to check whether bit 24 is set.\n\nWe decide whether the Host Controller supports A, C, or D driver\ntype depending on the Capabilities register. Driver type B is\nsuported by default. We then set the appropriate driver type for\nthe card using CMD6 mode 1. As per Host Controller spec v3.00, we\nset driver type for the host only if Preset Value Enable in the\nHost Control2 register is not set. SDHCI_HOST_CONTROL has been\nrenamed to SDHCI_HOST_CONTROL1 to conform to the spec.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "013909c4ffd16ded4895528b856fd8782df04dc6", "tree": "b74fe0c34dfd3c2348497b1aa3a34f5132ca4822", "parents": [ "f2119df6b764609af4baceb68caf1e848c1c8aa7" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:18:58 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:04:40 2011 -0400" }, "message": "mmc: sd: query function modes for uhs cards\n\nSD cards which conform to Physical Layer Spec v3.01 can support\nadditional Bus Speed Modes, Driver Strength, and Current Limit\nother than the default values. We use CMD6 mode 0 to read these\nadditional card functions. The values read here will be used\nduring UHS-I initialization steps.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "f2119df6b764609af4baceb68caf1e848c1c8aa7", "tree": "3c234b150d7add419cd07e15929b94b8c3baec63", "parents": [ "cb87ea28ed9e75a41eb456bfcb547b4e6f10e750" ], "author": { "name": "Arindam Nath", "email": "arindam.nath@amd.com", "time": "Thu May 05 12:18:57 2011 +0530" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:04:38 2011 -0400" }, "message": "mmc: sd: add support for signal voltage switch procedure\n\nHost Controller v3.00 adds another Capabilities register. Apart\nfrom other things, this new register indicates whether the Host\nController supports SDR50, SDR104, and DDR50 UHS-I modes. The spec\ndoesn\u0027t mention about explicit support for SDR12 and SDR25 UHS-I\nmodes, so the Host Controller v3.00 should support them by default.\nAlso if the controller supports SDR104 mode, it will also support\nSDR50 mode as well. So depending on the host support, we set the\ncorresponding MMC_CAP_* flags. One more new register. Host Control2\nis added in v3.00, which is used during Signal Voltage Switch\nprocedure described below.\n\nSince as per v3.00 spec, UHS-I supported hosts should set S18R\nto 1, we set S18R (bit 24) of OCR before sending ACMD41. We also\nneed to set XPC (bit 28) of OCR in case the host can supply \u003e150mA.\nThis support is indicated by the Maximum Current Capabilities\nregister of the Host Controller.\n\nIf the response of ACMD41 has both CCS and S18A set, we start the\nsignal voltage switch procedure, which if successfull, will switch\nthe card from 3.3V signalling to 1.8V signalling. Signal voltage\nswitch procedure adds support for a new command CMD11 in the\nPhysical Layer Spec v3.01. As part of this procedure, we need to\nset 1.8V Signalling Enable (bit 3) of Host Control2 register, which\nif remains set after 5ms, means the switch to 1.8V signalling is\nsuccessfull. Otherwise, we clear bit 24 of OCR and retry the\ninitialization sequence. When we remove the card, and insert the\nsame or another card, we need to make sure that we start with 3.3V\nsignalling voltage. So we call mmc_set_signal_voltage() with\nMMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling\nvoltage before we actually start initializing the card.\n\nTested by Zhangfei Gao with a Toshiba uhs card and general hs card,\non mmp2 in SDMA mode.\n\nSigned-off-by: Arindam Nath \u003carindam.nath@amd.com\u003e\nReviewed-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nAcked-by: Zhangfei Gao \u003czhangfei.gao@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "cb87ea28ed9e75a41eb456bfcb547b4e6f10e750", "tree": "e3fe4a653bd96815c650dd9f5db11edc6b39b0db", "parents": [ "641c3187b9d53cfd4c23b0ce2ab18a13d5e775e5" ], "author": { "name": "John Calixto", "email": "john.calixto@modsystems.com", "time": "Tue Apr 26 18:56:29 2011 -0400" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:02:54 2011 -0400" }, "message": "mmc: core: Add mmc CMD+ACMD passthrough ioctl\n\nAllows appropriately-privileged applications to send CMD (normal) and ACMD\n(application-specific; preceded with CMD55) commands to cards/devices on\nthe mmc bus. This is primarily useful for enabling the security\nfunctionality built in to every SD card.\n\nIt can also be used as a generic passthrough (e.g. to enable virtual\nmachines to control mmc bus devices directly). However, this use case has\nnot been tested rigorously. Generic passthrough testing was only conducted\nfor a few non-security opcodes to prove the feasibility of the passthrough.\n\nSince any opcode can be sent using this passthrough, it is very possible to\nrender the card/device unusable. Applications that use this ioctl must\nhave CAP_SYS_RAWIO.\n\nSecurity commands tested on TI PCIxx12 (SDHCI), Sigma Designs SMP8652 SoC,\nTI OMAP3621/OMAP3630 SoC, Samsung S5PC110 SoC, Qualcomm MSM7200A SoC.\n\nSigned-off-by: John Calixto \u003cjohn.calixto@modsystems.com\u003e\nReviewed-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nReviewed-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "82b0e23a295cc58d1290017ee97a40956ad68d94", "tree": "f3f140be979623ae8b83b79841eb842858ed054b", "parents": [ "f06c9153f5ecd47dfed23f87b9d08e42ff0e4170" ], "author": { "name": "Takashi Iwai", "email": "tiwai@suse.de", "time": "Thu Apr 21 20:26:38 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:02:42 2011 -0400" }, "message": "mmc: sdhci: Fix read-only detection with JMicron 388 chip\n\nOn HP laptops with JMicron 388 chip, the write-locked SD card isn\u0027t\ndetected correctly as read-only in many cases. This is because the\nPRESENT_STATE register becomes unsable just after plugging, and it\nreturns the WRITE_PROTECT bit wrongly at the first read.\n\nThis patch fixes the read-only detection by adding a new sdhci quirk\nindicating to check the register more intensively with a relatively\nlong delay.\n\nThe patch is tested with 2.6.39-rc4 kernel.\n\nCc: Aries Lee \u003carieslee@jmicron.com\u003e\nSigned-off-by: Takashi Iwai \u003ctiwai@suse.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "6a7a6b45f454686a1549729bfbae31f0b3b595d6", "tree": "dafdeae86c51d07c0115065114906d438781a50d", "parents": [ "f6a03cbf43e586211f8ea088148c8ecd3fc4b5be" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Tue Apr 12 15:06:53 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:01:34 2011 -0400" }, "message": "mmc: quirks: Fix erase/trim for certain SanDisk cards.\n\nCMD38 argument is passed through EXT_CSD[113].\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "371a689f64b0da140c3bcd3f55305ffa1c3a58ef", "tree": "c0dff82d668378d395cb22ce33cd93e6dafef9eb", "parents": [ "1a258db6f396e26c2c00b19c0107a891895d4584" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon Apr 11 18:10:25 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:01:21 2011 -0400" }, "message": "mmc: MMC boot partitions support.\n\nAllows device MMC boot partitions to be accessed. MMC partitions are\ntreated effectively as separate block devices on the same MMC card.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "d3a8d95dcbb726b9cf0bbc166b2473bdd236c88c", "tree": "10c6e435f28f6d61562ce54291063913e59dc0b3", "parents": [ "a3c7778f8153b9e4eceea6738973280b9e63c618" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon Apr 11 16:13:43 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:01:13 2011 -0400" }, "message": "mmc: core: Allow setting CMD timeout for CMD6 (SWITCH).\n\nCMD6 is an R1B-type command, where DAT is used as busy. Depending\non register written using CMD6, timeout value can be different\nas per spec.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "eaa02f751ff4f8abfc2e55a15c20a5a274244418", "tree": "c521e84176e140acdc03926683b525250ceee777", "parents": [ "853c6cac0dc0d9d330deb5b48c19eebafaed1841" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon Apr 11 16:13:41 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:01:05 2011 -0400" }, "message": "mmc: core: Rename erase_timeout to cmd_timeout_ms.\n\nRenames erase_timeout to cmd_timeout_ms inside struct mmc_command.\nFirst step to making host honor timeouts for non-data-transfer\ncommands. Cleans up erase timeout code.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "853c6cac0dc0d9d330deb5b48c19eebafaed1841", "tree": "88bbcb5a7b32f23dba7d42d7e61d55ff2d1fc442", "parents": [ "32780cd1350e651e68bdf33b7f5b009d21d5b794" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Tue Apr 12 12:59:09 2011 -0400" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:00:59 2011 -0400" }, "message": "mmc: quirks: fix truncation warnings\n\nFix data truncation warnings: .manfid is not unsigned long:\n\ndrivers/mmc/core/quirks.c:36: warning: large integer implicitly truncated to unsigned type\ndrivers/mmc/core/quirks.c:40: warning: large integer implicitly truncated to unsigned type\ndrivers/mmc/core/quirks.c:43: warning: large integer implicitly truncated to unsigned type\ndrivers/mmc/core/quirks.c:46: warning: large integer implicitly truncated to unsigned type\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "32780cd1350e651e68bdf33b7f5b009d21d5b794", "tree": "e8e86350a3eca20cca098b488e596d2b76ecaea8", "parents": [ "f317dfeb86c83d03304a74ce5426a69422b79547" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Mon Apr 11 17:02:15 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:00:54 2011 -0400" }, "message": "mmc: quirks: Extends card quirks with MMC/SD quirks matching the CID.\n\nThe current mechanism is SDIO-only. This allows us to create\nfunction-specific quirks, without creating messy Kconfig dependencies,\nor polluting core/ with function-specific code.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "2059a02dcb84236f9db9197fa9b00418d7b8465b", "tree": "d51b9fe1b70a7e3e7d5c24912637d22a04bf35b5", "parents": [ "0b4043d70af5871908864fa725821bc8e667542d" ], "author": { "name": "Ohad Ben-Cohen", "email": "ohad@wizery.com", "time": "Tue Apr 05 18:02:25 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 21:00:01 2011 -0400" }, "message": "mmc: add MMC_QUIRK_DISABLE_CD\n\n006ebd5d introduced sdio_disable_cd(), which disconnects the pull-up\nresistor on CD/DAT[3] (pin 1) of the card.\n\nMake it possible to start using sdio_disable_cd() by introducing\nMMC_QUIRK_DISABLE_CD.\n\nSigned-off-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "eab4068795d670b065164096805cbf15a19e9690", "tree": "5fb62e0a18163fe2c46044cb23c276a9dad64477", "parents": [ "6b93d01fe5971951911a070f51f412d50e9536dc" ], "author": { "name": "Ohad Ben-Cohen", "email": "ohad@wizery.com", "time": "Tue Apr 05 17:50:14 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 20:59:52 2011 -0400" }, "message": "mmc: add MMC_QUIRK_NONSTD_FUNC_IF\n\nIntroduce MMC_QUIRK_NONSTD_FUNC_IF to ignore the \"SDIO Standard Function\ninterface code\" as indicated by the card\u0027s FBR, and instead treat all\nfunctions as non-standard interfaces.\n\nThis is required to prevent standard drivers from facing\nerrors when trying to communicate with SDIO cards that erroneously\nindicate standard function interface codes.\n\nSigned-off-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "6b93d01fe5971951911a070f51f412d50e9536dc", "tree": "0e0221f3af9f954bd60e469f94810730899ee374", "parents": [ "a5e9425d2010978c5f85986cc70a9fa0c0d5b912" ], "author": { "name": "Ohad Ben-Cohen", "email": "ohad@wizery.com", "time": "Tue Apr 05 17:43:21 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 20:59:47 2011 -0400" }, "message": "mmc: do not switch to 1-bit mode if not required\n\n6b5eda36 followed SDIO spec part E1 section 8, which states that\nin case SDIO interrupts are being used to wake up a suspended host,\nthen it is required to switch to 1-bit mode before stopping the clock.\n\nBefore switching to 1-bit mode (or back to 4-bit mode on resume),\nmake sure that SDIO interrupts are really being used to wake the host.\n\nThis is helpful for devices which have an external irq line (e.g.\nwl1271), and do not use SDIO interrupts to wake up the host.\n\nIn this case, switching to 1-bit mode (and back to 4-bit mode on resume)\nis not necessary.\n\nReported-by: Eliad Peller \u003celiad@wizery.com\u003e\nSigned-off-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "a5e9425d2010978c5f85986cc70a9fa0c0d5b912", "tree": "2d58d5b79f3e0b2fe30edbb5fc1b6808b7576d81", "parents": [ "f4c5522b0a8827f39f83f928961d87e081bfe71c" ], "author": { "name": "Ohad Ben-Cohen", "email": "ohad@wizery.com", "time": "Tue Apr 05 17:43:20 2011 +0300" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 20:59:43 2011 -0400" }, "message": "mmc: mmc_card_keep_power cleanups\n\nmmc_card_is_powered_resumed is a mouthful; instead, simply use\nmmc_card_keep_power, which also better explains the purpose of\nthe macro.\n\nEmploy mmc_card_keep_power() where possible.\n\nSigned-off-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "f4c5522b0a8827f39f83f928961d87e081bfe71c", "tree": "3c2126f0adb2a3444b2fd152cc1a880c192c9d77", "parents": [ "766a6bf6e987ff5f5085c614b5a62a55006b6a7e" ], "author": { "name": "Andrei Warkentin", "email": "andreiw@motorola.com", "time": "Thu Mar 31 18:40:00 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 20:59:38 2011 -0400" }, "message": "mmc: Reliable write support.\n\nAllows reliable writes to be used for MMC writes. Reliable writes are used\nto service write REQ_FUA/REQ_META requests. Handles both the legacy and\nthe enhanced reliable write support in MMC cards.\n\nSigned-off-by: Andrei Warkentin \u003candreiw@motorola.com\u003e\nReviewed-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "41e2a4893566ced3c46af15df5b727326881e47d", "tree": "62263d47bf1f034857e8138095af724aa61c53bb", "parents": [ "7c21738efd0b5e8c2a9ac2440e7ffbf432d6f239" ], "author": { "name": "Philip Rakity", "email": "prakity@marvell.com", "time": "Sat Mar 19 14:10:33 2011 -0400" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue May 24 20:59:13 2011 -0400" }, "message": "mmc: Ensure linux starts in eMMC user partition\n\nuBoot sometimes leaves eMMC pointing to the private boot partition.\nEnsure we always start looking at the user partition.\n\nSigned-off-by: Philip Rakity \u003cprakity@marvell.com\u003e\nSigned-off-by: Bruce Clemens \u003cbpclemens@marvell.com\u003e\nSigned-off-by: Mark F. Brown \u003cmarkb@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "86f315bbb2374f1f077500ad131dd9b71856e697", "tree": "d1e70a9bfaa1665bef1b085f6f8ce4a0498e90d2", "parents": [ "eed631e0d741d1a1067cfc6d709fdf2363126f9c" ], "author": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Mon May 16 11:32:26 2011 -0400" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Mon May 16 11:32:26 2011 -0400" }, "message": "Revert \"mmc: fix a race between card-detect rescan and clock-gate work instances\"\n\nThis reverts commit 26fc8775b51484d8c0a671198639c6d5ae60533e, which has\nbeen reported to cause boot/resume-time crashes for some users:\n\nhttps://bbs.archlinux.org/viewtopic.php?id\u003d118751.\n\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\nCc: \u003cstable@kernel.org\u003e\n" }, { "commit": "26fc8775b51484d8c0a671198639c6d5ae60533e", "tree": "df906e9e78fada3739e576ba0546b726de58f585", "parents": [ "f69475142136c8ad9b9c717aea2ff907aed9f863" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Fri Apr 15 20:08:19 2011 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Wed Apr 27 19:16:12 2011 -0400" }, "message": "mmc: fix a race between card-detect rescan and clock-gate work instances\n\nCurrently there is a race in the MMC core between a card-detect\nrescan work and the clock-gating work, scheduled from a command\ncompletion. Fix it by removing the dedicated clock-gating mutex\nand using the MMC standard locking mechanism instead.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Simon Horman \u003chorms@verge.net.au\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "25985edcedea6396277003854657b5f3cb31a628", "tree": "f026e810210a2ee7290caeb737c23cb6472b7c38", "parents": [ "6aba74f2791287ec407e0f92487a725a25908067" ], "author": { "name": "Lucas De Marchi", "email": "lucas.demarchi@profusion.mobi", "time": "Wed Mar 30 22:57:33 2011 -0300" }, "committer": { "name": "Lucas De Marchi", "email": "lucas.demarchi@profusion.mobi", "time": "Thu Mar 31 11:26:23 2011 -0300" }, "message": "Fix common misspellings\n\nFixes generated by \u0027codespell\u0027 and manually reviewed.\n\nSigned-off-by: Lucas De Marchi \u003clucas.demarchi@profusion.mobi\u003e\n" }, { "commit": "cba179aec779b364a683906b99e23014c7652e8e", "tree": "f88c1be6d919591ab6ee41c736248437887a8963", "parents": [ "5fd0157901d5a8f497f3d3b95cb4beebf1641d1b" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Thu Mar 24 09:48:36 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Mar 26 15:58:50 2011 -0400" }, "message": "mmc: tmio_mmc: Move some defines into a shared header\n\nAlso add TMIO_BBS.\n\nThis allows these defines to also be used by zboot.\n\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "42051e8a7bce76ebd3cd201704ee2427120636e1", "tree": "f62527fca5ea9d247faffa9bda2539d996b18068", "parents": [ "4fbc5ece430bc2890edc90a112c742844130f943" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Mon Mar 14 09:52:33 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Fri Mar 25 10:39:23 2011 -0400" }, "message": "mmc: tmio: convert the SDHI MMC driver from MFD to a platform driver\n\nOn sh-mobile platforms the SDHI driver was using the tmio_mmc SD/SDIO\nMFD cell driver. Now that the tmio_mmc driver has been split into a\ncore and a separate MFD glue, we can support SDHI natively without the\nneed to emulate an MFD controller. This also allows to support systems\nwith an on-SoC SDHI controller and a separate MFD with a TMIO core.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "9d9659b6c0ebf7dde65ebada4c67980818245913", "tree": "05335a7e2d03350309d617834997d7fe9c395d28", "parents": [ "a6558c2d07d5c955fbb0290f68c27164a5567b9a" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Thu Mar 24 07:04:38 2011 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Fri Mar 25 01:24:57 2011 +0900" }, "message": "mmc: Add MMC_PROGRESS_*\n\nThis is my second attempt to make this enum generally available.\nThe first attempt added MMCIF_PROGRESS_* to include/linux/mmc/sh_mmcif.h.\nHowever this is not sufficiently generic as the enum will be\nused by SDHI boot code.\n\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "c07946a3350244d7c3d9bc1032325e04dd11575b", "tree": "8cab4261ebbdb857e7f46fe2dc6ed3d4652369f4", "parents": [ "e61cf1184d72e574460492fd6c6b6d8a3ace2089" ], "author": { "name": "Jaehoon Chung", "email": "jh80.chung@samsung.com", "time": "Fri Feb 25 11:08:14 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Thu Mar 17 15:35:22 2011 -0400" }, "message": "mmc: dw_mmc: support mmc power control with regulator\n\nThis patch adds support for power regulators.\n\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "e61cf1184d72e574460492fd6c6b6d8a3ace2089", "tree": "2a95d08ee1b19a7cbeadc7ca0622f93bbcc9e3f2", "parents": [ "fc3d7720541d4b70cbae25ac121d7e6343125090" ], "author": { "name": "Jaehoon Chung", "email": "jh80.chung@samsung.com", "time": "Thu Mar 17 20:32:33 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Thu Mar 17 15:35:20 2011 -0400" }, "message": "mmc: dw_mmc: fix suspend/resume operation\n\nThis patch is related to re-init processing on suspend/resume.\n\nWhen card is resuming, some register is reset. If card is removable,\nmaybe controller should be rescan for card. But if assume card is\nnon-removable, need to restore the old value at registers.\n\nWe store the value of FIFOTH at probe time and then restore it in\ndw_mci_resume().\n\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "fc3d7720541d4b70cbae25ac121d7e6343125090", "tree": "f1ca22f9e6363c2ddfc84dfdc6e4992299e4f93a", "parents": [ "860cfe796c793bfad1e666de9600852f2d653c57" ], "author": { "name": "Jaehoon Chung", "email": "jh80.chung@samsung.com", "time": "Fri Feb 25 11:08:15 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Thu Mar 17 15:35:18 2011 -0400" }, "message": "mmc: dw_mmc: add quirks for unreliable card detect, and capabilities\n\nThis patch adds quirks and capabilities to platdata.\n\nSome cards don\u0027t use the CDn pin; in that case, we assume the card\u0027s\ninserted. Some boards need other capabilities. So, we add capabilities\nin the board\u0027s platdata.\n\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nSigned-off-by: Kyungmin Park \u003ckyungmin.park@samsung.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "ab1efd271704416c9e6e9cb4e5f58e7e4c4260e6", "tree": "6199d0a57592537c2e1f050754415225561c6b48", "parents": [ "0aab3995485b8a994bf29a995a008c9ea4a28054" ], "author": { "name": "Ulf Hansson", "email": "ulf.hansson@stericsson.com", "time": "Wed Mar 09 09:11:02 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Thu Mar 17 15:35:11 2011 -0400" }, "message": "mmc: core: export function mmc_do_release_host()\n\nWhen using mmc_try_claim_host the corresponding release\nfunction is mmc_do_release_host, which then also must\nbe exported.\n\nReviewed-by: Jonas Aberg \u003cjonas.aberg@stericsson.com\u003e\nReviewed-by: Sebastian Rasmussen \u003csebastian.rasmussen@stericsson.com\u003e\nSigned-off-by: Ulf Hansson \u003culf.hansson@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "37b7785e3ac5128809340eaeb791ca7a471c4e32", "tree": "ff7744cb148e22cf36c3801eb00b7a2a2ee98567", "parents": [ "449bdc2d9d62794246351d10dd4534a239bf06b6" ], "author": { "name": "Jaehoon Chung", "email": "jh80.chung@samsung.com", "time": "Thu Feb 17 13:09:04 2011 +0900" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue Mar 15 13:49:28 2011 -0400" }, "message": "mmc: dw_mmc: modify quirks bit-shift control\n\nIf we need some quirks, maybe add quirks in future\nBut now, quirks value set to integer..later we should be confused..\nSo I think that need bit-shift control.\n\nAnd If we need not any quirks, we didn\u0027t set anything..\n(Need not DW_MCI_QUIRK_NONE)\n\nSigned-off-by: Jaehoon Chung \u003cjh80.chung@samsung.com\u003e\nAcked-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "db9935000d95ae3f9702b7ff6ac0eef2319d8772", "tree": "86f75ca6ec0b73c728f19b0dd43e8702bef448bc", "parents": [ "57f0adc7eaaf4315d568e72069dbe48aa7e20995" ], "author": { "name": "Pierre Tardy", "email": "tardyp@gmail.com", "time": "Sun Feb 06 19:03:47 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue Mar 15 13:48:35 2011 -0400" }, "message": "mmc: add MMC_QUIRK_BROKEN_CLK_GATING\n\nSome sdio card are not following sdio standard, and do not work\nwhen the sdio bus\u0027s clock is gated.\n\nTo keep functionnality for all legacy driver, we turn this quirk on\nfor every sdio card.\nDrivers needs to disable the quirk manually when someone verifies that\ntheir supported card works with clock gating.\n\nSigned-off-by: Pierre Tardy \u003ctardyp@gmail.com\u003e\nAcked-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "57f0adc7eaaf4315d568e72069dbe48aa7e20995", "tree": "233c66fd4f21b977f532702ce9427023b2e53e09", "parents": [ "66c036e0142fed2484d58a2d3c7a4d21ba32b6a6" ], "author": { "name": "Pierre Tardy", "email": "pierre.tardy@intel.com", "time": "Sun Feb 06 19:03:46 2011 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue Mar 15 13:48:33 2011 -0400" }, "message": "mmc: add per device quirk placeholder\n\nSome cards have quirks valid for every platforms using current\nplatform quirk hooks leads to a lot of code and debug duplication.\n\nSo we inspire a bit from what exists in PCI subsystem and do our own\nper vendorid/deviceid quirk. We still drop the complexity of the pci\nquirk system (with special section tables, and so on).\nThat can be added later if needed.\n\nSigned-off-by: Pierre Tardy \u003cpierre.tardy@intel.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "709de99df0ecf3102e7728fbd876a3591859f423", "tree": "f1adaa026531d3dcc93cf33c2e8ede84455ca46a", "parents": [ "cfd80652467717ca7346857d6d8c94503d74f3a3" ], "author": { "name": "Chuanxiao Dong", "email": "chuanxiao.dong@intel.com", "time": "Sat Jan 22 04:09:41 2011 +0800" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Tue Mar 15 13:48:01 2011 -0400" }, "message": "mmc: export eMMC4.4 enhanced area details to sysfs\n\nEnhanced area feature is a new feature defined in eMMC4.4 standard. This\nuser data area provides higher performance/reliability, at the expense\nof using twice the effective media space due to the area using SLC.\n\nThe MMC driver now reads out the enhanced area offset and size and adds\nthem to the device attributes in sysfs. Enabling the enhanced area can\nonly be done once, and should be done in manufacturing. To use this\nfeature, bit ERASE_GRP_DEF should also be set.\n\nDocumentation/ABI/testing/sysfs-devices-mmc describes the two new\nattributes.\n\nSigned-off-by: Chuanxiao Dong \u003cchuanxiao.dong@intel.com\u003e\nReviewed-by: Chris Ball \u003ccjb@laptop.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "bba958783b1b4cb0a9420f4e11082467132a334c", "tree": "9bdd12bf167d10040eb2eb16fe741211ffb82803", "parents": [ "9c4bc1c2befbbdce4b9fd526e67a7a2ea143ffa2" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Fri Jan 14 15:57:47 2011 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Fri Jan 14 15:57:47 2011 +0900" }, "message": "mmc: sh_mmcif: Convert to __raw_xxx() I/O accessors.\n\nWhen using the I/O accessors in raw mode from the boot stubs we don\u0027t\nwant to bother with any of the complexity associated with readl/writel\nand friends. Furthermore, utilization within the context of the host\ndriver itself is all performed on an ioremapped window, so using the\n__raw variants there doesn\u0027t pose any problem either.\n\nIf and when barriers need to be added in the future, these will need to\nbe explicitly written out, but this is so far not a concern for any of\nthe affected CPUs in question.\n\nThis fixes up the link error introduced by the ARM tree via its barrier\nrefactoring:\n\n\tarch/arm/boot/compressed/mmcif-sh7372.o: In function `mmcif_loader\u0027:\n\tmmcif-sh7372.c:(.text+0x9e8): undefined reference to `outer_cache\n\nFollowing the change in:\n\n\thttp://www.arm.linux.org.uk/developer/patches/viewpatch.php?id\u003d6275/1\n\nReported-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "83eb95b852902f952ba594447a796ad8146b9462", "tree": "33c199aeeae58b69ad8d6d2a33c2d96ba2b98ddf", "parents": [ "efb3e34b6176d30c4fe8635fa8e1beb6280cc2cd", "9bbe7b984096ac45586da2adf26c14069ecb79b2" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Wed Jan 12 14:37:42 2011 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Wed Jan 12 14:37:42 2011 +0900" }, "message": "Merge branch \u0027sh/sdio\u0027 into sh-latest\n" }, { "commit": "89e9fd32c6f4ed58cd6f6e3c3cf5b536a3f36100", "tree": "8117c319cd5d24132f10756e0993061c47515b2e", "parents": [ "239f6dcbab35c90240edf47293cec6e33ea2cf9a", "2f5998610ae315fa659ebe2ae0f1c02203b63d9a", "54b384634f7083bcacf9a9ed2e6f4c3d0a246e49" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Jan 11 13:05:15 2011 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Jan 11 13:05:15 2011 +0900" }, "message": "Merge branches \u0027sh/memchunk\u0027 and \u0027common/mmcif\u0027 into sh-latest\n" }, { "commit": "f95f3850f7a9e1d49ebc5b6e72e7cc3ec3685b0b", "tree": "2903746678fde809a1fcede6ce16cd9f45334214", "parents": [ "03d2bfc878e4dff9e596accc7b7eccf947804a3c" ], "author": { "name": "Will Newton", "email": "will.newton@gmail.com", "time": "Sun Jan 02 01:11:59 2011 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Jan 08 23:52:24 2011 -0500" }, "message": "mmc: dw_mmc: Add Synopsys DesignWare mmc host driver.\n\nThis adds the mmc host driver for the Synopsys DesignWare mmc\nhost controller, found in a number of embedded SoC designs.\n\nSigned-off-by: Will Newton \u003cwill.newton@imgtec.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nReviewed-by: Chris Ball \u003ccjb@laptop.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "30652aa36b58d57fcc1a0acce51e391bbb6edf5e", "tree": "80743c840e0456381b4e1aea223661eb694a976e", "parents": [ "c288b85554097a3d1271f935c48b442280b2db9e" ], "author": { "name": "Olof Johansson", "email": "olof@lixom.net", "time": "Sat Jan 01 18:37:32 2011 -0600" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Jan 08 23:52:23 2011 -0500" }, "message": "mmc: sdhci: add quirk for max len ADMA descriptors\n\nSome controllers misparse segment length 0 as being 0, not 65536. Add\na quirk to deal with it.\n\nSigned-off-by: Olof Johansson \u003colof@lixom.net\u003e\nReviewed-by: Chris Ball \u003ccjb@laptop.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "22113efd00491310da802f3b1a9a66cfcf415fac", "tree": "1faf6e99a591f9b6856bab6c8318eeeacb076051", "parents": [ "e6f29a8dc1602e170daf955233891a9130573a55" ], "author": { "name": "Aries Lee", "email": "arieslee@jmicron.com", "time": "Wed Dec 15 08:14:24 2010 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Jan 08 23:52:09 2011 -0500" }, "message": "mmc: Test bus-width for old MMC devices\n\nSome old MMC devices fail with the 4/8 bits the driver tries to use\nexclusively. This patch adds a test for the given bus setup and falls\nback to the lower bit mode (until 1-bit mode) when the test fails.\n\n[Major rework and refactoring by tiwai]\n[Quirk addition and many fixes by prakity]\n\nSigned-off-by: Aries Lee \u003carieslee@jmicron.com\u003e\nSigned-off-by: Takashi Iwai \u003ctiwai@suse.de\u003e\nSigned-off-by: Philip Rakity \u003cprakity@marvell.com\u003e\nTested-by: Philip Rakity \u003cprakity@marvell.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "080bc9774b6f1e3866747b18631bad26f47c22ce", "tree": "07ac4d1539b75036083d8b3c499e213fcca09cc4", "parents": [ "e594573d790bd7e269f05955d316b88f7be0c14a" ], "author": { "name": "Ohad Ben-Cohen", "email": "ohad@wizery.com", "time": "Sun Nov 28 07:21:29 2010 +0200" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Jan 08 22:48:17 2011 -0500" }, "message": "mmc: sdio: don\u0027t reinitialize nonremovable powered-resumed cards\n\nUpon system resume, SDIO core must reinitialize cards that were\npowered off during suspend.\n\nIf the card had its power kept during suspend (and thus it is\n\u0027powered-resumed\u0027), SDIO core performs only a limited reinitializing,\nmainly needed to make sure that the card wasn\u0027t removed/replaced.\n\nIf a __nonremovable__ card is powered-resumed, we can safely skip the\nreinitializing phase.\n\nNote: 9b966aa (mmc: sdio: fully reconfigure oldcard on resume) removed\nthe bus width reconfiguration since mmc_sdio_init_card already does it.\nIt is brought back now in case mmc_sdio_init_card is skipped.\n\nSigned-off-by: Ohad Ben-Cohen \u003cohad@wizery.com\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "8f230f454fe04ba326ffaead3a6b88dcf44eaf4b", "tree": "9f5c43b48aa84131f7b94b44e4d500e0ec271ba0", "parents": [ "150ee73d1b35936aafc5fd3b39a7291b1f66de07" ], "author": { "name": "Takashi Iwai", "email": "tiwai@suse.de", "time": "Wed Dec 08 10:04:30 2010 +0100" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Jan 08 22:48:04 2011 -0500" }, "message": "mmc: Add support for JMicron 388 SD/MMC controller\n\nJMicron 388 SD/MMC combo controller supports the 1.8V low-voltage for\nSD, but MMC doesn\u0027t work with the low-voltage, resulting in an error\nat probing.\n\nThis patch adds the support for multiple voltage mask per device type,\nso that SD works with 1.8V while MMC forces 3.3V. Here new ocr_avail_*\nfields for each device are introduced, so that the actual OCR mask is\nswitched dynamically.\n\nAlso, the restriction of low-voltage in core/sd.c is removed when the\nbit is allowed explicitly via ocr_avail_sd mask.\n\nThis patch was rewritten from scratch based on Aries\u0027 original code.\n\nSigned-off-by: Aries Lee \u003carieslee@jmicron.com\u003e\nSigned-off-by: Takashi Iwai \u003ctiwai@suse.de\u003e\nReviewed-by: Chris Ball \u003ccjb@laptop.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "04566831a703ae3ef4b49a2deae261c9ed26e020", "tree": "5dbf02cc4733de2959b5d40f848a74b758804c61", "parents": [ "26daa1ed40c6b31b4220581431982814c47c608a" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon Nov 08 21:36:50 2010 -0500" }, "committer": { "name": "Chris Ball", "email": "cjb@laptop.org", "time": "Sat Jan 08 22:48:03 2011 -0500" }, "message": "mmc: Aggressive clock gating framework\n\nThis patch modifies the MMC core code to optionally call the set_ios()\noperation on the driver with the clock frequency set to 0 (gate) after\na grace period of at least 8 MCLK cycles, then restore it (ungate)\nbefore any new request. This gives the driver the option to shut down\nthe MCI clock to the MMC/SD card when the clock frequency is 0, i.e.\nthe core has stated that the MCI clock does not need to be generated.\n\nIt is inspired by existing clock gating code found in the OMAP and\nAtmel drivers and brings this up to the host abstraction. Gating is\nperformed before and after any MMC request.\n\nThis patchset implements this for the MMCI/PL180 MMC/SD host controller,\nbut it should be simple to switch OMAP/Atmel over to using this instead.\n\nmmc_set_{gated,ungated}() add variable protection to the state holders\nfor the clock gating code. This is particularly important when ordinary\n.set_ios() calls would race with the .set_ios() call resulting from a\ndelayed gate operation.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nReviewed-by: Chris Ball \u003ccjb@laptop.org\u003e\nTested-by: Chris Ball \u003ccjb@laptop.org\u003e\nSigned-off-by: Chris Ball \u003ccjb@laptop.org\u003e\n" }, { "commit": "8bcee1832d23869c2cdb6886ae5210b0143256f0", "tree": "9fac190248ed9ed10fe4e6f7b1b4cda8eaef7ddd", "parents": [ "5ce2a2ddb5d75d5e2371e58011fc21351bf278cb", "1cf215a5b43950d1a304373037828158057ff9fc" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Dec 21 00:40:51 2010 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Dec 21 00:40:51 2010 +0900" }, "message": "Merge branch \u0027rmobile/urgent\u0027 into rmobile-latest\n\nConflicts:\n\tarch/arm/mach-shmobile/include/mach/entry-macro.S\n\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "54b384634f7083bcacf9a9ed2e6f4c3d0a246e49", "tree": "51a37b9fc454ff9e5fced781e433a23ccc3d11d7", "parents": [ "9f843706bb87837b823228467f4f83973fd110e9" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Mon Dec 06 00:12:45 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Wed Dec 08 16:24:28 2010 +0900" }, "message": "mmc, sh: Remove sh_mmcif_boot_slurp()\n\nAs the only caller of sh_mmcif_boot_do_read() is\nsh_mmcif_boot_slurp() the configuration portion of\nsh_mmcif_boot_slurp() can be merged into sh_mmcif_boot_do_read().\n\nOnce this is done sh_mmcif_boot_slurp() is only a call\nto sh_mmcif_boot_do_read() with platform specific information -\nthe offset that images are stored on MMC. So make the\nsh_mmcif_boot_do_read() call directly from platform code\nand remove sh_mmcif_boot_slurp() altogether.\n\nCc: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "9f843706bb87837b823228467f4f83973fd110e9", "tree": "8072b05668ce169120f74733f3a9cdda1e24ee80", "parents": [ "22efa0fee32d9e7f6f6fbc396a872b5708d86048" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Mon Dec 06 00:12:44 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Wed Dec 08 16:24:21 2010 +0900" }, "message": "mmc, sh: Move MMCIF_PROGRESS_* into sh_mmcif.h\n\nAllow MMCIF_PROGRESS_* to be shared.\n\nCc: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "d8e7943d821d8ee7f48ff38f6f7c509297c88402", "tree": "7c3990942d495fd6bdfcdf6e69fe37bda8e4ce33", "parents": [ "df73af86b6e737f357aae85e0b5e621516117780", "22efa0fee32d9e7f6f6fbc396a872b5708d86048" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Nov 30 14:42:55 2010 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Nov 30 14:42:55 2010 +0900" }, "message": "Merge branch \u0027common/mmcif\u0027 into rmobile/mmcif\n" }, { "commit": "22efa0fee32d9e7f6f6fbc396a872b5708d86048", "tree": "e5ed9af4fcb68b6c44f25e88a3e97fcb68c681c9", "parents": [ "1ae0affedce1d3e401991fbe7f2674753f0a7641" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Sat Nov 27 00:11:55 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Nov 29 12:54:55 2010 +0900" }, "message": "sh, mmc: Use defines when setting CE_CLK_CTRL\n\nThe 16-19th bits of CE_CLK_CTRL set the\nMMC clock frequency.\n\nCc: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nCc: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "1ae0affedce1d3e401991fbe7f2674753f0a7641", "tree": "0df282400a9e16d6a8ad131359c4794b7154de48", "parents": [ "7211a1bae6eac26539eb2d77a26fcd1bccef8137" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Fri Nov 26 23:02:58 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Nov 29 12:54:50 2010 +0900" }, "message": "mmc, sh: Correct value for reset\n\nThis resolves a regression that I introduced in\n\"mmc, sh: Move constants to sh_mmcif.h\". Having\nexamined the manual and tested the code on an AP4EVB board\nit seems that the correct sequence is.\n\n1) Write 1 to bit 31 and zeros to all other bits\n2) Write zero to all bits\n\nCc: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nCc: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "5c3b9bac28c62151f133a944fe14df5e153ae493", "tree": "f8159b142262aaa80406f2dbef744c012ffda113", "parents": [ "b127c6fb508f86542c3d5e460e1b99d2294360a6", "15ec44611904be0dcc97b84c29fbf964e5e2b36f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Nov 27 07:16:29 2010 +0900" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Nov 27 07:16:29 2010 +0900" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc:\n mmc: sdhci: 8-bit bus width changes\n mmc: sdio: fix runtime PM anomalies by introducing MMC_CAP_POWER_OFF_CARD\n mmc: sdio: fix nasty oops in mmc_sdio_detect\n mmc: omap4: hsmmc: Fix improper card detection while booting\n mmc: fix rmmod race for hosts using card-detection polling\n mmc: sdhci: Fix crash on boot with C0 stepping Moorestown platforms\n mmc: sdhci-esdhc-imx: enable QUIRK_NO_MULTIBLOCK only for i.MX25 and i.MX35\n mmc: sdhci-esdhc-imx: fix timeout on i.MX\u0027s sdhci\n mmc: sdhci: Properly enable SDIO IRQ wakeups\n mmc: ushc: Return proper error code for ushc_probe()\n mmc: Fix printing of card DDR type\n" }, { "commit": "a782d688e9c6f9ca9a7a9a28e8e2876969ddef53", "tree": "c8b13a19a1397bbbda255a59ce8a26518991d2e5", "parents": [ "e47bf32aa8de06ec72e18b4fbbd880caeedb0088" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Nov 24 10:05:22 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Thu Nov 25 16:26:46 2010 +0900" }, "message": "mmc: sh_mmcif: add DMA support\n\nThe MMCIF controller on sh-mobile platforms can use the DMA controller for data\ntransfers. Interface to the SH dmaengine driver to enable DMA. We also have to\nlower the maximum number of segments to match with the number od DMA\ndescriptors on SuperH, this doesn\u0027t significantly affect driver\u0027s PIO\nperformance.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" } ], "next": "ed919b0125b26dcc052e44836f66e7e1f5c49c7e" }