)]}' { "log": [ { "commit": "3cfef9524677a4ecb392d6fbffe6ebce6302f1d4", "tree": "88647d9dc50d634dee9cfeb7f354d620977a2f33", "parents": [ "982653009b883ef1529089e3e6f1ae2fee41cbe2", "68cc3990a545dc0da221b4844dd8b9c06623a6c5" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Oct 26 16:17:32 2011 +0200" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Oct 26 16:17:32 2011 +0200" }, "message": "Merge branch \u0027core-locking-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip\n\n* \u0027core-locking-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (27 commits)\n rtmutex: Add missing rcu_read_unlock() in debug_rt_mutex_print_deadlock()\n lockdep: Comment all warnings\n lib: atomic64: Change the type of local lock to raw_spinlock_t\n locking, lib/atomic64: Annotate atomic64_lock::lock as raw\n locking, x86, iommu: Annotate qi-\u003eq_lock as raw\n locking, x86, iommu: Annotate irq_2_ir_lock as raw\n locking, x86, iommu: Annotate iommu-\u003eregister_lock as raw\n locking, dma, ipu: Annotate bank_lock as raw\n locking, ARM: Annotate low level hw locks as raw\n locking, drivers/dca: Annotate dca_lock as raw\n locking, powerpc: Annotate uic-\u003elock as raw\n locking, x86: mce: Annotate cmci_discover_lock as raw\n locking, ACPI: Annotate c3_lock as raw\n locking, oprofile: Annotate oprofilefs lock as raw\n locking, video: Annotate vga console lock as raw\n locking, latencytop: Annotate latency_lock as raw\n locking, timer_stats: Annotate table_lock as raw\n locking, rwsem: Annotate inner lock as raw\n locking, semaphores: Annotate inner lock as raw\n locking, sched: Annotate thread_group_cputimer as raw\n ...\n\nFix up conflicts in kernel/posix-cpu-timers.c manually: making\ncputimer-\u003ecputime a raw lock conflicted with the ABBA fix in commit\nbcd5cff7216f (\"cputimer: Cure lock inversion\").\n" }, { "commit": "d3f138106b4b40640dc667f0222fd9f137387b32", "tree": "2c5d51deff32ec0999493bbb73cb18a7e4a455c3", "parents": [ "c39d77ffa28c6e72702193df4fa53928c1b6f3e6" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Tue Aug 23 17:05:25 2011 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Wed Sep 21 10:22:03 2011 +0200" }, "message": "iommu: Rename the DMAR and INTR_REMAP config options\n\nChange the CONFIG_DMAR to CONFIG_INTEL_IOMMU to be consistent\nwith the other IOMMU options.\n\nRename the CONFIG_INTR_REMAP to CONFIG_IRQ_REMAP to match the\nirq subsystem name.\n\nAnd define the CONFIG_DMAR_TABLE for the common ACPI DMAR\nroutines shared by both CONFIG_INTEL_IOMMU and CONFIG_IRQ_REMAP.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: yinghai@kernel.org\nCc: youquan.song@intel.com\nCc: joerg.roedel@amd.com\nCc: tony.luck@intel.com\nCc: dwmw2@infradead.org\nLink: http://lkml.kernel.org/r/20110824001456.558630224@sbsiddha-desk.sc.intel.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "3b8f40481513a7b6123def5a02db4cff96ae2198", "tree": "b183c44200f644f5f84484aa7603924815b7adbb", "parents": [ "96f8e98bfeba3efa82eca85343bc058f6eced888" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Jul 19 17:02:07 2011 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Sep 13 11:12:20 2011 +0200" }, "message": "locking, x86, iommu: Annotate qi-\u003eq_lock as raw\n\nThe qi-\u003eq_lock lock can be taken in atomic context and therefore\ncannot be preempted on -rt - annotate it.\n\nIn mainline this change documents the low level nature of\nthe lock - otherwise there\u0027s no functional difference. Lockdep\nand Sparse checking will work as usual.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "1f5b3c3fd2d73d6b30e9ef6dcbf131a791d5cbbd", "tree": "1d24f2510bd8c57f5e026bf9a7ff93999ed39577", "parents": [ "289b4e7a48d91fbef7af819020d826ad9f49f568" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Jul 19 16:19:51 2011 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Sep 13 11:12:17 2011 +0200" }, "message": "locking, x86, iommu: Annotate iommu-\u003eregister_lock as raw\n\nThe iommu-\u003eregister_lock can be taken in atomic context and therefore\nmust not be preempted on -rt - annotate it.\n\nIn mainline this change documents the low level nature of\nthe lock - otherwise there\u0027s no functional difference. Lockdep\nand Sparse checking will work as usual.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "ee34b32d8c2950f66038c8975747ef9aec855289", "tree": "572eef281a2b41b3e5ca5d6889752f5e7736526b", "parents": [ "e0fc7e0b4b5e69616f10a894ab9afff3c64be74e" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Fri Oct 02 11:01:21 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Oct 05 07:55:22 2009 +0100" }, "message": "dmar: support for parsing Remapping Hardware Static Affinity structure\n\nAdd support for parsing Remapping Hardware Static Affinity (RHSA) structure.\nThis enables identifying the association between remapping hardware units and\nthe corresponding proximity domain. This enables to allocate transalation\nstructures closer to the remapping hardware unit.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "074835f0143b83845af5044af2739c52c9f53808", "tree": "f573860163fda805b97656f7bc400f148179e1a9", "parents": [ "e936d0773df172ec8600777fdd72bbc1f75f22ad" ], "author": { "name": "Youquan Song", "email": "youquan.song@intel.com", "time": "Wed Sep 09 12:05:39 2009 -0400" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Sep 11 16:40:10 2009 +0100" }, "message": "intel-iommu: Fix kernel hang if interrupt remapping disabled in BIOS\n\nBIOS clear DMAR table INTR_REMAP flag to disable interrupt remapping. Current\nkernel only check interrupt remapping(IR) flag in DRHD\u0027s extended capability\nregister to decide interrupt remapping support or not. But IR flag will not\nchange when BIOS disable/enable interrupt remapping.\n\nWhen user disable interrupt remapping in BIOS or BIOS often defaultly disable\ninterrupt remapping feature when BIOS is not mature.Though BIOS disable\ninterrupt remapping but intr_remapping_supported function will always report\nto OS support interrupt remapping if VT-d2 chipset populated. On this\ncases, kernel will continue enable interrupt remapping and result kernel panic.\nThis bug exist on almost all platforms with interrupt remapping support.\n\nThis patch add DMAR table INTR_REMAP flag check before enable interrupt\nremapping.\n\nSigned-off-by: Youquan Song \u003cyouquan.song@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "93a23a7271dfb811b3adb72779054c3a24433112", "tree": "1a5d92b6816bd3bd7f2ac6c342d9b98ec202ed40", "parents": [ "9dd2fe89062c90a964d122b8be5615d6f2203bbe" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon May 18 13:51:37 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon May 18 14:46:26 2009 +0100" }, "message": "VT-d: support the device IOTLB\n\nEnable the device IOTLB (i.e. ATS) for both the bare metal and KVM\nenvironments.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "6ba6c3a4cacfd68bf970e3e04e2ff0d66fa0f695", "tree": "02afc5c010ec841f7e6ad9fc68e8a76f7f18909a", "parents": [ "aa5d2b515b6fca5f8a56eac84f7fa0a68c1ce9b7" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon May 18 13:51:35 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon May 18 14:45:13 2009 +0100" }, "message": "VT-d: add device IOTLB invalidation support\n\nSupport device IOTLB invalidation to flush the translation cached\nin the Endpoint.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "aa5d2b515b6fca5f8a56eac84f7fa0a68c1ce9b7", "tree": "c98753254dfe2f3e54a4c38c9191ab5f4afb4c39", "parents": [ "e277d2fc79d6abb86fafadb58dca0b9c498a9aa7" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon May 18 13:51:34 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon May 18 14:45:09 2009 +0100" }, "message": "VT-d: parse ATSR in DMA Remapping Reporting Structure\n\nParse the Root Port ATS Capability Reporting Structure in the DMA\nRemapping Reporting Structure ACPI table.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1f0ef2aa18802a8ce7eb5a5164aaaf4d59073801", "tree": "953fd29f1853b0773e9dcd72ab1ecb3231c6b457", "parents": [ "4c25a2c1b90bf785fc2e2f0f0c74a80b3e070d39" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun May 10 19:58:49 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun May 10 19:58:49 2009 +0100" }, "message": "intel-iommu: Clean up handling of \"caching mode\" vs. IOTLB flushing.\n\nAs we just did for context cache flushing, clean up the logic around\nwhether we need to flush the iotlb or just the write-buffer, depending\non caching mode.\n\nFix the same bug in qi_flush_iotlb() that qi_flush_context() had -- it\nisn\u0027t supposed to be returning an error; it\u0027s supposed to be returning a\nflag which triggers a write-buffer flush.\n\nRemove some superfluous conditional write-buffer flushes which could\nnever have happened because they weren\u0027t for non-present-to-present\nmapping changes anyway.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "4c25a2c1b90bf785fc2e2f0f0c74a80b3e070d39", "tree": "2784fbbf4d6782db300b92870d2bf6111ef26627", "parents": [ "fa3b6dcd5298db2e7b63c17795c9e5570d3df8d9" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun May 10 17:16:06 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun May 10 19:49:52 2009 +0100" }, "message": "intel-iommu: Clean up handling of \"caching mode\" vs. context flushing.\n\nIt really doesn\u0027t make a lot of sense to have some of the logic to\nhandle caching vs. non-caching mode duplicated in qi_flush_context() and\n__iommu_flush_context(), while the return value indicates whether the\ncaller should take other action which depends on the same thing.\n\nEspecially since qi_flush_context() thought it was returning something\nentirely different anyway.\n\nThis patch makes qi_flush_context() and __iommu_flush_context() both\nreturn void, removes the \u0027non_present_entry_flush\u0027 argument and makes\nthe only call site which _set_ that argument to 1 do the right thing.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "4ed0d3e6c64cfd9ba4ceb2099b10d1cf8ece4320", "tree": "950bacfaf57040aafbcc2ea9b52eb171d35c23bd", "parents": [ "091069740304c979f957ceacec39c461d0192158" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Fri Apr 24 17:30:20 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Apr 29 06:54:34 2009 +0100" }, "message": "Intel IOMMU Pass Through Support\n\nThe patch adds kernel parameter intel_iommu\u003dpt to set up pass through\nmode in context mapping entry. This disables DMAR in linux kernel; but\nKVM still runs on VT-d and interrupt remapping still works.\n\nIn this mode, kernel uses swiotlb for DMA API functions but other VT-d\nfunctionalities are enabled for KVM. KVM always uses multi level\ntranslation page table in VT-d. By default, pass though mode is disabled\nin kernel.\n\nThis is useful when people don\u0027t want to enable VT-d DMAR in kernel but\nstill want to use KVM and interrupt remapping for reasons like DMAR\nperformance concern or debug purpose.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nAcked-by: Weidong Han \u003cweidong@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "161fde083f3403e7aa178dc944bf43c339e18491", "tree": "79473edadf7aad496c9158400ea7bb4f8336516e", "parents": [ "b24696bc55f66fecc30715e003f10fc2555a9271" ], "author": { "name": "Han, Weidong", "email": "weidong.han@intel.com", "time": "Fri Apr 03 17:15:47 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Apr 03 21:46:01 2009 +0100" }, "message": "intel-iommu: set compatibility format interrupt\n\nWhen extended interrupt mode (x2apic mode) is not supported in a\nsystem, it must set compatibility format interrupt to bypass\ninterrupt remapping, otherwise compatibility format interrupts\nwill be blocked.\n\nThis will be used when interrupt remapping is enabled while x2apic\nis not supported.\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "f59c7b69bcba31cd355ababe067202b9895d6102", "tree": "4f06ceb6ab9a135acd9b316c806aaa99c097b373", "parents": [ "8f912ba4d7cdaf7d31cf39fe5a9b7732308a256d" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Fri Mar 27 14:22:42 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Apr 03 21:45:54 2009 +0100" }, "message": "Intel IOMMU Suspend/Resume Support - DMAR\n\nThis patch implements the suspend and resume feature for Intel IOMMU\nDMAR. It hooks to kernel suspend and resume interface. When suspend happens, it\nsaves necessary hardware registers. When resume happens, it restores the\nregisters and restarts IOMMU by enabling translation, setting up root entry, and\nre-enabling queued invalidation.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "ca1ee219c070eab755712d50638bbcd1f8630fc1", "tree": "c0c252a9095830aadc5dc9ffdd16d9167dd605c9", "parents": [ "3cc50ac0dbda5100684e570247782330155d35e0", "afeeb7cebbd223ffee303fd8de4ba97458b13581" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 10:36:57 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 10:36:57 2009 -0700" }, "message": "Merge git://git.infradead.org/iommu-2.6\n\n* git://git.infradead.org/iommu-2.6:\n intel-iommu: Fix address wrap on 32-bit kernel.\n intel-iommu: Enable DMAR on 32-bit kernel.\n intel-iommu: fix PCI device detach from virtual machine\n intel-iommu: VT-d page table to support snooping control bit\n iommu: Add domain_has_cap iommu_ops\n intel-iommu: Snooping control support\n\nFixed trivial conflicts in arch/x86/Kconfig and drivers/pci/intel-iommu.c\n" }, { "commit": "712b0006bf3a9ed0b14a56c3291975e582127766", "tree": "aff33e947673137ae21734321e1f036600297223", "parents": [ "e1c502482853f84606928f5a2f2eb6da1993cda1", "b0d44c0dbbd52effb731b1c0af9afd56215c48de" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 30 13:41:00 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 30 13:41:00 2009 -0700" }, "message": "Merge branch \u0027iommu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027iommu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (60 commits)\n dma-debug: make memory range checks more consistent\n dma-debug: warn of unmapping an invalid dma address\n dma-debug: fix dma_debug_add_bus() definition for !CONFIG_DMA_API_DEBUG\n dma-debug/x86: register pci bus for dma-debug leak detection\n dma-debug: add a check dma memory leaks\n dma-debug: add checks for kernel text and rodata\n dma-debug: print stacktrace of mapping path on unmap error\n dma-debug: Documentation update\n dma-debug: x86 architecture bindings\n dma-debug: add function to dump dma mappings\n dma-debug: add checks for sync_single_sg_*\n dma-debug: add checks for sync_single_range_*\n dma-debug: add checks for sync_single_*\n dma-debug: add checking for [alloc|free]_coherent\n dma-debug: add add checking for map/unmap_sg\n dma-debug: add checking for map/unmap_page/single\n dma-debug: add core checking functions\n dma-debug: add debugfs interface\n dma-debug: add kernel command line parameters\n dma-debug: add initialization code\n ...\n\nFix trivial conflicts due to whitespace changes in arch/x86/kernel/pci-nommu.c\n" }, { "commit": "58c610bd1a3f50820e45a7c09ec0e44d2cda15dd", "tree": "696539e1e17fd7600222865fa331e9144737a58b", "parents": [ "a1e4ee22863d41a6fbb24310d7951836cb6dafe7" ], "author": { "name": "Sheng Yang", "email": "sheng@linux.intel.com", "time": "Wed Mar 18 15:33:05 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Mar 24 09:42:43 2009 +0000" }, "message": "intel-iommu: Snooping control support\n\nSnooping control enabled IOMMU to guarantee DMA cache coherency and thus reduce\nsoftware effort (VMM) in maintaining effective memory type.\n\nSigned-off-by: Sheng Yang \u003csheng@linux.intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "eba67e5da6e971993b2899d2cdf459ce77d3dbc5", "tree": "1776415c0ed65e6ad309b6790110941fadef243f", "parents": [ "9d783ba042771284fb4ee5013c3d94220755ae7f" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Mon Mar 16 17:04:56 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@linux.intel.com", "time": "Tue Mar 17 15:39:20 2009 -0700" }, "message": "x86, dmar: routines for disabling queued invalidation and intr remapping\n\nImpact: new interfaces (not yet used)\n\nRoutines for disabling queued invalidation and interrupt remapping.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@linux.intel.com\u003e\n" }, { "commit": "9d783ba042771284fb4ee5013c3d94220755ae7f", "tree": "102ec9f89d363589108ae35e4b38c12fc6e2765c", "parents": [ "0ac2491f57af5644f88383d28809760902d6f4d7" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Mon Mar 16 17:04:55 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@linux.intel.com", "time": "Tue Mar 17 15:38:59 2009 -0700" }, "message": "x86, x2apic: enable fault handling for intr-remapping\n\nImpact: interface augmentation (not yet used)\n\nEnable fault handling flow for intr-remapping aswell. Fault handling\ncode now shared by both dma-remapping and intr-remapping.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@linux.intel.com\u003e\n" }, { "commit": "7df4edb07cf54a4868b9a750424c0d2aa68f8d66", "tree": "0ad0ad3f3dcb6f9edf26dde42ba625053dddf54f", "parents": [ "0d688da5505d77bcef2441e0a22d8cc26459702d", "559595a985e106d2fa9f0c79b7f5805453fed593" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Thu Mar 05 12:47:28 2009 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Thu Mar 05 12:47:28 2009 +0100" }, "message": "Merge branch \u0027linus\u0027 into core/iommu\n" }, { "commit": "704126ad81b8cb7d3d70adb9ecb143f4d3fb38af", "tree": "e73c4d595799661757b7505cd67833addef0635e", "parents": [ "43f7392ba9e2585bf34f21399b1ed78692b5d437" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sun Jan 04 16:28:52 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Feb 09 11:03:17 2009 +0000" }, "message": "VT-d: handle Invalidation Queue Error to avoid system hang\n\nWhen hardware detects any error with a descriptor from the invalidation\nqueue, it stops fetching new descriptors from the queue until software\nclears the Invalidation Queue Error bit in the Fault Status register.\nFollowing fix handles the IQE so the kernel won\u0027t be trapped in an\ninfinite loop.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "d7ab5c46ae2743079a40bb4060e510418c0842b4", "tree": "da51ca0ad2c50f09ca638bb7bff18ea03b31b106", "parents": [ "dfb805e831cc5306b14eacd64e0b36d0d973ee0d" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Jan 28 21:53:18 2009 +0900" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Thu Jan 29 14:39:29 2009 +0100" }, "message": "intel-iommu: make dma mapping functions static\n\nThe dma ops unification enables X86 and IA64 to share intel_dma_ops so\nwe can make dma mapping functions static. This also remove unused\nintel_map_single().\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "160c1d8e40866edfeae7d68816b7005d70acf391", "tree": "37dd78b2ea28a3953a46d401bd9657005eb444d7", "parents": [ "f0402a262e1a4c03fc66b83659823bdcaac3c41a" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Mon Jan 05 23:59:02 2009 +0900" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Jan 06 14:06:57 2009 +0100" }, "message": "x86, ia64: convert to use generic dma_map_ops struct\n\nThis converts X86 and IA64 to use include/linux/dma-mapping.h.\n\nIt\u0027s a bit large but pretty boring. The major change for X86 is\nconverting \u0027int dir\u0027 to \u0027enum dma_data_direction dir\u0027 in DMA mapping\noperations. The major changes for IA64 is using map_page and\nunmap_page instead of map_single and unmap_single.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nAcked-by: Tony Luck \u003ctony.luck@intel.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "e4754c96cf8b82a754dc5ba791d6c0bf1fbe8e8e", "tree": "a5015d1874992e883e2d8f6ab46caead6503338e", "parents": [ "a8bcbb0de4a52f07fef7412ddc877348311ebf2a" ], "author": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Wed Dec 03 15:26:42 2008 +0100" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 14:11:08 2009 +0100" }, "message": "VT-d: remove now unused intel_iommu_found function\n\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "d14d65777c2491dd5baf1e17f444b8f653f3cbb1", "tree": "d2067ca36c019d6f7b7b25886d514ce23b68ea07", "parents": [ "dde57a210dcdce85e2813bab8f88687761d9f6a6" ], "author": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Wed Dec 03 15:06:57 2008 +0100" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 14:11:08 2009 +0100" }, "message": "VT-d: adapt domain iova_to_phys function for IOMMU API\n\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "dde57a210dcdce85e2813bab8f88687761d9f6a6", "tree": "cac9c8c6cc41361dad1c4d1c71f5926e670185fc", "parents": [ "4c5478c94eb29e6101f1f13175f7455bc8b5d953" ], "author": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Wed Dec 03 15:04:09 2008 +0100" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 14:11:08 2009 +0100" }, "message": "VT-d: adapt domain map and unmap functions for IOMMU API\n\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "4c5478c94eb29e6101f1f13175f7455bc8b5d953", "tree": "6235e9d9a22230c837f420f4f8d655817be8efa7", "parents": [ "5d450806eb0e569c5846a5825e7f535980b0da32" ], "author": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Wed Dec 03 14:58:24 2008 +0100" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 14:11:08 2009 +0100" }, "message": "VT-d: adapt device attach and detach functions for IOMMU API\n\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "5d450806eb0e569c5846a5825e7f535980b0da32", "tree": "6b110597307b7e8443e200bd5432ab0cd220d0a2", "parents": [ "19de40a8472fa64693eab844911eec277d489f6c" ], "author": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Wed Dec 03 14:52:32 2008 +0100" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 14:11:07 2009 +0100" }, "message": "VT-d: adapt domain init and destroy functions for IOMMU API\n\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "faa3d6f5ffe7bf60ebfd0d36513fbcda0eb0ea1a", "tree": "4992e52cff96da38bedfb7805c18ac97c9ae9c01", "parents": [ "ea6606b02fc3192f2edab2db669fa0b9756b4e67" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Mon Dec 08 23:09:29 2008 +0800" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 14:02:18 2009 +0100" }, "message": "Change intel iommu APIs of virtual machine domain\n\nThese APIs are used by KVM to use VT-d\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "1b5736839ae13dadc5947940144f95dd0f4a4a8c", "tree": "2b6ce6b68850d905e4ce5d38b6872b82f6328208", "parents": [ "8c11e798eee2ce4475134eaf61302b28ea4f205d" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Mon Dec 08 15:34:06 2008 +0800" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 14:02:18 2009 +0100" }, "message": "calculate agaw for each iommu\n\n\"SAGAW\" capability may be different across iommus. Use a default agaw, but if default agaw is not supported in some iommus, choose a less supported agaw.\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n" }, { "commit": "015ab17dc2e9de805c26e74f498b12ee5e8de07e", "tree": "9f86070afa1bf44b9c6622c47c6340834ef046af", "parents": [ "6680598b44ed3c0052d155522eb21fc5a00de5f3" ], "author": { "name": "Mark McLoughlin", "email": "markmc@redhat.com", "time": "Thu Nov 20 14:04:20 2008 +0000" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 11:57:34 2009 +0100" }, "message": "intel-iommu: remove some unused struct intel_iommu fields\n\nThe seg, saved_msg and sysdev fields appear to be unused since\nbefore the code was first merged.\n\nlinux/msi.h is not needed in linux/intel-iommu.h anymore since\nthere is no longer a reference to struct msi_msg. The MSI code\nin drivers/pci/intel-iommu.c still has linux/msi.h included\nvia linux/dmar.h.\n\nlinux/sysdev.h isn\u0027t needed because there is no reference to\nstruct sys_device.\n\nSigned-off-by: Mark McLoughlin \u003cmarkmc@redhat.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "5b6985ce8ec7127b4d60ad450b64ca8b82748a3b", "tree": "f1d5a27601df04a3481690a1a2f90fc688034aff", "parents": [ "cacd4213d8ffed83676f38d5d8e93c673e0f1af7" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Thu Oct 16 18:02:32 2008 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Oct 18 14:29:15 2008 +0100" }, "message": "intel-iommu: IA64 support\n\nThe current Intel IOMMU code assumes that both host page size and Intel\nIOMMU page size are 4KiB. The first patch supports variable page size.\nThis provides support for IA64 which has multiple page sizes.\n\nThis patch also adds some other code hooks for IA64 platform including\nDMAR_OPERATION_TIMEOUT definition.\n\n[dwmw2: some cleanup]\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "a77b67d4023770805141014b8fa9eb5467457817", "tree": "661dda1d33b8892f1e1fa2508565a288712592b9", "parents": [ "3481f21097cb560392c411377893b5109fbde557" ], "author": { "name": "Youquan Song", "email": "youquan.song@intel.com", "time": "Thu Oct 16 16:31:56 2008 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Oct 17 08:05:01 2008 +0100" }, "message": "dmar: Use queued invalidation interface for IOTLB and context invalidation\n\nIf queued invalidation interface is available and enabled, queued invalidation\ninterface will be used instead of the register based interface.\n\nAccording to Vt-d2 specification, when queued invalidation is enabled,\ninvalidation command submit works only through invalidation queue and not\nthrough the command registers interface.\n\nSigned-off-by: Youquan Song \u003cyouquan.song@intel.com\u003e\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "3481f21097cb560392c411377893b5109fbde557", "tree": "5bc3165cb45a0d4bc04ce3d945b5ec8483939ed7", "parents": [ "f05810c9962bba3e809f07619bda1bfdebbfbfb9" ], "author": { "name": "Youquan Song", "email": "youquan.song@intel.com", "time": "Thu Oct 16 16:31:55 2008 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Oct 17 08:03:14 2008 +0100" }, "message": "dmar: context cache and IOTLB invalidation using queued invalidation\n\nImplement context cache invalidate and IOTLB invalidation using\nqueued invalidation interface. This interface will be used by\nDMA remapping, when queued invalidation is supported.\n\nSigned-off-by: Youquan Song \u003cyouquan.song@intel.com\u003e\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "387179464257921eb9aa3d15cc3ff194f6945a7c", "tree": "a7f06903688df8a1d3231faf1ab68bf80e032ea6", "parents": [ "aa3a816b6d0bd59e1a9c548cc7d2dd829f26534f" ], "author": { "name": "Kay, Allen M", "email": "allen.m.kay@intel.com", "time": "Tue Sep 09 18:37:29 2008 +0300" }, "committer": { "name": "Avi Kivity", "email": "avi@redhat.com", "time": "Wed Oct 15 14:24:08 2008 +0200" }, "message": "VT-d: Changes to support KVM\n\nThis patch extends the VT-d driver to support KVM\n\n[Ben: fixed memory pinning]\n[avi: move dma_remapping.h as well]\n\nSigned-off-by: Kay, Allen M \u003callen.m.kay@intel.com\u003e\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: Ben-Ami Yassour \u003cbenami@il.ibm.com\u003e\nSigned-off-by: Amit Shah \u003camit.shah@qumranet.com\u003e\nAcked-by: Mark Gross \u003cmgross@linux.intel.com\u003e\nSigned-off-by: Avi Kivity \u003cavi@qumranet.com\u003e\n" }, { "commit": "b6fcb33ad6c05f152a672f7c96c1fab006527b80", "tree": "9926a4914b7d929f31794315dc21768f38c3628e", "parents": [ "2ae21010694e56461a63bfc80e960090ce0a5ed9" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:44 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:54 2008 +0200" }, "message": "x64, x2apic/intr-remap: routines managing Interrupt remapping table entries.\n\nRoutines handling the management of interrupt remapping table entries.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "2ae21010694e56461a63bfc80e960090ce0a5ed9", "tree": "d4ecdb710c4361df473b063eda9e1426fcf5c309", "parents": [ "fe962e90cb17a8426e144dee970e77ed789d98ee" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:43 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:53 2008 +0200" }, "message": "x64, x2apic/intr-remap: Interrupt remapping infrastructure\n\nInterrupt remapping (part of Intel Virtualization Tech for directed I/O)\ninfrastructure.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "fe962e90cb17a8426e144dee970e77ed789d98ee", "tree": "c7b3343df9bf58e047333758a89c78f6615fb97b", "parents": [ "cf1337f0447e5be8e66daa944f0ea3bcac2b6179" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:42 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:52 2008 +0200" }, "message": "x64, x2apic/intr-remap: Queued invalidation infrastructure (part of VT-d)\n\nQueued invalidation (part of Intel Virtualization Technology for\nDirected I/O architecture) infrastructure.\n\nThis will be used for invalidating the interrupt entry cache in the\ncase of Interrupt-remapping and IOTLB invalidation in the case\nof DMA-remapping.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "cf1337f0447e5be8e66daa944f0ea3bcac2b6179", "tree": "6e5120ba9a75fee603a660b4324c147b9e455c79", "parents": [ "ad3ad3f6a2caebf56869b83b69e23eb9fa5e0ab6" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:41 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:51 2008 +0200" }, "message": "x64, x2apic/intr-remap: move IOMMU_WAIT_OP() macro to intel-iommu.h\n\nmove IOMMU_WAIT_OP() macro to header file.\n\nThis will be used by both DMA-remapping and Intr-remapping.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "ad3ad3f6a2caebf56869b83b69e23eb9fa5e0ab6", "tree": "7bc99dde6a6313eb43783086a33f6eebc1da1907", "parents": [ "2d6b5f85bb4ca919d8ab0f30311309b53fb93bc3" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:40 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:50 2008 +0200" }, "message": "x64, x2apic/intr-remap: parse ioapic scope under vt-d structures\n\nParse the vt-d device scope structures to find the mapping between IO-APICs\nand the interrupt remapping hardware units.\n\nThis will be used later for enabling Interrupt-remapping for IOAPIC devices.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "1886e8a90a580f3ad343f2065c84c1b9e1dac9ef", "tree": "1f0a6b536a1bb7b24585973e70ad8e1a9a076f09", "parents": [ "c42d9f32443397aed2d37d37df161392e6a5862f" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:37 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:48 2008 +0200" }, "message": "x64, x2apic/intr-remap: code re-structuring, to be used by both DMA and Interrupt remapping\n\nAllocate the iommu during the parse of DMA remapping hardware\ndefinition structures. And also, introduce routines for device\nscope initialization which will be explicitly called during\ndma-remapping initialization.\n\nThese will be used for enabling interrupt remapping separately from the\nexisting DMA-remapping enabling sequence.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "c42d9f32443397aed2d37d37df161392e6a5862f", "tree": "564126849bb2e31d2cfb719c3b03457a597733d2", "parents": [ "e61d98d8dad0048619bb138b0ff996422ffae53b" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:36 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:47 2008 +0200" }, "message": "x64, x2apic/intr-remap: fix the need for sequential array allocation of iommus\n\nClean up the intel-iommu code related to deferred iommu flush logic. There is\nno need to allocate all the iommu\u0027s as a sequential array.\n\nThis will be used later in the interrupt-remapping patch series to\nallocate iommu much early and individually for each device remapping\nhardware unit.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "e61d98d8dad0048619bb138b0ff996422ffae53b", "tree": "f31fe1610a082e0e12605db879ff56546ad971e5", "parents": [ "1ba89386db0a3f39590b90b5dd20d7149ae52de0" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:35 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:46 2008 +0200" }, "message": "x64, x2apic/intr-remap: Intel vt-d, IOMMU code reorganization\n\ncode reorganization of the generic Intel vt-d parsing related routines and linux\niommu routines specific to Intel vt-d.\n\ndrivers/pci/dmar.c\tnow contains the generic vt-d parsing related routines\ndrivers/pci/intel_iommu.c contains the iommu routines specific to vt-d\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "98bcef56cadb4da138e2c1a2a0790f372382b236", "tree": "a33c72c26d6075e3bab1c27791ccbabac7ebd0af", "parents": [ "eaeb16883bd6aa2d6b6b61b825c0d2b0dc793f60" ], "author": { "name": "mark gross", "email": "mgross@linux.intel.com", "time": "Sat Feb 23 15:23:35 2008 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Sat Feb 23 17:12:14 2008 -0800" }, "message": "copyright owner and author clean up for intel iommu and related files\n\nThe following is a clean up and correction of the copyright holding\nentities for the files associated with the intel iommu code.\n\nSigned-off-by: \u003cmgross@linux.intel.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "f8bab73515ca5b392680bb033dceeb37b8463e95", "tree": "c450e793839868c23209e6fcbfb189975d9d4db6", "parents": [ "2d3a4e3666325a9709cc8ea2e88151394e8f20fc" ], "author": { "name": "mark gross", "email": "mgross@linux.intel.com", "time": "Fri Feb 08 04:18:38 2008 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Fri Feb 08 09:22:24 2008 -0800" }, "message": "intel-iommu: PMEN support\n\nAdd support for protected memory enable bits by clearing them if they are\nset at startup time. Some future boot loaders or firmware could have this\nbit set after it loads the kernel, and it needs to be cleared if DMA\u0027s are\ngoing to happen effectively.\n\nSigned-off-by: mark gross \u003cmgross@intel.com\u003e\nAcked-by: Muli Ben-Yehuda \u003cmuli@il.ibm.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "f661197e0a95ec7305e1e790d95b72a74a1c4a0f", "tree": "a6916d877a3d9db9bc658758bd347d4f436f6d59", "parents": [ "b1ed88b47f5e18c6efb8041275c16eeead5377df" ], "author": { "name": "David Miller", "email": "davem@davemloft.net", "time": "Wed Feb 06 01:36:23 2008 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Wed Feb 06 10:41:01 2008 -0800" }, "message": "Genericizing iova.[ch]\n\nI would like to potentially move the sparc64 IOMMU code over to using\nthe nice new drivers/pci/iova.[ch] code for free area management..\n\nIn order to do that we have to detach the IOMMU page size assumptions\nwhich only really need to exist in the intel-iommu.[ch] code.\n\nThis patch attempts to implement that.\n\n[akpm@linux-foundation.org: build fix]\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Anil S Keshavamurthy \u003canil.s.keshavamurthy@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "4fe05bbcd53160616774b6f5619b8a55bcfa1c57", "tree": "f6b03c6b5013ddb3ab13f7521d593d6bed5b1886", "parents": [ "b4a08a10b12c145da67cc788849bf7cc6efaa210" ], "author": { "name": "Al Viro", "email": "viro@ftp.linux.org.uk", "time": "Mon Oct 29 04:51:16 2007 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Oct 29 07:41:32 2007 -0700" }, "message": "intel-iommu fixes\n\n - off by one in dmar_get_fault_reason() (maximal index in array is\n ARRAY_SIZE()-1, not ARRAY_SIZE())\n - NULL noise removal\n - __iomem annotation fix\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "e820482cd2621dba60e403af1c54502daa54b220", "tree": "3498401c7154e14008ab80b2f0cbca539ce7ffbc", "parents": [ "3460a6d9cef9ac2aa997da7eff7ff1c8291b361c" ], "author": { "name": "Keshavamurthy, Anil S", "email": "anil.s.keshavamurthy@intel.com", "time": "Sun Oct 21 16:41:55 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Oct 22 08:13:19 2007 -0700" }, "message": "Intel IOMMU: Iommu Gfx workaround\n\nWhen we fix all the opensource gfx drivers to use the DMA api\u0027s, at that time\nwe can yank this config options out.\n\n[jengelh@computergmbh.de: Kconfig fixes]\nSigned-off-by: Anil S Keshavamurthy \u003canil.s.keshavamurthy@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Muli Ben-Yehuda \u003cmuli@il.ibm.com\u003e\nCc: \"Siddha, Suresh B\" \u003csuresh.b.siddha@intel.com\u003e\nCc: Arjan van de Ven \u003carjan@infradead.org\u003e\nCc: Ashok Raj \u003cashok.raj@intel.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Jan Engelhardt \u003cjengelh@gmx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "ba39592764ed20cee09aae5352e603a27bf56b0d", "tree": "efe7ec88bbd4d6b08b639830352c68411a7ef7fb", "parents": [ "f8de50eb6b085572ea773f26e066835ea3d3028b" ], "author": { "name": "Keshavamurthy, Anil S", "email": "anil.s.keshavamurthy@intel.com", "time": "Sun Oct 21 16:41:49 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Oct 22 08:13:18 2007 -0700" }, "message": "Intel IOMMU: Intel IOMMU driver\n\nActual intel IOMMU driver. Hardware spec can be found at:\nhttp://www.intel.com/technology/virtualization\n\nThis driver sets X86_64 \u0027dma_ops\u0027, so hook into standard DMA APIs. In this\nway, PCI driver will get virtual DMA address. This change is transparent to\nPCI drivers.\n\n[akpm@linux-foundation.org: remove unneeded cast]\n[akpm@linux-foundation.org: build fix]\n[bunk@stusta.de: fix duplicate CONFIG_DMAR Makefile line]\nSigned-off-by: Anil S Keshavamurthy \u003canil.s.keshavamurthy@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Muli Ben-Yehuda \u003cmuli@il.ibm.com\u003e\nCc: \"Siddha, Suresh B\" \u003csuresh.b.siddha@intel.com\u003e\nCc: Arjan van de Ven \u003carjan@infradead.org\u003e\nCc: Ashok Raj \u003cashok.raj@intel.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@stusta.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" } ] }