)]}' { "log": [ { "commit": "ebc82efa1cd64efba0f41455460411b852b5b89c", "tree": "7c63869c109c33dc4b4a5f95a46b24c688238117", "parents": [ "13802005d8f2db244ec1f5d7f6923de8f7a463db" ], "author": { "name": "Nicolas Royer", "email": "nicolas@eukrea.com", "time": "Sun Jul 01 19:19:46 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jul 11 11:08:28 2012 +0800" }, "message": "crypto: atmel - add Atmel SHA1/SHA256 driver\n\nSigned-off-by: Nicolas Royer \u003cnicolas@eukrea.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nAcked-by: Eric Bénard \u003ceric@eukrea.com\u003e\nTested-by: Eric Bénard \u003ceric@eukrea.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "13802005d8f2db244ec1f5d7f6923de8f7a463db", "tree": "05126a6de45d44d63df4ba7451695426a8c1e901", "parents": [ "bd3c7b5c2aba0d806285700848f588ca482094d8" ], "author": { "name": "Nicolas Royer", "email": "nicolas@eukrea.com", "time": "Sun Jul 01 19:19:45 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jul 11 11:08:14 2012 +0800" }, "message": "crypto: atmel - add Atmel DES/TDES driver\n\nSigned-off-by: Nicolas Royer \u003cnicolas@eukrea.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nAcked-by: Eric Bénard \u003ceric@eukrea.com\u003e\nTested-by: Eric Bénard \u003ceric@eukrea.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "bd3c7b5c2aba0d806285700848f588ca482094d8", "tree": "23cc5632224f085f37ce8af47997c3401c205a26", "parents": [ "815e972110052e8da68b5b5298ca2cd69cb7c3c0" ], "author": { "name": "Nicolas Royer", "email": "nicolas@eukrea.com", "time": "Sun Jul 01 19:19:44 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jul 11 11:07:40 2012 +0800" }, "message": "crypto: atmel - add Atmel AES driver\n\nSigned-off-by: Nicolas Royer \u003cnicolas@eukrea.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nAcked-by: Eric Bénard \u003ceric@eukrea.com\u003e\nTested-by: Eric Bénard \u003ceric@eukrea.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "95ead5d7ff824a01cb07921c9211a7e29437a929", "tree": "8d70af66dea817970adb33ff30beb4d641d563b6", "parents": [ "3621189064301a5fbb5d06ca17d966a026f4e501" ], "author": { "name": "Seth Jennings", "email": "sjenning@linux.vnet.ibm.com", "time": "Wed Jun 13 13:22:42 2012 -0500" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Jun 27 14:42:00 2012 +0800" }, "message": "crypto: nx - move nx build to driver/crypto Makefile\n\nWhen the nx driver was pulled, the Makefile that actually\nbuilds it is arch/powerpc/Makefile. This is unnatural.\n\nThis patch moves the line that builds the nx driver from\narch/powerpc/Makefile to drivers/crypto/Makefile where it\nbelongs.\n\nSigned-off-by: Seth Jennings \u003csjenning@linux.vnet.ibm.com\u003e\nAcked-by: Kent Yoder \u003ckey@linux.vnet.ibm.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "b8840098b70c11d70c29263e0765f103e6cbe55e", "tree": "4d9c7f993f7afd5ac365741976186496a169c74a", "parents": [ "a482b081a2d4d74d16bc9ea8779f9f6055f95852" ], "author": { "name": "Sonic Zhang", "email": "sonic.zhang@analog.com", "time": "Mon Jun 04 12:24:47 2012 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Jun 12 16:37:19 2012 +0800" }, "message": "crypto: bfin_crc - CRC hardware driver for BF60x family processors.\n\nThe CRC peripheral is a hardware block used to compute the CRC of the block\nof data. This is based on a CRC32 engine which computes the CRC value of 32b\ndata words presented to it. For data words of \u003c 32b in size, this driver\npack 0 automatically into 32b data units. This driver implements the async\nhash crypto framework API.\n\nSigned-off-by: Sonic Zhang \u003csonic.zhang@analog.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "2789c08fffeae270820dda5d096634aecc810af5", "tree": "113e76a6908b4b786374c53f010c472a3d663514", "parents": [ "028fdd87b79a45544a2b6902989f2cbbf73a3eac" ], "author": { "name": "Andreas Westin", "email": "andreas.westin@stericsson.com", "time": "Mon Apr 30 10:11:17 2012 +0200" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri May 04 19:04:51 2012 +1000" }, "message": "crypto: ux500 - Add driver for CRYP hardware\n\nThis adds a driver for the ST-Ericsson ux500 crypto hardware\nmodule. It supports AES, DES and 3DES, the driver implements\nsupport for AES-ECB,CBC and CTR.\n\nAcked-by: Linus Walleij \u003clinus.walleij@linaro.org\u003e\nSigned-off-by: Andreas Westin \u003candreas.westin@stericsson.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "f1df57d02a0f83e764b4dc9187f58665d70f190e", "tree": "a5b1177f864bef22665c0e3ca704917b014dcdb1", "parents": [ "e87e06cd8cc09afbbf61de1380913d51bf4dffb3" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Fri Jan 13 16:38:37 2012 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Jan 13 16:38:37 2012 +1100" }, "message": "crypto: driver for Tegra AES hardware\n\ndriver supports ecb/cbc/ofb/ansi_x9.31rng modes,\n128, 192 and 256-bit key sizes\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "a49e490c7a8a5c6c9474b1936ad8048f3e4440fc", "tree": "5d55ab67cf6f412a4b060133c980fff887f3304b", "parents": [ "b3b7f0550f84e06ae60df0a13c2992792fbd1af9" ], "author": { "name": "Vladimir Zapolskiy", "email": "vzapolskiy@gmail.com", "time": "Fri Apr 08 20:40:51 2011 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Apr 08 20:40:51 2011 +0800" }, "message": "crypto: s5p-sss - add S5PV210 advanced crypto engine support\n\nThis change adds support for AES encrypting and decrypting using\nadvanced crypto engine found on Samsung S5PV210 and S5PC110 SoCs.\n\nSigned-off-by: Vladimir Zapolskiy \u003cvzapolskiy@gmail.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "8e8ec596e6c0144e2dd500a57ee23dde9684df46", "tree": "6ca9b342f37b3dc7a62621e544c8861920668117", "parents": [ "60af520cf264ea26b2af3a6871bbd71850522aea" ], "author": { "name": "Kim Phillips", "email": "kim.phillips@freescale.com", "time": "Sun Mar 13 16:54:26 2011 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Sun Mar 27 10:45:16 2011 +0800" }, "message": "crypto: caam - Add support for the Freescale SEC4/CAAM\n\nThe SEC4 supercedes the SEC2.x/3.x as Freescale\u0027s\nIntegrated Security Engine. Its programming model is\nincompatible with all prior versions of the SEC (talitos).\n\nThe SEC4 is also known as the Cryptographic Accelerator\nand Assurance Module (CAAM); this driver is named caam.\n\nThis initial submission does not include support for Data Path\nmode operation - AEAD descriptors are submitted via the job\nring interface, while the Queue Interface (QI) is enabled\nfor use by others. Only AEAD algorithms are implemented\nat this time, for use with IPsec.\n\nMany thanks to the Freescale STC team for their contributions\nto this driver.\n\nSigned-off-by: Steve Cornelius \u003csec@pobox.com\u003e\nSigned-off-by: Kim Phillips \u003ckim.phillips@freescale.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "ce92136843cb6e14aba5fd7bc4e88dbe71e70c5a", "tree": "5ff99cc504181f37279f388bd502e624d101aa73", "parents": [ "bd1f2996b44a1c8bde76a6fecd10f36b6eb948d7" ], "author": { "name": "Jamie Iles", "email": "jamie@jamieiles.com", "time": "Mon Feb 21 16:43:21 2011 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Feb 21 22:42:40 2011 +1100" }, "message": "crypto: picoxcell - add support for the picoxcell crypto engines\n\nPicochip picoXcell devices have two crypto engines, one targeted\nat IPSEC offload and the other at WCDMA layer 2 ciphering.\n\nSigned-off-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "6d388b43d2c4ef6f0806c9bb9a5edebf00a23c6a", "tree": "e65d6ddcbe932751abd5aa357fcb683570444d15", "parents": [ "f4e523f2ad179f6bf5691ddc3cd2893856fafc66" ], "author": { "name": "Tracey Dent", "email": "tdent48227@gmail.com", "time": "Tue Oct 19 20:52:26 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Tue Oct 19 20:52:26 2010 +0800" }, "message": "crypto: Makefile - replace the use of \u003cmodule\u003e-objs with \u003cmodule\u003e-y\n\nChanged \u003cmodule\u003e-objs to \u003cmodule\u003e-y in Makefile.\n\nSigned-off-by: Tracey Dent \u003ctdent48227@gmail.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "537559a5b3ef854772bd89fbb43aa77d0bbfb721", "tree": "7341e9a9b9b91fbada30ef903950e5e12f5a74a1", "parents": [ "b744c679f62b368cb94c21c1dcd4618e42d88d63" ], "author": { "name": "Dmitry Kasatkin", "email": "dmitry.kasatkin@nokia.com", "time": "Fri Sep 03 19:16:02 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Sep 03 19:16:02 2010 +0800" }, "message": "crypto: omap-aes - OMAP2/3 AES hw accelerator driver\n\nSigned-off-by: Dmitry Kasatkin \u003cdmitry.kasatkin@nokia.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "0a625fd2abaa0aa0a6852b153d429dbc784748cc", "tree": "5d3664ed5681b4235bd9a112589d8c9dcbeb8021", "parents": [ "bf06099db18a1244957076e51847c644cfe46808" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed May 19 14:14:04 2010 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed May 19 14:14:04 2010 +1000" }, "message": "crypto: n2 - Add Niagara2 crypto driver\n\nCurrent deficiencies:\n\n1) No HMAC hash support yet.\n\n2) Although the algs are registered as ASYNC they always run\n synchronously.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "8628e7c89075834fc7b44629d09ff4f9043af114", "tree": "ac9e440a8452e13a56243714009ba8c6a110da2e", "parents": [ "ee5500c45c4860a84bba502c6d9ef5af6395dad6" ], "author": { "name": "Dmitry Kasatkin", "email": "dmitry.kasatkin@nokia.com", "time": "Mon May 03 11:10:59 2010 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon May 03 11:10:59 2010 +0800" }, "message": "crypto: omap - sha1 \u0026 md5 driver\n\nEarlier kernel contained omap sha1 and md5 driver, which was not maintained,\nwas not ported to new crypto APIs and removed from the source tree.\n\n- implements async crypto API using dma and cpu.\n- supports multiple sham instances if available\n- hmac\n- concurrent requests\n\nSigned-off-by: Dmitry Kasatkin \u003cdmitry.kasatkin@nokia.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "85a7f0ac5370901916a21935e1fafbe397b70f80", "tree": "e2bd5a67fee689f7a92ece61cfea8e2b192215a3", "parents": [ "ace1366369841c9c3a9788f79baa4d73f1c53107" ], "author": { "name": "Sebastian Andrzej Siewior", "email": "sebastian@breakpoint.cc", "time": "Mon Aug 10 12:50:03 2009 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Mon Aug 10 12:50:03 2009 +1000" }, "message": "crypto: mv_cesa - Add support for Orion5X crypto engine\n\nThis adds support for Marvell\u0027s Cryptographic Engines and Security\nAccelerator (CESA) which can be found on a few SoC.\nTested with dm-crypt.\n\nAcked-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nSigned-off-by: Sebastian Andrzej Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "049359d655277c382683a6030ae0bac485568ffc", "tree": "36d2c702b4b289ca949e439620f2801158b21fd4", "parents": [ "5b07bd57016fb1033c678746f90bfc3c12d3e494" ], "author": { "name": "James Hsiao", "email": "jhsiao@amcc.com", "time": "Thu Feb 05 16:18:13 2009 +1100" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed Feb 18 16:49:43 2009 +0800" }, "message": "crypto: amcc - Add crypt4xx driver\n\nThis patch adds support for AMCC ppc4xx security device driver. This is the\ninitial release that includes the driver framework with AES and SHA1 algorithms\nsupport.\n\nThe remaining algorithms will be released in the near future.\n\nSigned-off-by: James Hsiao \u003cjhsiao@amcc.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "81bef0150074d677d8cbd4e971a8ce6c9746a1fc", "tree": "57e263d8f89b8c6eb7532efd5e3f438044393675", "parents": [ "9c4a79653b35efc9d6790c295e22f79f4b361125" ], "author": { "name": "Christian Hohnstaedt", "email": "chohnstaedt@innominate.com", "time": "Wed Jun 25 14:38:47 2008 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Jul 10 20:35:16 2008 +0800" }, "message": "crypto: ixp4xx - Hardware crypto support for IXP4xx CPUs\n\nAdd support for the hardware crypto engine provided by the NPE C\nof the Intel IXP4xx networking processor series.\n\nSupported ciphers: des, des3, aes\nand a combination of them with md5 and sha1 hmac\n\nSigned-off-by: Christian Hohnstaedt \u003cchohnstaedt@innominate.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "9c4a79653b35efc9d6790c295e22f79f4b361125", "tree": "8cc3f6f9b4663d0bc4a4a02ae1adbb12c88c4a6f", "parents": [ "d729de23e86bbbb28adf6c3ded3651ea4ad8c539" ], "author": { "name": "Kim Phillips", "email": "kim.phillips@freescale.com", "time": "Mon Jun 23 19:50:15 2008 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Jul 10 20:35:16 2008 +0800" }, "message": "crypto: talitos - Freescale integrated security engine (SEC) driver\n\nAdd support for the SEC available on a wide range of PowerQUICC devices,\ne.g. MPC8349E, MPC8548E.\n\nThis initial version supports authenc(hmac(sha1),cbc(aes)) for use with IPsec.\n\nSigned-off-by: Kim Phillips \u003ckim.phillips@freescale.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "f7d0561ea1dadec5462846520b1f4fb304294fd5", "tree": "50109416f7a2780a19ee1d8fbc538f65b081ef5e", "parents": [ "23e353c8a681cc30d42fbd4f2c2be85c44fe209b" ], "author": { "name": "Evgeniy Polyakov", "email": "johnpol@2ka.mipt.ru", "time": "Fri Oct 26 21:31:14 2007 +0800" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Fri Jan 11 08:16:01 2008 +1100" }, "message": "[CRYPTO] hifn_795x: HIFN 795x driver\n\nThis is a driver for HIFN 795x crypto accelerator chips.\n\nIt passed all tests for AES, DES and DES3_EDE except weak test for DES,\nsince hardware can not determine weak keys.\n\nSigned-off-by: Evgeniy Polyakov \u003cjohnpol@2ka.mipt.ru\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "f6259deacfd55607ae57cff422d3bc7694ea14e7", "tree": "d984d50afb2ee4cfa941008fd879fd64ca9629a0", "parents": [ "e196d6259141eda47aeafd88514aae652bfbfc7f" ], "author": { "name": "Simon Arlott", "email": "simon@fire.lp0.eu", "time": "Wed May 02 22:08:26 2007 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Wed May 02 22:08:26 2007 +1000" }, "message": "[CRYPTO] padlock: Remove pointless padlock module\n\nWhen this is compiled in it is run too early to do anything useful:\n[ 6.052000] padlock: No VIA PadLock drivers have been loaded.\n[ 6.052000] padlock: Using VIA PadLock ACE for AES algorithm.\n[ 6.052000] padlock: Using VIA PadLock ACE for SHA1/SHA256 algorithms.\n\nWhen it\u0027s a module it isn\u0027t doing anything special, the same functionality \ncan be provided in userspace by \"probeall padlock padlock-aes padlock-sha\" \nin modules.conf if it is required.\n\nSigned-off-by: Simon Arlott \u003csimon@fire.lp0.eu\u003e\nCc: Michal Ludvig \u003cmichal@logix.cz\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "9fe757b0cfcee0724027a675c533077287a21b96", "tree": "a68942e39e350e78b0b9e0fcfa701b9ddbcf5a70", "parents": [ "94b9bb5480e73cec4552b19fc3f809742b4ebf67" ], "author": { "name": "Jordan Crouse", "email": "jordan.crouse@amd.com", "time": "Wed Oct 04 18:48:57 2006 +1000" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Dec 06 18:38:46 2006 -0800" }, "message": "[PATCH] crypto: Add support for the Geode LX AES hardware\n\nAdd a driver to support the AES hardware on the Geode LX processor.\n\nSigned-off-by: Jordan Crouse \u003cjordan.crouse@amd.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "5644bda5d6aa17a70b8842eb56365d501a5da159", "tree": "ac19f321bdc0dfa081e4ea7348584f516f6a7e7b", "parents": [ "cb17530b0a4e01bd595a7ac437467a1a9833a15c" ], "author": { "name": "Michal Ludvig", "email": "michal@logix.cz", "time": "Sun Aug 06 22:50:30 2006 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Sep 21 11:41:00 2006 +1000" }, "message": "[CRYPTO] padlock: Helper module padlock.ko\n\nCompile a helper module padlock.ko that will try\nto autoload all configured padlock algorithms.\n\nThis also provides backward compatibility with \nthe ancient times before padlock.ko was renamed \nto padlock-aes.ko\n\nSigned-off-by: Michal Ludvig \u003cmichal@logix.cz\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "6c833275152b454d311f0e70b5e6bf028b4a2aaf", "tree": "a08d9d1057730c1c5dde31de1db0bd81810ee8d2", "parents": [ "ccc17c34d676f116bd09dd36a3b01627bc6a2f8a" ], "author": { "name": "Michal Ludvig", "email": "michal@logix.cz", "time": "Wed Jul 12 12:29:38 2006 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Sep 21 11:40:59 2006 +1000" }, "message": "[CRYPTO] padlock: Driver for SHA1 / SHA256 algorithms\n\nSupport for SHA1 / SHA256 algorithms in VIA C7 processors.\n\nSigned-off-by: Michal Ludvig \u003cmichal@logix.cz\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "1191f0a49390caf16f4a2831a4fc373757471ad6", "tree": "8b92255ab82b777feade49a68cc0dc9691f1c665", "parents": [ "b14cdd6704c96474ba5c74b5959487beaa5ee1cd" ], "author": { "name": "Michal Ludvig", "email": "michal@logix.cz", "time": "Sun Aug 06 22:46:20 2006 +1000" }, "committer": { "name": "Herbert Xu", "email": "herbert@gondor.apana.org.au", "time": "Thu Sep 21 11:40:21 2006 +1000" }, "message": "[CRYPTO] padlock: Get rid of padlock-generic.c\n\nMerge padlock-generic.c into padlock-aes.c and compile\nAES as a standalone module. We won\u0027t make a monolithic\npadlock.ko with all supported algorithms, instead we\u0027ll\ncompile each driver into its own module.\n\nSigned-off-by: Michal Ludvig \u003cmichal@logix.cz\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d", "parents": [], "author": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n" } ] }