)]}'
{
  "log": [
    {
      "commit": "209b84a88fe81341b4d8d465acc4a67cb7c3feb3",
      "tree": "134632ed8c914f0ee497e7a22bc616d84e068119",
      "parents": [
        "74465b4ff9ac1da503025c0a0042e023bfa6505c"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:17 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:17 2009 -0700"
      },
      "message": "dmaengine: replace dma_async_client_register with dmaengine_get\n\nNow that clients no longer need to be notified of channel arrival\ndma_async_client_register can simply increment the dmaengine_ref_count.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "2ba05622b8b143b0c95968ba59bddfbd6d2f2559",
      "tree": "b7b72d02a993ff2ba731d6608f4ab8ce87482bcb",
      "parents": [
        "bec085134e446577a983f17f57d642a88d1af53b"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:14 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:14 2009 -0700"
      },
      "message": "dmaengine: provide a common \u0027issue_pending_all\u0027 implementation\n\nasync_tx and net_dma each have open-coded versions of issue_pending_all,\nso provide a common routine in dmaengine.\n\nThe implementation needs to walk the global device list, so implement\nrcu to allow dma_issue_pending_all to run lockless.  Clients protect\nthemselves from channel removal events by holding a dmaengine reference.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n"
    },
    {
      "commit": "bec085134e446577a983f17f57d642a88d1af53b",
      "tree": "7d29afc53fedc72349ee78112fb71f68ff48ce24",
      "parents": [
        "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:14 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:14 2009 -0700"
      },
      "message": "dmaengine: centralize channel allocation, introduce dma_find_channel\n\nAllowing multiple clients to each define their own channel allocation\nscheme quickly leads to a pathological situation.  For memory-to-memory\noffload all clients can share a central allocator.\n\nThis simply moves the existing async_tx allocator to dmaengine with\nminimal fixups:\n* async_tx.c:get_chan_ref_by_cap --\u003e dmaengine.c:nth_chan\n* async_tx.c:async_tx_rebalance --\u003e dmaengine.c:dma_channel_rebalance\n* split out common code from async_tx.c:__async_tx_find_channel --\u003e\n  dma_find_channel\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n"
    },
    {
      "commit": "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1",
      "tree": "afba24357d1f4ff69ccb2b39a19542546590a50b",
      "parents": [
        "07f2211e4fbce6990722d78c4f04225da9c0e9cf"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:14 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:14 2009 -0700"
      },
      "message": "dmaengine: up-level reference counting to the module level\n\nSimply, if a client wants any dmaengine channel then prevent all dmaengine\nmodules from being removed.  Once the clients are done re-enable module\nremoval.\n\nWhy?, beyond reducing complication:\n1/ Tracking reference counts per-transaction in an efficient manner, as\n   is currently done, requires a complicated scheme to avoid cache-line\n   bouncing effects.\n2/ Per-transaction ref-counting gives the false impression that a\n   dma-driver can be gracefully removed ahead of its user (net, md, or\n   dma-slave)\n3/ None of the in-tree dma-drivers talk to hot pluggable hardware, but\n   if such an engine were built one day we still would not need to notify\n   clients of remove events.  The driver can simply return NULL to a\n   -\u003eprep() request, something that is much easier for a client to handle.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n"
    },
    {
      "commit": "07f2211e4fbce6990722d78c4f04225da9c0e9cf",
      "tree": "51934e20a334e93c8c399d2e6375f264551e9bc3",
      "parents": [
        "28405d8d9ce05f5bd869ef8b48da5086f9527d73"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Jan 05 17:14:31 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Jan 05 18:10:19 2009 -0700"
      },
      "message": "dmaengine: remove dependency on async_tx\n\nasync_tx.ko is a consumer of dma channels.  A circular dependency arises\nif modules in drivers/dma rely on common code in async_tx.ko.  It\nprevents either module from being unloaded.\n\nMove dma_wait_for_async_tx and async_tx_run_dependencies to dmaeninge.o\nwhere they should have been from the beginning.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "a06d568f7c5e40e34ea64881842deb8f4382babf",
      "tree": "15b38b4652705b7c58bd89052c81ab91ca94cc4a",
      "parents": [
        "b0b42b16ff2b90f17bc1a4308366c9beba4b276e"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Dec 08 13:46:00 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Dec 08 13:46:00 2008 -0700"
      },
      "message": "async_xor: dma_map destination DMA_BIDIRECTIONAL\n\nMapping the destination multiple times is a misuse of the dma-api.\nSince the destination may be reused as a source, ensure that it is only\nmapped once and that it is mapped bidirectionally.  This appears to add\nugliness on the unmap side in that it always reads back the destination\naddress from the descriptor, but gcc can determine that dma_unmap is a\nnop and not emit the code that calculates its arguments.\n\nCc: \u003cstable@kernel.org\u003e\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nAcked-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "fdb0ac80618729e6b12121c66449b8532990eaf3",
      "tree": "7572761bb23e6cc87ef2ffb061d9998f4e4dfd57",
      "parents": [
        "6bfb09a1005193be5c81ebac9f3ef85210142650"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Sep 13 19:57:04 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Sep 13 19:57:04 2008 -0700"
      },
      "message": "async_tx: make async_tx_run_dependencies() easier to read\n\n* Rename \u0027next\u0027 to \u0027dep\u0027\n* Move the channel switch check inside the loop to simplify\n  termination\n\nAcked-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "de24125dd0a452bfd4502fc448e3534c5d2e87aa",
      "tree": "30b86411bdbbe6ebea4598bd82856a399f66bd88",
      "parents": [
        "b380b0d4f7dffcc235c0facefa537d4655619101"
      ],
      "author": {
        "name": "Yuri Tikhonov",
        "email": "yur@emcraft.com",
        "time": "Fri Sep 05 08:15:47 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Sep 05 08:15:47 2008 -0700"
      },
      "message": "async_tx: fix the bug in async_tx_run_dependencies\n\nShould clear the next pointer of the TX if we are sure that the\nnext TX (say NXT) will be submitted to the channel too. Overwise,\nwe break the chain of descriptors, because we lose the information\nabout the next descriptor to run. So next time, when invoke\nasync_tx_run_dependencies() with TX, it\u0027s TX-\u003enext will be NULL, and\nNXT will be never submitted.\n\nCc: \u003cstable@kernel.org\u003e\t\t[2.6.26]\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "e34a8ae79056e6cea4a1ac21119ee3c91f378f99",
      "tree": "8ff15ee52e38b2e0031e71313a01668589e6dccc",
      "parents": [
        "ca5de404ff036a29b25e9a83f6919c9f606c5841"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Aug 05 10:22:05 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Aug 05 10:25:20 2008 -0700"
      },
      "message": "async_tx: fix missing braces in async_xor_zero_sum\n\nFound-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "5554b35933245e95710d709175e14c02cbc956a4",
      "tree": "2eeb2f05a7061da3c9a3bc9ea69a344b990c6b49",
      "parents": [
        "0f6e38a6381446eff5175b77d1094834a633a90f",
        "7f1b358a236ee9c19657a619ac6f2dcabcaa0924"
      ],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Wed Jul 23 12:03:18 2008 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Wed Jul 23 12:03:18 2008 -0700"
      },
      "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (24 commits)\n  I/OAT: I/OAT version 3.0 support\n  I/OAT: tcp_dma_copybreak default value dependent on I/OAT version\n  I/OAT: Add watchdog/reset functionality to ioatdma\n  iop_adma: cleanup iop_chan_xor_slot_count\n  iop_adma: document how to calculate the minimum descriptor pool size\n  iop_adma: directly reclaim descriptors on allocation failure\n  async_tx: make async_tx_test_ack a boolean routine\n  async_tx: remove depend_tx from async_tx_sync_epilog\n  async_tx: export async_tx_quiesce\n  async_tx: fix handling of the \"out of descriptor\" condition in async_xor\n  async_tx: ensure the xor destination buffer remains dma-mapped\n  async_tx: list_for_each_entry_rcu() cleanup\n  dmaengine: Driver for the Synopsys DesignWare DMA controller\n  dmaengine: Add slave DMA interface\n  dmaengine: add DMA_COMPL_SKIP_{SRC,DEST}_UNMAP flags to control dma unmap\n  dmaengine: Add dma_client parameter to device_alloc_chan_resources\n  dmatest: Simple DMA memcpy test client\n  dmaengine: DMA engine driver for Marvell XOR engine\n  iop-adma: fix platform driver hotplug/coldplug\n  dmaengine: track the number of clients using a channel\n  ...\n\nFixed up conflict in drivers/dca/dca-sysfs.c manually\n"
    },
    {
      "commit": "3dce01713723bbcc92562bd4488e8b840a4f786c",
      "tree": "7e0720179ad4240b993f86f558a3efa8861f1033",
      "parents": [
        "d2c52b7983b95bb3fc2a784e479f832f142d4523"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:55 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:55 2008 -0700"
      },
      "message": "async_tx: remove depend_tx from async_tx_sync_epilog\n\nAll callers of async_tx_sync_epilog have called async_tx_quiesce on the\ndepend_tx, so async_tx_sync_epilog need only call the callback to\ncomplete the operation.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "d2c52b7983b95bb3fc2a784e479f832f142d4523",
      "tree": "7bc37e7438cee523496674adcd97034df764af47",
      "parents": [
        "669ab0b210f9bd15d94d4d6a49ae13366a85e4da"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:55 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:55 2008 -0700"
      },
      "message": "async_tx: export async_tx_quiesce\n\nReplace open coded \"wait and acknowledge\" instances with async_tx_quiesce.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "669ab0b210f9bd15d94d4d6a49ae13366a85e4da",
      "tree": "ead561418e94def95c4d4b4512ae3c9a7888febe",
      "parents": [
        "1e55db2d6bdef92abc981b68673564e63c80da4d"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:55 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:55 2008 -0700"
      },
      "message": "async_tx: fix handling of the \"out of descriptor\" condition in async_xor\n\nEnsure forward progress is made when a dmaengine driver is unable to\nallocate an xor descriptor by breaking the dependency chain with\nasync_tx_quisce() and issue any pending descriptors.\n\nTested with iop-adma by setting device-\u003emax_xor \u003d 2 to force multiple\ncalls to device_prep_dma_xor for each call to async_xor and limiting the\ndescriptor slot pool to 5.  Discovered that the minimum descriptor pool\nsize for iop-adma is 2 * iop_chan_xor_slot_cnt(device-\u003emax_xor) + 1.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "1e55db2d6bdef92abc981b68673564e63c80da4d",
      "tree": "ac3cd7c249735772df8c08b1d803563bad854527",
      "parents": [
        "20fc190b0ef58bf8b3b0bff9de122083956f82ec"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Jul 16 19:44:56 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:55 2008 -0700"
      },
      "message": "async_tx: ensure the xor destination buffer remains dma-mapped\n\nWhen the number of source buffers for an xor operation exceeds the hardware\nchannel maximum async_xor creates a chain of dependent operations.  The result\nof one operation is reused as an input to the next to continue the xor\ncalculation.  The destination buffer should remain mapped for the duration of\nthe entire chain.  To provide this guarantee the code must no longer be allowed\nto fallback to the synchronous path as this will preclude the buffer from being\nunmapped, i.e. the dma-driver will potentially miss the descriptor with\n!DMA_COMPL_SKIP_DEST_UNMAP.\n\nCc: Neil Brown \u003cneilb@suse.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "20fc190b0ef58bf8b3b0bff9de122083956f82ec",
      "tree": "81512548e0f7b74b2f96b664e389fda5d9fad29a",
      "parents": [
        "3bfb1d20b547a5071d01344581eac5846ea84491"
      ],
      "author": {
        "name": "Li Zefan",
        "email": "lizf@cn.fujitsu.com",
        "time": "Thu Jul 17 17:59:47 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:47 2008 -0700"
      },
      "message": "async_tx: list_for_each_entry_rcu() cleanup\n\nIn the rcu update side, don\u0027t use list_for_each_entry_rcu().\n\nSigned-off-by: Li Zefan \u003clizf@cn.fujitsu.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "65bc3ffe8c067e387fe5557bc3ea5071071f6af9",
      "tree": "71d7eb925b020a6e45d8d1a4047b961df34cff97",
      "parents": [
        "51ee87f27a1d2c0e08492924f2fb0223c4c704d9"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jun 05 23:26:11 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:57:55 2008 -0700"
      },
      "message": "async_tx: fix async_memset compile error\n\ncommit 636bdeaa \u0027dmaengine: ack to flags: make use of the unused bits in\nthe \u0027ack\u0027 field\u0027 missed an -\u003eack conversion in\ncrypto/async_tx/async_memset.c\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "82524746c27fa418c250a56dd7606b9d3fc79826",
      "tree": "1801230b8fc2e436e722ac6f54fc53f1c112c310",
      "parents": [
        "32300751b4079cb5688453baa94711579d4285d5"
      ],
      "author": {
        "name": "Franck Bui-Huu",
        "email": "fbuihuu@gmail.com",
        "time": "Mon May 12 21:21:05 2008 +0200"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Mon May 19 10:01:37 2008 +0200"
      },
      "message": "rcu: split list.h and move rcu-protected lists into rculist.h\n\nMove rcu-protected lists from list.h into a new header file rculist.h.\n\nThis is done because list are a very used primitive structure all over the\nkernel and it\u0027s currently impossible to include other header files in this\nlist.h without creating some circular dependencies.\n\nFor example, list.h implements rcu-protected list and uses rcu_dereference()\nwithout including rcupdate.h.  It actually compiles because users of\nrcu_dereference() are macros.  Others RCU functions could be used too but\naren\u0027t probably because of this.\n\nTherefore this patch creates rculist.h which includes rcupdates without to\nmany changes/troubles.\n\nSigned-off-by: Franck Bui-Huu \u003cfbuihuu@gmail.com\u003e\nAcked-by: Paul E. McKenney \u003cpaulmck@linux.vnet.ibm.com\u003e\nAcked-by: Josh Triplett \u003cjosh@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "636bdeaa1243327501edfd2a597ed7443eb4239a",
      "tree": "59b894f124e3664ea4a537d7c07c527abdb9c8da",
      "parents": [
        "c4fe15541d0ef5cc8cc1ce43057663851f8fc387"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:26 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:54 2008 -0700"
      },
      "message": "dmaengine: ack to flags: make use of the unused bits in the \u0027ack\u0027 field\n\n\u0027ack\u0027 is currently a simple integer that flags whether or not a client is done\ntouching fields in the given descriptor.  It is effectively just a single bit\nof information.  Converting this to a flags parameter allows the other bits to\nbe put to use to control completion actions, like dma-unmap, and capture\nresults, like xor-zero-sum \u003d\u003d 0.\n\nChanges are one of:\n1/ convert all open-coded -\u003eack manipulations to use async_tx_ack\n   and async_tx_test_ack.\n2/ set the ack bit at prep time where possible\n3/ make drivers store the flags at prep time\n4/ add flags to the device_prep_dma_interrupt prototype\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "19242d7233df7d658405d4b7ee1758d21414cfaa",
      "tree": "4bffa2700c30fdb454dfa150115a0607c6cf3d2a",
      "parents": [
        "1c62979ed29a8e2bf9fbe1db101c81a0089676f8"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:25 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:05 2008 -0700"
      },
      "message": "async_tx: fix multiple dependency submission\n\nShrink struct dma_async_tx_descriptor and introduce\nasync_tx_channel_switch to properly inject a channel switch interrupt in\nthe descriptor stream.  This simplifies the locking model as drivers no\nlonger need to handle dma_async_tx_descriptor.lock.\n\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "8d8002f642886ae256a3c5d70fe8aff4faf3631a",
      "tree": "81a3df533e7a0ad2d268b28fba1507e770df0f55",
      "parents": [
        "f79abb627f033c85a6088231f20c85bc4a9bd757"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Mar 18 21:23:59 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Mar 18 17:01:00 2008 -0700"
      },
      "message": "async_tx: avoid the async xor_zero_sum path when src_cnt \u003e device-\u003emax_xor\n\nIf the channel cannot perform the operation in one call to\n-\u003edevice_prep_dma_zero_sum, then fallback to the xor+page_is_zero path.\nThis only affects users with arrays larger than 16 devices on iop13xx or\n32 devices on iop3xx.\n\nCc: \u003cstable@kernel.org\u003e\nCc: Neil Brown \u003cneilb@suse.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "3280ab3e8815d60cea483d49b21261972e2785d6",
      "tree": "6f74b532ce482fc8bcdb0fdbca3a823053b6cc37",
      "parents": [
        "3d9b525b69bc3302d8355e5f5cf081a856c211e0"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Mar 13 17:45:28 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Mar 13 10:57:10 2008 -0700"
      },
      "message": "async_tx: checkpatch says s/__FUNCTION__/__func__/g\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "47437b2c9a64315efeb3d84e97ffefd6c3c67ef1",
      "tree": "e0dec7b29bebb0a2113f143576d940c571869aa0",
      "parents": [
        "d4c56f97ff21df405d0cebe11f49e3c3c79662b5"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:59 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:18 2008 -0700"
      },
      "message": "async_tx: allow architecture specific async_tx_find_channel implementations\n\nThe source and destination addresses are included to allow channel\nselection based on address alignment.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n"
    },
    {
      "commit": "d4c56f97ff21df405d0cebe11f49e3c3c79662b5",
      "tree": "e6b0de433d7c985982ac12815998242a786d87b2",
      "parents": [
        "0036731c88fdb5bf4f04a796a30b5e445fc57f54"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:58 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:18 2008 -0700"
      },
      "message": "async_tx: replace \u0027int_en\u0027 with operation preparation flags\n\nPass a full set of flags to drivers\u0027 per-operation \u0027prep\u0027 routines.\nCurrently the only flag passed is DMA_PREP_INTERRUPT.  The expectation is\nthat arch-specific async_tx_find_channel() implementations can exploit this\ncapability to find the best channel for an operation.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n"
    },
    {
      "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54",
      "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e",
      "parents": [
        "d909b347591a23c5a2c324fbccd4c9c966f31c67"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:57 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead.  Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses.  In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses.  This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *).  As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G.  It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n"
    },
    {
      "commit": "d909b347591a23c5a2c324fbccd4c9c966f31c67",
      "tree": "1092bfdc2722eed041a29752a62836366855c30a",
      "parents": [
        "e73ef9acfd30f36bf7c60237ecffe7bbca8068d6"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:30:14 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: kill ASYNC_TX_ASSUME_COHERENT\n\nRemove the unused ASYNC_TX_ASSUME_COHERENT flag.  Async_tx is\nmeant to hide the difference between asynchronous hardware and synchronous\nsoftware operations, this flag requires clients to understand cache\ncoherency consequences of the async path.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n"
    },
    {
      "commit": "cf8f68aa76e8e12f9dcbba3ffe61fb9f2a3a0c2b",
      "tree": "f53fa3040cfd8fcc47eb8aaed60a0a79181cd9b2",
      "parents": [
        "1367a3d310afc1ce758c8b94a0dc77834b4494a0"
      ],
      "author": {
        "name": "Denis Cheng",
        "email": "crquan@gmail.com",
        "time": "Sat Feb 02 19:29:58 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: use LIST_HEAD instead of LIST_HEAD_INIT\n\nsingle list_head variable initialized with LIST_HEAD_INIT could almost\nalways can be replaced with LIST_HEAD declaration, this shrinks the code\nand looks better.\n\nSigned-off-by: Denis Cheng \u003ccrquan@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "1367a3d310afc1ce758c8b94a0dc77834b4494a0",
      "tree": "cf6938c1662074f26ee16ff02d3c38332bc010ef",
      "parents": [
        "551e4fb2465b87de9d4aa1669b27d624435443bb"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 18:46:43 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: fix compile breakage, mark do_async_xor __always_inline\n\ndo_async_xor must be compiled away on !HAS_DMA archs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Cornelia Huck \u003ccornelia.huck@de.ibm.com\u003e\n"
    },
    {
      "commit": "6247cdc2cd334dad0ea5428245a7d8f4b075f21e",
      "tree": "275bfcdb142a92ea347d264b6b37b17c98d41733",
      "parents": [
        "c5d2b9f444b8d9f5ad7c5e583686c119ba3a9ba7"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Sep 21 13:27:04 2007 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Sep 24 10:26:26 2007 -0700"
      },
      "message": "async_tx: fix dma_wait_for_async_tx\n\nFix dma_wait_for_async_tx to not loop forever in the case where a\ndependency chain is longer than two entries.  This condition will not\nhappen with current in-kernel drivers, but fix it for future drivers.\n\nFound-by: Saeed Bishara \u003csaeed.bishara@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "eb0645a8b1f14da300f40bb9f424640cd1181fbf",
      "tree": "462789626fcd1775bec80d74d19bcd68797589c8",
      "parents": [
        "7c6129c68fe90a61166800b40217a850b8faee98"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 20 00:31:46 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Fri Jul 20 08:44:19 2007 -0700"
      },
      "message": "async_tx: fix kmap_atomic usage in async_memcpy\n\nAndrew Morton:\n\t[async_memcpy] is very wrong if both ASYNC_TX_KMAP_DST and\n\tASYNC_TX_KMAP_SRC can ever be set.  We\u0027ll end up using the same kmap\n\tslot for both src add dest and we get either corrupted data or a BUG.\n\nEvgeniy Polyakov:\n\tBtw, shouldn\u0027t it always be kmap_atomic() even if flag is not set.\n\tThat pages are usual one returned by alloc_page().\n\nSo fix the usage of kmap_atomic and kill the ASYNC_TX_KMAP_DST and\nASYNC_TX_KMAP_SRC flags.\n\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Evgeniy Polyakov \u003cjohnpol@2ka.mipt.ru\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "9bc89cd82d6f88fb0ca39b30445c329a430fd66b",
      "tree": "7bd0e856abd359f84edea1bacfd1dd32edd93fbb",
      "parents": [
        "685784aaf3cd0e3ff5e36c7ecf6f441cdbf57f73"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 02 11:10:44 2007 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 13 08:06:14 2007 -0700"
      },
      "message": "async_tx: add the async_tx api\n\nThe async_tx api provides methods for describing a chain of asynchronous\nbulk memory transfers/transforms with support for inter-transactional\ndependencies.  It is implemented as a dmaengine client that smooths over\nthe details of different hardware offload engine implementations.  Code\nthat is written to the api can optimize for asynchronous operation and the\napi will fit the chain of operations to the available offload resources. \n \n\tI imagine that any piece of ADMA hardware would register with the\n\t\u0027async_*\u0027 subsystem, and a call to async_X would be routed as\n\tappropriate, or be run in-line. - Neil Brown\n\nasync_tx exploits the capabilities of struct dma_async_tx_descriptor to\nprovide an api of the following general format:\n\nstruct dma_async_tx_descriptor *\nasync_\u003coperation\u003e(..., struct dma_async_tx_descriptor *depend_tx,\n\t\t\tdma_async_tx_callback cb_fn, void *cb_param)\n{\n\tstruct dma_chan *chan \u003d async_tx_find_channel(depend_tx, \u003coperation\u003e);\n\tstruct dma_device *device \u003d chan ? chan-\u003edevice : NULL;\n\tint int_en \u003d cb_fn ? 1 : 0;\n\tstruct dma_async_tx_descriptor *tx \u003d device ?\n\t\tdevice-\u003edevice_prep_dma_\u003coperation\u003e(chan, len, int_en) : NULL;\n\n\tif (tx) { /* run \u003coperation\u003e asynchronously */\n\t\t...\n\t\ttx-\u003etx_set_dest(addr, tx, index);\n\t\t...\n\t\ttx-\u003etx_set_src(addr, tx, index);\n\t\t...\n\t\tasync_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);\n\t} else { /* run \u003coperation\u003e synchronously */\n\t\t...\n\t\t\u003coperation\u003e\n\t\t...\n\t\tasync_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);\n\t}\n\n\treturn tx;\n}\n\nasync_tx_find_channel() returns a capable channel from its pool.  The\nchannel pool is organized as a per-cpu array of channel pointers.  The\nasync_tx_rebalance() routine is tasked with managing these arrays.  In the\nuniprocessor case async_tx_rebalance() tries to spread responsibility\nevenly over channels of similar capabilities.  For example if there are two\ncopy+xor channels, one will handle copy operations and the other will\nhandle xor.  In the SMP case async_tx_rebalance() attempts to spread the\noperations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor\nchannel0 while cpu1 gets copy channel 1 and xor channel 1.  When a\ndependency is specified async_tx_find_channel defaults to keeping the\noperation on the same channel.  A xor-\u003ecopy-\u003exor chain will stay on one\nchannel if it supports both operation types, otherwise the transaction will\ntransition between a copy and a xor resource.\n\nCurrently the raid5 implementation in the MD raid456 driver has been\nconverted to the async_tx api.  A driver for the offload engines on the\nIntel Xscale series of I/O processors, iop-adma, is provided in a later\ncommit.  With the iop-adma driver and async_tx, raid456 is able to offload\ncopy, xor, and xor-zero-sum operations to hardware engines.\n \nOn iop342 tiobench showed higher throughput for sequential writes (20 - 30%\nimprovement) and sequential reads to a degraded array (40 - 55%\nimprovement).  For the other cases performance was roughly equal, +/- a few\npercentage points.  On a x86-smp platform the performance of the async_tx\nimplementation (in synchronous mode) was also +/- a few percentage points\nof the original implementation.  According to \u0027top\u0027 on iop342 CPU\nutilization drops from ~50% to ~15% during a \u0027resync\u0027 while the speed\naccording to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.\n \nThe tiobench command line used for testing was: tiobench --size 2048\n--block 4096 --block 131072 --dir /mnt/raid --numruns 5\n* iop342 had 1GB of memory available\n\nDetails:\n* if CONFIG_DMA_ENGINE\u003dn the asynchronous path is compiled away by making\n  async_tx_find_channel a static inline routine that always returns NULL\n* when a callback is specified for a given transaction an interrupt will\n  fire at operation completion time and the callback will occur in a\n  tasklet.  if the the channel does not support interrupts then a live\n  polling wait will be performed\n* the api is written as a dmaengine client that requests all available\n  channels\n* In support of dependencies the api implicitly schedules channel-switch\n  interrupts.  The interrupt triggers the cleanup tasklet which causes\n  pending operations to be scheduled on the next channel\n* Xor engines treat an xor destination address differently than a software\n  xor routine.  To the software routine the destination address is an implied\n  source, whereas engines treat it as a write-only destination.  This patch\n  modifies the xor_blocks routine to take a an explicit destination address\n  to mirror the hardware.\n\nChangelog:\n* fixed a leftover debug print\n* don\u0027t allow callbacks in async_interrupt_cond\n* fixed xor_block changes\n* fixed usage of ASYNC_TX_XOR_DROP_DEST\n* drop dma mapping methods, suggested by Chris Leech\n* printk warning fixups from Andrew Morton\n* don\u0027t use inline in C files, Adrian Bunk\n* select the API when MD is enabled\n* BUG_ON xor source counts \u003c\u003d 1\n* implicitly handle hardware concerns like channel switching and\n  interrupts, Neil Brown\n* remove the per operation type list, and distribute operation capabilities\n  evenly amongst the available channels\n* simplify async_tx_find_channel to optimize the fast path\n* introduce the channel_table_initialized flag to prevent early calls to\n  the api\n* reorganize the code to mimic crypto\n* include mm.h as not all archs include it in dma-mapping.h\n* make the Kconfig options non-user visible, Adrian Bunk\n* move async_tx under crypto since it is meant as \u0027core\u0027 functionality, and\n  the two may share algorithms in the future\n* move large inline functions into c files\n* checkpatch.pl fixes\n* gpl v2 only correction\n\nCc: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-By: NeilBrown \u003cneilb@suse.de\u003e\n"
    }
  ]
}