)]}' { "log": [ { "commit": "d8902adcc1a9fd484c8cb5e575152e32192c1ff8", "tree": "305109ce60db5ea9710dddce9db8a23f65ff4572", "parents": [ "9134d02bc0af4a8747d448d1f811ec5f8eb96df6" ], "author": { "name": "Nobuhiro Iwamatsu", "email": "iwamatsu.nobuhiro@renesas.com", "time": "Mon Sep 07 03:26:23 2009 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:02 2009 -0700" }, "message": "dmaengine: sh: Add Support SuperH DMA Engine driver\n\nThis supported all DMA channels, and it was tested in SH7722,\nSH7780, SH7785 and SH7763.\nThis can not use with SH DMA API.\n\nSigned-off-by: Nobuhiro Iwamatsu \u003ciwamatsu.nobuhiro@renesas.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9134d02bc0af4a8747d448d1f811ec5f8eb96df6", "tree": "704c3e5dcc10f360815c4868a74711f82fb62e27", "parents": [ "bbb20089a3275a19e475dbc21320c3742e3ca423", "80ffb3cceaefa405f2ecd46d66500ed8d53efe74" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:54 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:54 2009 -0700" }, "message": "Merge commit \u0027md/for-linus\u0027 into async-tx-next\n\nConflicts:\n\tdrivers/md/raid5.c\n" }, { "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423", "tree": "216fdc1cbef450ca688135c5b8969169482d9a48", "parents": [ "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n" }, { "commit": "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "tree": "dfee34eb1f317b35f33a02291e65ce6ec46e3a5a", "parents": [ "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c", "f6dbf651615900646fe0ba1ef5ce1027e5b4748d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "message": "Merge branch \u0027iop-raid6\u0027 into async-tx-next\n" }, { "commit": "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843", "tree": "74fd6b5c2c35dcea18928a600ff34c04f8626cb6", "parents": [ "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "message": "dmaengine: Move all map_sg/unmap_sg for slave channel to its client\n\nDan Williams wrote:\n... DMA-slave clients request specific channels and know the hardware\ndetails at a low level, so it should not be too high an expectation to\npush dma mapping responsibility to the client.\n\nAlso this patch includes DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE support for\ndw_dmac driver.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d", "tree": "5f2145c023b9145d1461ecb63c839fd32f762378", "parents": [ "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: Add DMA_SLAVE support\n\nUse the DMA_SLAVE capability of the DMAEngine API to copy/from a\nscatterlist into an arbitrary list of hardware address/length pairs.\n\nThis allows a single DMA transaction to copy data from several different\ndevices into a scatterlist at the same time.\n\nThis also adds support to enable some controller-specific features such as\nexternal start and external pause for a DMA transaction.\n\n[dan.j.williams@intel.com: rebased on tx_list movement]\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd", "tree": "73424d223391302a9a16df65378d78f25fd05929", "parents": [ "162b96e63e518aa6ff029ce23de12d7f027483bf" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: split apart external pause and request count features\n\nWhen using the Freescale DMA controller in external control mode, both the\nrequest count and external pause bits need to be setup correctly. This was\nbeing done with the same function.\n\nThe 83xx controller lacks the external pause feature, but has a similar\nfeature called external start. This feature requires that the request count\nbits be setup correctly.\n\nSplit the function into two parts, to make it possible to use the external\nstart feature on the 83xx controller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "162b96e63e518aa6ff029ce23de12d7f027483bf", "tree": "532191d0cef7cf975b70a07b1c69a293d6f552f7", "parents": [ "0803172778901e24a75ab074798d98c2b7411559" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "ioat2,3: cacheline align software descriptor allocations\n\nAll the necessary fields for handling an ioat2,3 ring entry can fit into\none cacheline. Move -\u003elen prior to -\u003etxd in struct ioat_ring_ent, and\nmove allocation of these entries to a hw-cache-aligned kmem cache to\nreduce the number of cachelines dirtied for descriptor management.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0803172778901e24a75ab074798d98c2b7411559", "tree": "a3e1d0cf4228d65dc1fac2ad56f3beb6b6f3474b", "parents": [ "1979b186b80449ac6574d97c254b694c8a99b703" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "dmaengine: kill tx_list\n\nThe tx_list attribute of struct dma_async_tx_descriptor is common to\nmost, but not all dma driver implementations. None of the upper level\ncode (dmaengine/async_tx) uses it, so allow drivers to implement it\nlocally if they need it. This saves sizeof(struct list_head) bytes for\ndrivers that do not manage descriptors with a linked list (e.g.: ioatdma\nv2,3).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "1979b186b80449ac6574d97c254b694c8a99b703", "tree": "9befdf33c11c0b0e4ce6720c7c81efeb7005ce7c", "parents": [ "285a3c71640ad7101b7237b8fbaa4ead22c6551c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "txx9dmac: implement a private tx_list\n\nDrop txx9dmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "285a3c71640ad7101b7237b8fbaa4ead22c6551c", "tree": "d4da48d227f2bc069cb3c1074c6267b5e29426e1", "parents": [ "64203b67274680e95e0c2eec935a22fc94e9ecb5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "at_hdmac: implement a private tx_list\n\nDrop at_hdmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "64203b67274680e95e0c2eec935a22fc94e9ecb5", "tree": "93d56edbf3ecccdd0cffae3a20c3a7b7dd17cd5a", "parents": [ "ea25968a32a621b02c3715d6b649f0c6ef53c24e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "mv_xor: implement a private tx_list\n\nDrop mv_xor\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ea25968a32a621b02c3715d6b649f0c6ef53c24e", "tree": "8da75c38c0ac0690eb03e89ccf146d062ba4d855", "parents": [ "308136d1abcb2d759bac40ed4f5d42ac4af59d8b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "ioat: implement a private tx_list\n\nDrop ioatdma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "308136d1abcb2d759bac40ed4f5d42ac4af59d8b", "tree": "c0cf21c5144929332a5f99d1aff8393e6cddcbbb", "parents": [ "eda34234578fd822c950fd06b5c5ff7ac08b3001" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "iop-adma: implement a private tx_list\n \nDrop iop-adma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "eda34234578fd822c950fd06b5c5ff7ac08b3001", "tree": "860b3c9d347ddd57e6884f9f1e019370de4d45b1", "parents": [ "e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "fsldma: implement a private tx_list\n\nDrop fsldma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c", "tree": "664db6534e1654e98142ae01dab0aa223196d3d7", "parents": [ "e12c4fa377ffda2490476caae17f24daaf9c9bd7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "dw_dmac: implement a private tx_list\n\nDrop dw_dmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "e12c4fa377ffda2490476caae17f24daaf9c9bd7", "tree": "aa7a19d8f7f931709a8a835a4b0d441f83d759fd", "parents": [ "a348a7e6fdbcd2d5192a09719a479bb238fde727", "4b652f0db3be891c7b76b109c3b55003b920fc96" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:52:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:52:57 2009 -0700" }, "message": "Merge branch \u0027ioat\u0027 into dmaengine\n" }, { "commit": "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c", "tree": "b8aa7273a874904396c79099facd104eeb4074e0", "parents": [ "6506cbca6b5b36d682bd39afcbf3f575c81dddb6" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "message": "I/OAT: Convert to PCI_VDEVICE()\n\nTrivial cleanup to make the PCI ID table easier to read.\n\n[dan.j.williams@intel.com: extended to v3.2 devices]\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6506cbca6b5b36d682bd39afcbf3f575c81dddb6", "tree": "ea82de689e7712eaa76209afcaf9a8678dac9f3f", "parents": [ "e3232714d465c42ac631929b990f5e35e2d8a955" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "message": "Add MODULE_DEVICE_TABLE() so ioatdma module is autoloaded\n\nThe ioatdma module is missing aliases for the PCI devices it supports,\nso it is not autoloaded on boot. Add a MODULE_DEVICE_TABLE() to get\nthese aliases.\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e3232714d465c42ac631929b990f5e35e2d8a955", "tree": "f6b9fe66bd11cdae420f558bebf7e8d4b89b52b4", "parents": [ "b265b11fc1a0bd6ae5a7fde12e374583a52ab326" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:02 2009 -0700" }, "message": "ioat3: segregate raid engines\n\nThe cleanup routine for the raid cases imposes extra checks for handling\nraid descriptors and extended descriptors. If the channel does not\nsupport raid it can avoid this extra overhead by using the ioat2 cleanup\npath.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b265b11fc1a0bd6ae5a7fde12e374583a52ab326", "tree": "8a864413b52e06f11f7f0299cdefd398999e82fb", "parents": [ "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e" ], "author": { "name": "Tom Picard", "email": "tom.s.picard@intel.com", "time": "Tue Sep 08 17:43:01 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:01 2009 -0700" }, "message": "ioat3: ioat3.2 pci ids for Jasper Forest\n\nJasper Forest introduces raid offload support via ioat3.2 support. When\nraid offload is enabled two (out of 8 channels) will report raid5/raid6\noffload capabilities. The remaining channels will only report ioat3.0\ncapabilities (memcpy).\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e", "tree": "edb87012a3e42a7bbaa26a1172442da6ea389632", "parents": [ "ae786624c27411c1d38823f640b39f3d97412d5a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "message": "ioat3: interrupt descriptor support\n\nThe async_tx api uses the DMA_INTERRUPT operation type to terminate a\nchain of issued operations with a callback routine.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ae786624c27411c1d38823f640b39f3d97412d5a", "tree": "87ca33dae521c2c5622ea67dde97611e77d77df8", "parents": [ "d69d235b7da2778891640ee95efcd68075978904" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "message": "ioat3: support xor via pq descriptors\n\nIf a platform advertises pq capabilities, but not xor, then use\nioat3_prep_pqxor and ioat3_prep_pqxor_val to simulate xor support.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d69d235b7da2778891640ee95efcd68075978904", "tree": "e7f22d38d8a742ddbca167af123f4987ada8926c", "parents": [ "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:59 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:59 2009 -0700" }, "message": "ioat3: pq support\n\nioat3.2 adds support for raid6 syndrome generation (xor sum of galois\nfield multiplication products) using up to 8 sources. It can also\nperform an pq-zero-sum operation to validate whether the syndrome for a\ngiven set of sources matches a previously computed syndrome.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952", "tree": "55cb18ecfae85033d61f730b5f32d2ac1fb572bc", "parents": [ "b094ad3be564e7cc59cca4ff0256550d3a55dd3b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:58 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:58 2009 -0700" }, "message": "ioat3: xor self test\n\nThis adds a hardware specific self test to be called from ioat_probe.\nIn the ioat3 case we will have tests for all the different raid\noperations, while ioat1 and ioat2 will continue to just test memcpy.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b094ad3be564e7cc59cca4ff0256550d3a55dd3b", "tree": "d69f515b2ee6af2b0f12bb3028d7c7f5b3390794", "parents": [ "e61dacaeb3918cd00cd642e8fb0828324ac59819" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "message": "ioat3: xor support\n\nioat3.2 adds xor offload support for up to 8 sources. It can also\nperform an xor-zero-sum operation to validate whether all given sources\nsum to zero, without writing to a destination. Xor descriptors differ\nfrom memcpy in that one operation may require multiple descriptors\ndepending on the number of sources. When the number of sources exceeds\n5 an extended descriptor is needed. These descriptors need to be\naccounted for when updating the DMA_COUNT register.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e61dacaeb3918cd00cd642e8fb0828324ac59819", "tree": "70c4acf1cf33502bdca8da16bd88c0daab2bbc29", "parents": [ "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "message": "ioat3: enable dca for completion writes\n\nTag completion writes for direct cache access to reduce the latency of\nchecking for descriptor completions.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2", "tree": "3ef3f6724e7a812ba83b420c3915c4a46762aeb7", "parents": [ "bf40a6869c9198bdf56fe173961feb89e9f0d961" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:56 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:56 2009 -0700" }, "message": "ioat: add \u0027ioat\u0027 sysfs attributes\n\nExport driver attributes for diagnostic purposes:\n\u0027ring_size\u0027: total number of descriptors available to the engine\n\u0027ring_active\u0027: number of descriptors in-flight\n\u0027capabilities\u0027: supported operation types for this channel\n\u0027version\u0027: Intel(R) QuickData specfication revision\n\nThis also allows some chattiness to be removed from the driver startup\nas this information is now available via sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bf40a6869c9198bdf56fe173961feb89e9f0d961", "tree": "3d1b6bf44647857997113fe1b036fb46e360d8a7", "parents": [ "2aec048cdc4a5a81163a42a61df903f76a27e737" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:55 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:55 2009 -0700" }, "message": "ioat3: split ioat3 support to its own file, add memset\n\nUp until this point the driver for Intel(R) QuickData Technology\nengines, specification versions 2 and 3, were mostly identical save for\na few quirks. Version 3.2 hardware adds many new capabilities (like\nraid offload support) requiring some infrastructure that is not relevant\nfor v2. For better code organization of the new funcionality move v3\nand v3.2 support to its own file dma_v3.c, and export some routines from\nthe base files (dma.c and dma_v2.c) that can be reused directly.\n\nThe first new capability included in this code reorganization is support\nfor v3.2 memset operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "2aec048cdc4a5a81163a42a61df903f76a27e737", "tree": "00347decc9b145f4c805c8475b980d2641b8ec11", "parents": [ "128f2d567f906d38b11d993d8d97b9b988848e26" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:54 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:54 2009 -0700" }, "message": "ioat3: hardware version 3.2 register / descriptor definitions\n\nioat3.2 adds raid5 and raid6 offload capabilities.\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "128f2d567f906d38b11d993d8d97b9b988848e26", "tree": "523fd4b737bd44bccddb2425ae0b16f78a819e19", "parents": [ "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "ioat2+: add fence support\n\nIn preparation for adding more operation types to the ioat3 path the\ndriver needs to honor the DMA_PREP_FENCE flag. For example the async_tx api\nwill hand xor-\u003ememcpy-\u003exor chains to the driver with the \u0027fence\u0027 flag set on\nthe first xor and the memcpy operation. This flag in turn sets the \u0027fence\u0027\nflag in the descriptor control field telling the hardware that future\ndescriptors in the chain depend on the result of the current descriptor, so\nwait for all writes to complete before starting the next operation.\n\nNote that ioat1 does not prefetch the descriptor chain, so does not\nrequire/support fenced operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7", "tree": "bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce", "parents": [ "9308add6ea4fedeba37b0d7c4630a542bd34f214" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "dmaengine, async_tx: support alignment checks\n\nSome engines have transfer size and address alignment restrictions. Add\na per-operation alignment property to struct dma_device that the async\nroutines and dmatest can use to check alignment capabilities.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9308add6ea4fedeba37b0d7c4630a542bd34f214", "tree": "5b94b9c8eebc7a7ef6879a7fdfc553c6758312dc", "parents": [ "138f4c359d23d2ec38d18bd70dd9613ae515fe93" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "message": "dmaengine: cleanup unused transaction types\n\nNo drivers currently implement these operation types, so they can be\ndeleted.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "138f4c359d23d2ec38d18bd70dd9613ae515fe93", "tree": "ad7fafba6eac74d9d92ade839a65171466d67a70", "parents": [ "0403e3827788d878163f9ef0541b748b0f88ca5d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "message": "dmaengine, async_tx: add a \"no channel switch\" allocator\n\nChannel switching is problematic for some dmaengine drivers as the\narchitecture precludes separating the -\u003eprep from -\u003esubmit. In these\ncases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify\nthe async_tx allocator to only return channels that support all of the\nrequired asynchronous operations.\n\nFor example MD_RAID456\u003dy selects support for asynchronous xor, xor\nvalidate, pq, pq validate, and memcpy. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dy any channel with all these\ncapabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to\nquickly locate compatible channels with the guarantee that dependency\nchains will remain on one channel. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dn async_tx_find_channel() may select\nchannels that lead to operation chains that need to cross channel\nboundaries using the async_tx channel switch capability.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0403e3827788d878163f9ef0541b748b0f88ca5d", "tree": "2dc73744bd92c268a1310f24668167f130877278", "parents": [ "f9dd2134374c8de6b911e2b8652c6c9622eaa658" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:50 2009 -0700" }, "message": "dmaengine: add fence support\n\nSome engines optimize operation by reading ahead in the descriptor chain\nsuch that descriptor2 may start execution before descriptor1 completes.\nIf descriptor2 depends on the result from descriptor1 then a fence is\nrequired (on descriptor2) to disable this optimization. The async_tx\napi could implicitly identify dependencies via the \u0027depend_tx\u0027\nparameter, but that would constrain cases where the dependency chain\nonly specifies a completion order rather than a data dependency. So,\nprovide an ASYNC_TX_FENCE to explicitly identify data dependencies.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f9dd2134374c8de6b911e2b8652c6c9622eaa658", "tree": "c1b8f8d622941606b9e7247ab31d811ba4295011", "parents": [ "4b652f0db3be891c7b76b109c3b55003b920fc96", "07a3b417dc3d00802bd7b4874c3e811f0b015a7d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "message": "Merge branch \u0027md-raid6-accel\u0027 into ioat3.2\n\nConflicts:\n\tinclude/linux/dmaengine.h\n" }, { "commit": "4b652f0db3be891c7b76b109c3b55003b920fc96", "tree": "a7747543a2076a2f58f423297e0da78b2963a04d", "parents": [ "a309218acee8606f7e235da20cc826eb06d9b0f6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:02:15 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:38:54 2009 -0700" }, "message": "net_dma: poll for a descriptor after allocation failure\n\nHandle descriptor allocation failures by polling for a descriptor. The\ndriver will force forward progress when polled. In the best case this\npolling interval will be the time it takes for one dma memcpy\ntransaction to complete. In the worst case, channel hang, we will need\nto wait 100ms for the cleanup watchdog to fire (ioatdma driver).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a309218acee8606f7e235da20cc826eb06d9b0f6", "tree": "abf2cc9830b6a5a52a165e6a736e85cd5d7b36c0", "parents": [ "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:02:01 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:38:54 2009 -0700" }, "message": "ioat2,3: dynamically resize descriptor ring\n\nIncrement the allocation order of the descriptor ring every time we run\nout of descriptors up to a maximum of allocation order specified by the\nmodule parameter \u0027ioat_max_alloc_order\u0027. After each idle period\ndecrement the allocation order to a minimum order of\n\u0027ioat_ring_alloc_order\u0027 (i.e. the default ring size, tunable as a module\nparameter).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd", "tree": "9bb255d9f596ab062996de49032875e8b9253971", "parents": [ "ad643f54c8514998333bc6c7b201fda2267496be" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:49 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: switch watchdog and reset handler from workqueue to timer\n\nIn order to support dynamic resizing of the descriptor ring or polling\nfor a descriptor in the presence of a hung channel the reset handler\nneeds to make progress while in a non-preemptible context. The current\nworkqueue implementation precludes polling channel reset completion\nunder spin_lock().\n\nThis conversion also allows us to return to opportunistic cleanup in the\nioat2 case as the timer implementation guarantees at least one cleanup\nafter every descriptor is submitted. This means the worst case\ncompletion latency becomes the timer frequency (for exceptional\ncircumstances), but with the benefit of avoiding busy waiting when the\nlock is contended.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ad643f54c8514998333bc6c7b201fda2267496be", "tree": "c92bbecd74912ada08dfa94662b52e63d4c5df46", "parents": [ "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:38 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat1: trim ioat_dma_desc_sw\n\nSave 4 bytes per software descriptor by transmitting tx_cnt in an unused\nportion of the hardware descriptor.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52", "tree": "a029ab0c4e66a6ea7c7a7b76c06bcffe92fab5e8", "parents": [ "f6ab95b55735fa03cad8d0f966647e5df206e207" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:30 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: ___devinit annotate the initialization paths\n\nMark all single use initialization routines with __devinit.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f6ab95b55735fa03cad8d0f966647e5df206e207", "tree": "958127a8b5e171d53d26cd1a40d128e34bf8c7b1", "parents": [ "bb3207863014c7310593146f11fbc6573eab43c8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: preserve chanctrl bits when re-arming interrupts\n\nThe register write in ioat_dma_cleanup_tasklet is unfortunate in two\nways:\n1/ It clears the extra \u0027enable\u0027 bits that we set at alloc_chan_resources time\n2/ It gives the impression that it disables interrupts when it is in\n fact re-arming interrupts\n\n[ Impact: fix, persist the value of the chanctrl register when re-arming ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bb3207863014c7310593146f11fbc6573eab43c8", "tree": "d54da64e459d28969cdd9250cadaaa581cbae43d", "parents": [ "4fb9b9e8d55880523db550043dfb204696dd0422" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: ignore reserved bits for chancnt and xfercap\n\nDon\u0027t trust that the reserved bits are always zero, also sanity check\nthe returned value.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4fb9b9e8d55880523db550043dfb204696dd0422", "tree": "733a672aeb819bb8133b16329a6b5088cf9ee693", "parents": [ "6df9183a153291a2585a8dfe67597fc18c201147" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: cleanup completion status reads\n\nThe cleanup path makes an effort to only perform an atomic read of the\n64-bit completion address. However in the 32-bit case it does not\nmatter if we read the upper-32 and lower-32 non-atomically because the\nupper-32 will always be zero.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6df9183a153291a2585a8dfe67597fc18c201147", "tree": "5e5f3b3da9308e20f2dda71c85242460bb7cacfa", "parents": [ "38e12f64a165e83617c21dae3c15972fd8d639f5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:00:55 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:23 2009 -0700" }, "message": "ioat: add some dev_dbg() calls\n\nProvide some output for debugging the driver.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "38e12f64a165e83617c21dae3c15972fd8d639f5", "tree": "43f0951cf0b91b0d831a469d0147c1c4cdd15dfa", "parents": [ "5cbafa65b92ee4f5b8ba915cddf94b91f186b989" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:00:46 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:23 2009 -0700" }, "message": "ioat1: kill unused unmap parameters\n\nThe unified ioat1/ioat2 ioat_dma_unmap() implementation derives the\nsource and dest addresses from the unmap descriptor. There is no longer\na need to track this information in struct ioat_desc_sw.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5cbafa65b92ee4f5b8ba915cddf94b91f186b989", "tree": "f074c9dbcdedf05c5567a4e456a15120895363a6", "parents": [ "dcbc853af6f0c056088e4df0794d9bf36184809e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 26 13:01:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat2,3: convert to a true ring buffer\n\nReplace the current linked list munged into a ring with a native ring\nbuffer implementation. The benefit of this approach is reduced overhead\nas many parameters can be derived from ring position with simple pointer\ncomparisons and descriptor allocation/freeing becomes just a\nmanipulation of head/tail pointers.\n\nIt requires a contiguous allocation for the software descriptor\ninformation.\n\nSince this arrangement is significantly different from the ioat1 chain,\nmove ioat2,3 support into its own file and header. Common routines are\nexported from driver/dma/ioat/dma.[ch].\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "dcbc853af6f0c056088e4df0794d9bf36184809e", "tree": "1cbab40167487cff6dc8984a00756cfc39dff3f3", "parents": [ "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: prepare the code for ioat[12]_dma_chan split\n\nPrepare the code for the conversion of the ioat2 linked-list-ring into a\nnative ring buffer. After this conversion ioat2 channels will share\nless of the ioat1 infrastructure, but there will still be places where\nsharing is possible. struct ioat_chan_common is created to house the\nchannel attributes that will remain common between ioat1 and ioat2\nchannels.\n\nFor every routine that accesses both common and hardware specific fields\nthe old unified \u0027ioat_chan\u0027 pointer is split into an \u0027ioat\u0027 and \u0027chan\u0027\npointer. Where \u0027chan\u0027 references common fields and \u0027ioat\u0027 the\nhardware/version specific.\n\n[ Impact: pure structure member movement/variable renames, no logic changes ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc", "tree": "1f6e4bf5e5ab831ce9cb6de645a1f03545c8cf0a", "parents": [ "a0587bcf3e64029a4da2a5666cad18df38db0d56" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:05 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: fix self test interrupts\n\nIf a callback is to be attached to a descriptor the channel needs to\nknow at -\u003eprep time so it can set the interrupt enable bit. This is in\npreparation for moving descriptor ioat2 descriptor preparation from\n-\u003esubmit to -\u003eprep.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "a0587bcf3e64029a4da2a5666cad18df38db0d56", "tree": "475b3a2a7cd102f40d7c16fed431c227576c255a", "parents": [ "c7984f4e4e3af3bf8027d636283ea8658c7f80b9" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat1: move descriptor allocation from submit to prep\n\nThe async_tx api assumes that after a successful -\u003eprep a subsequent\n-\u003esubmit will not fail due to a lack of resources.\n\nThis also fixes a bug in the allocation failure case. Previously the\ndescriptors allocated prior to the allocation failure would not be\nreturned to the free list.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "c7984f4e4e3af3bf8027d636283ea8658c7f80b9", "tree": "81fb1adc44173505d447aa93142cc96a4bf03044", "parents": [ "77867fff033ea549096c49d863c564ad7d8be36f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: define descriptor control bit-field\n\nThis cleans up a mess of and\u0027ing and or\u0027ing bit definitions, and allows\nsimple assignments from the specified dma_ctrl_flags parameter.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "77867fff033ea549096c49d863c564ad7d8be36f", "tree": "d39bce48f29aa9ce6f23f15e73fab8333d91bc75", "parents": [ "f2427e276ffec5ce599c6bc116e0927269a360ef" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: fix type mismatch for -\u003edmacount\n\n-\u003edmacount tracks the sequence number of active descriptors. It is\nwritten to the DMACOUNT register to update the channel\u0027s view of pending\ndescriptors in the chain. The register is 16-bits so -\u003edmacount should\nbe unsigned and 16-bit as well. Also modify -\u003edesccount to maintain\nalignment.\n\nThis was never a problem in practice because we never compared dmacount\nvalues, but this is a bug waiting to happen.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "f2427e276ffec5ce599c6bc116e0927269a360ef", "tree": "d23b47ad7a00daeba720c25bb900fd96bf226f54", "parents": [ "b31b78f1ab7806759622b703357e39a21f757281" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:42:38 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: split ioat_dma_probe into core/version-specific routines\n\nTowards the removal of ioatdma_device.version split the initialization\npath into distinct versions. This conversion:\n1/ moves version specific probe code to version specific routines\n2/ removes the need for ioat_device\n3/ turns off the ioat1 msi quirk if the device is reinitialized for intx\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "b31b78f1ab7806759622b703357e39a21f757281", "tree": "70144a699561184ed9d7bcd0b0f8f2b102204947", "parents": [ "bc3c70258526a635325f1f15138a96297879bc1a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:42:32 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: kill function prototype ifdef guards\n\nThe only .c files that utilize these protected prototypes depend on\nCONFIG_INTEL_IOATDMA\u003dy, so there is no value gained in providing empty\nprototypes.\n\n[ Impact: pure cleanup ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "bc3c70258526a635325f1f15138a96297879bc1a", "tree": "65ced583f975cb19dc12f498f7e97536033fe74f", "parents": [ "e6c0b69a43150c1a37cf342ce5faedf12583bf79" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:33:42 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: cleanup some long deref chains and 80 column collisions\n\n* reduce device-\u003ecommon. to dma-\u003e in ioat_dma_{probe,remove,selftest}\n* ioat_lookup_chan_by_index to ioat_chan_by_index\n* multi-line function definitions\n* ioat_desc_sw.async_tx to ioat_desc_sw.txd\n* desc-\u003etxd. to tx-\u003e in cleanup routine\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "e6c0b69a43150c1a37cf342ce5faedf12583bf79", "tree": "955456982fea62d6557ad5992f19ee3e73e64bc2", "parents": [ "1f27adc2f050836c12deb4d99afe507636537a0b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:44 2009 -0700" }, "message": "ioat: convert ioat_probe to pcim/devm\n\nThe driver currently duplicates much of what these routines offer, so\njust use the common code. For example -\u003eirq_mode tracks what interrupt\nmode was initialized, which duplicates the -\u003emsix_enabled and\n-\u003emsi_enabled handling in pcim_release.\n\nThis also adds a check to the return value of dma_async_device_register,\nwhich can fail.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "1f27adc2f050836c12deb4d99afe507636537a0b", "tree": "aeb0b1a0896dd1367174a46d29c7ebc18187a4f9", "parents": [ "584ec22759c06cdfc189c03a727f20038526245b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:02 2009 -0700" }, "message": "ioat: move definitions to dma.h\n\nSome of these defines may be useful outside of dma.c and the header is\nprivate so there are no namespace pollution concerns.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "a348a7e6fdbcd2d5192a09719a479bb238fde727", "tree": "5ff94185f4e5a810777469d7fe7832a8ec2d3430", "parents": [ "808347f6a31792079e345ec865e9cfcb6e8ae6b2", "28d0325ce6e0a52f53d8af687e6427fee59004d3" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 14:32:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 14:32:24 2009 -0700" }, "message": "Merge commit \u0027v2.6.31-rc1\u0027 into dmaengine\n" }, { "commit": "07a3b417dc3d00802bd7b4874c3e811f0b015a7d", "tree": "b3b484067f700a70f3e7d575bad6e7e4ae2742cc", "parents": [ "b774ef491b4edf6876077014ecbb87f10c69c10f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:13 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:13 2009 -0700" }, "message": "md/raid456: distribute raid processing over multiple cores\n\nNow that the resources to handle stripe_head operations are allocated\npercpu it is possible for raid5d to distribute stripe handling over\nmultiple cores. This conversion also adds a call to cond_resched() in\nthe non-multicore case to prevent one core from getting monopolized for\nraid operations.\n\nCc: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b774ef491b4edf6876077014ecbb87f10c69c10f", "tree": "a4132f50e29b43c0b23e478001220b3e90ea4731", "parents": [ "6c0069c0ae9659e3a91b68eaed06a5c6c37f45c8" ], "author": { "name": "Yuri Tikhonov", "email": "yur@emcraft.com", "time": "Sat Aug 29 19:13:13 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:13 2009 -0700" }, "message": "md/raid6: remove synchronous infrastructure\n\nThese routines have been replaced by there asynchronous counterparts.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "6c0069c0ae9659e3a91b68eaed06a5c6c37f45c8", "tree": "97b01fc8602e7b6d4c495d0f0562ae901d78f58b", "parents": [ "d82dfee0ad8f240fef1b28e2258891c07da57367" ], "author": { "name": "Yuri Tikhonov", "email": "yur@emcraft.com", "time": "Sat Aug 29 19:13:13 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:13 2009 -0700" }, "message": "md/raid6: asynchronous handle_stripe6\n\n1/ Use STRIPE_OP_BIOFILL to offload completion of read requests to\n raid_run_ops\n2/ Implement a handler for sh-\u003ereconstruct_state similar to the raid5 case\n (adds handling of Q parity)\n3/ Prevent handle_parity_checks6 from running concurrently with \u0027compute\u0027\n operations\n4/ Hook up raid_run_ops\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "d82dfee0ad8f240fef1b28e2258891c07da57367", "tree": "44431399bef701c52f413c364f80751c18ff1179", "parents": [ "a9b39a741a7e3b262b9f51fefb68e17b32756999" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 13:40:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:13 2009 -0700" }, "message": "md/raid6: asynchronous handle_parity_check6\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nImplement the state machine for handling the RAID-6 parities check and\nrepair functionality. Note that the raid6 case does not need to check\nfor new failures, like raid5, as it will always writeback the correct\ndisks. The raid5 case can be updated to check zero_sum_result to avoid\ngetting confused by new failures rather than retrying the entire check\noperation.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "a9b39a741a7e3b262b9f51fefb68e17b32756999", "tree": "659f32a0377ff241627eedb60816bda283e2233f", "parents": [ "5599becca4bee7badf605e41fd5bcde76d51f2a4" ], "author": { "name": "Yuri Tikhonov", "email": "yur@emcraft.com", "time": "Sat Aug 29 19:13:12 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:12 2009 -0700" }, "message": "md/raid6: asynchronous handle_stripe_dirtying6\n\nIn the synchronous implementation of stripe dirtying we processed a\ndegraded stripe with one call to handle_stripe_dirtying6(). I.e.\ncompute the missing blocks from the other drives, then copy in the new\ndata and reconstruct the parities.\n\nIn the asynchronous case we do not perform stripe operations directly.\nInstead, operations are scheduled with flags to be later serviced by\nraid_run_ops. So, for the degraded case the final reconstruction step\ncan only be carried out after all blocks have been brought up to date by\nbeing read, or computed. Like the raid5 case schedule_reconstruction()\nsets STRIPE_OP_RECONSTRUCT to request a parity generation pass and\nthrough operation chaining can handle compute and reconstruct in a\nsingle raid_run_ops pass.\n\n[dan.j.williams@intel.com: fixup handle_stripe_dirtying6 gating]\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "5599becca4bee7badf605e41fd5bcde76d51f2a4", "tree": "c2d231dfb073dc19bd9ac7cdbac20e07280b9fb0", "parents": [ "c0f7bddbe60f43578dccf4ffb8d4bff88f625ea7" ], "author": { "name": "Yuri Tikhonov", "email": "yur@emcraft.com", "time": "Sat Aug 29 19:13:12 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:12 2009 -0700" }, "message": "md/raid6: asynchronous handle_stripe_fill6\n\nModify handle_stripe_fill6 to work asynchronously by introducing\nfetch_block6 as the raid6 analog of fetch_block5 (schedule compute\noperations for missing/out-of-sync disks).\n\n[dan.j.williams@intel.com: compute D+Q in one pass]\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "c0f7bddbe60f43578dccf4ffb8d4bff88f625ea7", "tree": "4100908f0a90821b6b1e42b725f25d279525799f", "parents": [ "ac6b53b6e6acab27e4f3e2383f9ac1f0d7c6200b" ], "author": { "name": "Yuri Tikhonov", "email": "yur@emcraft.com", "time": "Sat Aug 29 19:13:12 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:12 2009 -0700" }, "message": "md/raid5,6: common schedule_reconstruction for raid5/6\n\nExtend schedule_reconstruction5 for reuse by the raid6 path. Add\nsupport for generating Q and BUG() if a request is made to perform\n\u0027prexor\u0027.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ac6b53b6e6acab27e4f3e2383f9ac1f0d7c6200b", "tree": "e9c67502fd32a9eea4902ea382e51eecb09f2a54", "parents": [ "4e7d2c0aefb77f7b24942e5af042a083be4d60bb" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 13:40:19 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:12 2009 -0700" }, "message": "md/raid6: asynchronous raid6 operations\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nThe raid_run_ops routine uses the asynchronous offload api and\nthe stripe_operations member of a stripe_head to carry out xor+pq+copy\noperations asynchronously, outside the lock.\n\nThe operations performed by RAID-6 are the same as in the RAID-5 case\nexcept for no support of STRIPE_OP_PREXOR operations. All the others\nare supported:\nSTRIPE_OP_BIOFILL\n - copy data into request buffers to satisfy a read request\nSTRIPE_OP_COMPUTE_BLK\n - generate missing blocks (1 or 2) in the cache from the other blocks\nSTRIPE_OP_BIODRAIN\n - copy data out of request buffers to satisfy a write request\nSTRIPE_OP_RECONSTRUCT\n - recalculate parity for new data that has entered the cache\nSTRIPE_OP_CHECK\n - verify that the parity is correct\n\nThe flow is the same as in the RAID-5 case, and reuses some routines, namely:\n1/ ops_complete_postxor (renamed to ops_complete_reconstruct)\n2/ ops_complete_compute (updated to set up to 2 targets uptodate)\n3/ ops_run_check (renamed to ops_run_check_p for xor parity checks)\n\n[neilb@suse.de: fixes to get it to pass mdadm regression suite]\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "4e7d2c0aefb77f7b24942e5af042a083be4d60bb", "tree": "59d127eac9d9c0ff5feea9d741739ccc6fae65c3", "parents": [ "cb3c82992f62f838e6476a0bff12909158007fc6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:11 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:13:11 2009 -0700" }, "message": "md/raid5: factor out mark_uptodate from ops_complete_compute5\n\nops_complete_compute5 can be reused in the raid6 path if it is updated to\ngenerically handle a second target.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "f6dbf651615900646fe0ba1ef5ce1027e5b4748d", "tree": "a78d096174765ce893dddfd6fed9e5e92d45aaaa", "parents": [ "7bf649aee8ac93ecc280f8745dcf8ec19d7b9fb1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:40 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:40 2009 -0700" }, "message": "iop-adma: P+Q self test\n\nEven though the intent is to extend dmatest with P+Q tests there is\nstill value in having an always-on sanity check to prevent an\nunintentionally broken driver from registering.\n\nThis depends on raid6_pq.ko for verification, the side effect being that\nPQ capable channels will fail to register when raid6 is disabled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "7bf649aee8ac93ecc280f8745dcf8ec19d7b9fb1", "tree": "b35282323d278afb16c18a42c8c0db34508cef6c", "parents": [ "72be12f0c39df46832403cbfd82e132a883f5ddc" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Aug 28 14:32:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "message": "iop-adma: P+Q support for iop13xx adma engines\n\niop33x support is not included because that engine is a bit more awkward\nto handle in that it can either be in xor mode or pq mode. The\ndmaengine/async_tx layers currently only comprehend static capabilities.\n\nNote iop13xx does not support hardware PQ continuation so the driver\nmust handle the DMA_PREP_CONTINUE flag for operations across \u003e 16\nsources. From the comment for dma_maxpq:\n\n/* When an engine does not support native continuation we need 3 extra\n * source slots to reuse P and Q with the following coefficients:\n * 1/ {00} * P : remove P from Q\u0027, but use it as a source for P\u0027\n * 2/ {01} * Q : use Q to continue Q\u0027 calculation\n * 3/ {00} * Q : subtract Q from P\u0027 to cancel (2)\n */\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n\n\n" }, { "commit": "72be12f0c39df46832403cbfd82e132a883f5ddc", "tree": "61a4014d28852692464aca3f509d2024e7006f68", "parents": [ "507fbec4cff442ebce6706db34603bfb9cc3b5a9" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 13:38:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "message": "iop-adma: fix lockdep false positive\n\nlockdep correctly identifies a potential recursive locking case for\niop_chan-\u003elock, but in the dependency submission case we expect that the same\nclass will be acquired for both the parent dependency and the child channel.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "507fbec4cff442ebce6706db34603bfb9cc3b5a9", "tree": "781901167ab7d2ed2f064d9a0e6faa2e87148165", "parents": [ "cb3c82992f62f838e6476a0bff12909158007fc6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:12:39 2009 -0700" }, "message": "iop-adma: cleanup iop_adma_run_tx_complete_actions\n\nReplace \u0027desc-\u003easync_tx.\u0027 with \u0027tx-\u003e\u0027\n\n[ Impact: pure cleanup ]\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "cb3c82992f62f838e6476a0bff12909158007fc6", "tree": "d6ced15a81340b9b8343c369fea22940f31f06eb", "parents": [ "58691d64c44ae41ddf098ecb31e9a994026e3cff" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:28 2009 -0700" }, "message": "async_tx: raid6 recovery self test\n\nPort drivers/md/raid6test/test.c to use the async raid6 recovery\nroutines. This is meant as a unit test for raid6 acceleration drivers. In\naddition to the 16-drive test case this implements tests for the 4-disk and\n5-disk special cases (dma devices can not generically handle less than 2\nsources), and adds a test for the D+Q case.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "58691d64c44ae41ddf098ecb31e9a994026e3cff", "tree": "93c36b2d244648a9b5880dc97de3cb945fdebda7", "parents": [ "0a82a6239beecc95db6e05fe43ee62d16b381d38" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "dmatest: add pq support\n\nTest raid6 p+q operations with a simple \"always multiply by 1\" q\ncalculation to fit into dmatest\u0027s current destination verification\nscheme.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "0a82a6239beecc95db6e05fe43ee62d16b381d38", "tree": "524f6417ae8128f5b1da322872e860bd4af5840d", "parents": [ "b2f46fd8ef3dff2ab30f31126833f78b7480283a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: add support for asynchronous RAID6 recovery operations\n\n async_raid6_2data_recov() recovers two data disk failures\n\n async_raid6_datap_recov() recovers a data disk and the P disk\n\nThese routines are a port of the synchronous versions found in\ndrivers/md/raid6recov.c. The primary difference is breaking out the xor\noperations into separate calls to async_xor. Two helper routines are\nintroduced to perform scalar multiplication where needed.\nasync_sum_product() multiplies two sources by scalar coefficients and\nthen sums (xor) the result. async_mult() simply multiplies a single\nsource by a scalar.\n\nThis implemention also includes, in contrast to the original\nsynchronous-only code, special case handling for the 4-disk and 5-disk\narray cases. In these situations the default N-disk algorithm will\npresent 0-source or 1-source operations to dma devices. To cover for\ndma devices where the minimum source count is 2 we implement 4-disk and\n5-disk handling in the recovery code.\n\n[ Impact: asynchronous raid6 recovery routines for 2data and datap cases ]\n\nCc: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nCc: Ilya Yanok \u003cyanok@emcraft.com\u003e\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "b2f46fd8ef3dff2ab30f31126833f78b7480283a", "tree": "9f111e3e313b4d142c12d2d8156a2704a36904f8", "parents": [ "95475e57113c66aac7583925736ed2e2d58c990d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: add support for asynchronous GF multiplication\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nThis adds support for doing asynchronous GF multiplication by adding\ntwo additional functions to the async_tx API:\n\n async_gen_syndrome() does simultaneous XOR and Galois field\n multiplication of sources.\n\n async_syndrome_val() validates the given source buffers against known P\n and Q values.\n\nWhen a request is made to run async_pq against more than the hardware\nmaximum number of supported sources we need to reuse the previous\ngenerated P and Q values as sources into the next operation. Care must\nbe taken to remove Q from P\u0027 and P from Q\u0027. For example to perform a 5\nsource pq op with hardware that only supports 4 sources at a time the\nfollowing approach is taken:\n\np, q \u003d PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))\np\u0027, q\u0027 \u003d PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))\n\np\u0027 \u003d p + q + q + src4 \u003d p + src4\nq\u0027 \u003d {00}*p + {01}*q + {00}*q + {10}*src4 \u003d q + {10}*src4\n\nNote: 4 is the minimum acceptable maxpq otherwise we punt to\nsynchronous-software path.\n\nThe DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as\nsources (in the above manner) and fill the remaining slots up to maxpq\nwith the new sources/coefficients.\n\nNote1: Some devices have native support for P+Q continuation and can skip\nthis extra work. Devices with this capability can advertise it with\ndma_set_maxpq. It is up to each driver how to handle the\nDMA_PREP_CONTINUE flag.\n\nNote2: The api supports disabling the generation of P when generating Q,\nthis is ignored by the synchronous path but is implemented by some dma\ndevices to save unnecessary writes. In this case the continuation\nalgorithm is simplified to only reuse Q as a source.\n\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "95475e57113c66aac7583925736ed2e2d58c990d", "tree": "933aa0ca3bffef5b1457c516fbe3e8690b4c4cb1", "parents": [ "af1f951eb6ef27b01cbfb3f6c21b770af4368a6d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:19:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: remove walk of tx-\u003eparent chain in dma_wait_for_async_tx\n\nWe currently walk the parent chain when waiting for a given tx to\ncomplete however this walk may race with the driver cleanup routine.\nThe routines in async_raid6_recov.c may fall back to the synchronous\npath at any point so we need to be prepared to call async_tx_quiesce()\n(which calls dma_wait_for_async_tx). To remove the -\u003eparent walk we\nguarantee that every time a dependency is attached -\u003eissue_pending() is\ninvoked, then we can simply poll the initial descriptor until\ncompletion.\n\nThis also allows for a lighter weight \u0027issue pending\u0027 implementation as\nthere is no longer a requirement to iterate through all the channels\u0027\n-\u003eissue_pending() routines as long as operations have been submitted in\nan ordered chain. async_tx_issue_pending() is added for this case.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "af1f951eb6ef27b01cbfb3f6c21b770af4368a6d", "tree": "2009d83f93be62856eebbe9a41310d8ead4a6a13", "parents": [ "ad283ea4a3ce82cda2efe33163748a397b31b1eb" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "message": "async_tx: kill needless module_{init|exit}\n\nIf module_init and module_exit are nops then neither need to be defined.\n\n[ Impact: pure cleanup ]\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ad283ea4a3ce82cda2efe33163748a397b31b1eb", "tree": "11cd739195f336895abe9e4a62d824e49a41c24f", "parents": [ "d6f38f31f3ad4b0dd33fe970988f14e7c65ef702" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "message": "async_tx: add sum check flags\n\nReplace the flat zero_sum_result with a collection of flags to contain\nthe P (xor) zero-sum result, and the soon to be utilized Q (raid6 reed\nsolomon syndrome) zero-sum result. Use the SUM_CHECK_ namespace instead\nof DMA_ since these flags will be used on non-dma-zero-sum enabled\nplatforms.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "d6f38f31f3ad4b0dd33fe970988f14e7c65ef702", "tree": "0b881c68e676376f2f0eccb2eb377dc3561d395f", "parents": [ "36d1c6476be51101778882897b315bd928c8c7b5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 11:50:52 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "message": "md/raid5,6: add percpu scribble region for buffer lists\n\nUse percpu memory rather than stack for storing the buffer lists used in\nparity calculations. Include space for dma address conversions and pass\nthat to async_tx via the async_submit_ctl.scribble pointer.\n\n[ Impact: move memory pressure from stack to heap ]\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "36d1c6476be51101778882897b315bd928c8c7b5", "tree": "55b4ecd93ce9c22722c9c9da0dd28a2d2f7c082d", "parents": [ "a11034b4282515fd7d9f6fdc0a1380781da461c3" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 11:48:22 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "message": "md/raid6: move the spare page to a percpu allocation\n\nIn preparation for asynchronous handling of raid6 operations move the\nspare page to a percpu allocation to allow multiple simultaneous\nsynchronous raid6 recovery operations.\n\nMake this allocation cpu hotplug aware to maximize allocation\nefficiency.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "80ffb3cceaefa405f2ecd46d66500ed8d53efe74", "tree": "867d6ec951663255076ea42fab29a31eac4e51c0", "parents": [ "4d484a4a7a5126410eed5f8dd329a33f6eeed068" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Tue Aug 18 10:35:26 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Tue Aug 18 10:35:26 2009 +1000" }, "message": "Fix new incorrect error return from do_md_stop.\n\nRecent commit c8c00a6915a2e3d10416e8bdd3138429beb96210\nchanged the exit paths in do_md_stop and was not quite\ncareful enough. There is one path were \u0027err\u0027 now needs\nto be cleared but it isn\u0027t.\nSo setting an array to readonly (with mdadm --readonly) will\nwork, but will incorrectly report and error: ENXIO.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "4d484a4a7a5126410eed5f8dd329a33f6eeed068", "tree": "9fe49a23117adc2d475711f39a16c1718bab4b7f", "parents": [ "1a67dde0abba36421a1257d01ba9de2f6d1c160a" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:41:50 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:41:50 2009 +1000" }, "message": "md: allow upper limit for resync/reshape to be set when array is read-only\n\nNormally we only allow the upper limit for a reshape to be decreased\nwhen the array not performing a sync/recovery/reshape, otherwise there\ncould be races. But if an array is part-way through a reshape when it\nis assembled the reshape is started immediately leaving no window\nto set an upper bound.\n\nIf the array is started read-only, the reshape will be suspended until\nthe array becomes writable, so that provides a window during which it\nis perfectly safe to reduce the upper limit of a reshape.\n\nSo: allow the upper limit (sync_max) to be reduced even if the reshape\nthread is running, as long as the array is still read-only.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "1a67dde0abba36421a1257d01ba9de2f6d1c160a", "tree": "c182c31207c46824097be7ce6b8813f05db4eb65", "parents": [ "a639755cf885e437b2fe4168d35157fa90d530ab" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:41:49 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:41:49 2009 +1000" }, "message": "md/raid5: Properly remove excess drives after shrinking a raid5/6\n\nWe were removing the drives, from the array, but not\nremoving symlinks from /sys/.... and not marking the device\nas having been removed.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "a639755cf885e437b2fe4168d35157fa90d530ab", "tree": "01d9a04a1c1c0b16863a51ec389470e436e9fb13", "parents": [ "67ac6011db5d2b0c853d573ff474b25c85dfb644" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:13:00 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:13:00 2009 +1000" }, "message": "md/raid5: make sure a reshape restarts at the correct address.\n\nThis \"if\" don\u0027t allow for the possibility that the number of devices\ndoesn\u0027t change, and so sector_nr isn\u0027t set correctly in that case.\nSo change \u0027\u003e\u0027 to \u0027\u003e\u003d\u0027.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "67ac6011db5d2b0c853d573ff474b25c85dfb644", "tree": "29b30e5e4eac0564c34e0b0b3d655383ba9c783f", "parents": [ "51d5668cb2e3fd1827a55184e48606fff054c5be" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:06:24 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 10:06:24 2009 +1000" }, "message": "md/raid5: allow new reshape modes to be restarted in the middle.\n\nmd/raid5 doesn\u0027t allow a reshape to restart if it involves writing\nover the same part of disk that it would be reading from.\nThis happens at the beginning of a reshape that increases the number\nof devices, at the end of a reshape that decreases the number of\ndevices, and continuously for a reshape that does not change the\nnumber of devices.\n\nThe current code is correct for the \"increase number of devices\"\ncase as the critical section at the start is handled by userspace\nperforming a backup.\n\nIt does not work for reducing the number of devices, or the\nno-change case.\nFor \u0027reducing\u0027, we need to invert the test. For no-change we cannot\nreally be sure things will be safe, so simply require the array\nto be read-only, which is how the user-space code which carefully\nstarts such arrays works.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "51d5668cb2e3fd1827a55184e48606fff054c5be", "tree": "117824cc3a25c04c939856578105c6c93af6ac8b", "parents": [ "c8c00a6915a2e3d10416e8bdd3138429beb96210" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 09:54:02 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Thu Aug 13 09:54:02 2009 +1000" }, "message": "md: never advance \u0027events\u0027 counter by more than 1.\n\nWhen assembling arrays, md allows two devices to have different event\ncounts as long as the difference is only \u00271\u0027. This is to cope with\na system failure between updating the metadata on two difference\ndevices.\n\nHowever there are currently times when we update the event count by\n2. This was done to keep the event count even when the array is clean\nand odd when it is dirty, which allows us to avoid writing common\nupdate to spare devices and so allow those spares to go to sleep.\n\nThis is bad for the above reason. So change it to never increase by\ntwo. This means that the alignment between \u0027odd/even\u0027 and\n\u0027clean/dirty\u0027 might take a little longer to attain, but that is only a\nsmall cost. The spares will get a few more updates but that will\nstill be spared (;-) most updates and can still go to sleep.\n\nPrior to this patch there was a small chance that after a crash an\narray would fail to assemble due to the overly large event count\nmismatch.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "c8c00a6915a2e3d10416e8bdd3138429beb96210", "tree": "ecf06a9e2b08edefe707da450b52a69f818ec7d6", "parents": [ "7b2aa037e878c939676675969983284a02958ae3" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Mon Aug 10 12:50:52 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Mon Aug 10 12:50:52 2009 +1000" }, "message": "Remove deadlock potential in md_open\n\nA recent commit:\n commit 449aad3e25358812c43afc60918c5ad3819488e7\n\nintroduced the possibility of an A-B/B-A deadlock between\nbd_mutex and reconfig_mutex.\n\n__blkdev_get holds bd_mutex while calling md_open which takes\n reconfig_mutex,\ndo_md_run is always called with reconfig_mutex held, and it now\n takes bd_mutex in the call the revalidate_disk.\n\nThis potential deadlock was not caught by lockdep due to the\nuse of mutex_lock_interruptible_nexted which was introduced\nby\n commit d63a5a74dee87883fda6b7d170244acaac5b05e8\ndo avoid a warning of an impossible deadlock.\n\nIt is quite possible to split reconfig_mutex in to two locks.\nOne protects the array data structures while it is being\nreconfigured, the other ensures that an array is never even partially\nopen while it is being deactivated.\nIn particular, the second lock prevents an open from completing\nbetween the time when do_md_stop checks if there are any active opens,\nand the time when the array is either set read-only, or when -\u003epers is\nset to NULL. So we can be certain that no IO is in flight as the\narray is being destroyed.\n\nSo create a new lock, open_mutex, just to ensure exclusion between\n\u0027open\u0027 and \u0027stop\u0027.\n\nThis avoids the deadlock and also avoids the lockdep warning mentioned\nin commit d63a5a74d\n\nReported-by: \"Mike Snitzer\" \u003csnitzer@gmail.com\u003e\nReported-by: \"H. Peter Anvin\" \u003chpa@zytor.com\u003e\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "7b2aa037e878c939676675969983284a02958ae3", "tree": "eb7387b6d26f8f3550d99b1d9b77ebce818e5657", "parents": [ "710ad849ae76bc2f938a885e928b90cdbbe61a6e", "cf7fdd57f978d40ceb9a0f58a25f5cf9c84d6f33" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:06:36 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:06:36 2009 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6:\n USB: fix oops on disconnect in cdc-acm\n USB: storage: include Prolific Technology USB drive in unusual_devs list\n USB: ftdi_sio: add product_id for Marvell OpenRD Base, Client\n USB: ftdi_sio: add vendor and product id for Bayer glucose meter serial converter cable\n USB: EHCI: fix counting of transaction error retries\n USB: EHCI: fix two new bugs related to Clear-TT-Buffer\n USB: usbfs: fix -ENOENT error code to be -ENODEV\n USB: musb: fix the nop registration for OMAP3EVM\n USB: devio: Properly do access_ok() checks\n USB: pl2303: New vendor and product id\n" }, { "commit": "710ad849ae76bc2f938a885e928b90cdbbe61a6e", "tree": "28d53ccd6cf3888453fb7e588f5c62edcc595f69", "parents": [ "b32b8e645ea764620ececc0c9a66a7fc08536d4d", "749d00dbf154fc2f9ac59df669205039de0d5b45" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:06:13 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:06:13 2009 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6:\n Staging: rspiusb: Fix buffer overflow\n staging: add dependencies on PCI for drivers that require it\n Staging: rtl8192su: fix build error\n Staging: rt2870: Revert d44ca7 Removal of kernel_thread() API\n Staging: rt2870: Add USB ID for Linksys, Planex Communications, Belkin\n" }, { "commit": "b32b8e645ea764620ececc0c9a66a7fc08536d4d", "tree": "8ac1b62204b61d4c520bce21845726c58d767221", "parents": [ "d6a0967c90dced0a8baf502e6f3d5862fd5a5805", "819e0064634f580ab618189e657ea58341d214b7" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:03:59 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:03:59 2009 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (22 commits)\n drm/i915: Fix read outside array bounds in restoring the SWF10 range.\n drm/i915: Use our own workqueue to avoid wedging the system along with the GPU.\n drm/i915: Add support for dual-channel LVDS on 8xx.\n drm/i915: Return disconnected for SDVO DVI when there\u0027s no digital EDID.\n drm/i915: Choose real sdvo output according to result from detection\n drm/i915: Set preferred mode for integrated TV according to TV format\n drm/i915: fix 845G FIFO size \u0026 burst length\n drm/i915: fix VGA detect on IGDNG\n drm/i915: Add eDP support on IGDNG mobile chip\n drm/i915: enable DisplayPort support on IGDNG\n drm/i915: Fix channel ending action for DP aux transaction\n drm/i915: fix issue in display pipe setup on IGDNG\n drm/i915: disable VGA plane reliably\n drm/I915: Fix offset to DVO timings in LVDS data\n drm/i915: hdmi detection according by reading edid\n drm/i915: correct self-refresh calculation in \"everything off\" case\n drm/i915: handle FIFO oversubsription correctly\n drm/i915: FIFO watermark calculation fixes\n drm/i915: ignore lvds on AOpen Mini PC MP-915\n drm/i915: Allow frame buffers up to 4096x4096 on 915/945 class hardware\n ...\n" }, { "commit": "d6a0967c90dced0a8baf502e6f3d5862fd5a5805", "tree": "e0242d5077730dabc4102b7abad9ee0c41e33bc0", "parents": [ "fb385003c4ac9634cf2448f6ded81e5fd1190c1f", "ceab36edd3d3ad3ffd01d41d6d1e05ac1ff8357e" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:03:09 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 19:03:09 2009 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable:\n Btrfs: fix balancing oops when invalidate_inode_pages2 returns EBUSY\n Btrfs: correct error-handling zlib error handling\n Btrfs: remove superfluous NULL pointer check in btrfs_rename()\n Btrfs: make sure the async caching thread advances the key\n Btrfs: fix btrfs_remove_from_free_space corner case\n" }, { "commit": "fb385003c4ac9634cf2448f6ded81e5fd1190c1f", "tree": "3a6068559cef144c04b96372ee0eecf20dfb108b", "parents": [ "36b8659f9316b24c514a7c8290596b2382b91dd2", "b36ec0428a06fcbdb67d61e9e664154e5dd9a8c7" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 18:53:44 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 07 18:53:44 2009 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/hch/xfs-icache-races\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/hch/xfs-icache-races:\n xfs: fix freeing of inodes not yet added to the inode cache\n vfs: add __destroy_inode\n vfs: fix inode_init_always calling convention\n" }, { "commit": "749d00dbf154fc2f9ac59df669205039de0d5b45", "tree": "0099ed2a213c0b221e89a22a5b7a9611e11ddf0b", "parents": [ "5fb4d2525b6dcffbb8bc26a7dfc7ed17ad323a06" ], "author": { "name": "Roel Kluin", "email": "roel.kluin@gmail.com", "time": "Fri Aug 07 21:00:10 2009 +0200" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:12:03 2009 -0700" }, "message": "Staging: rspiusb: Fix buffer overflow\n\nusb_buffer_map_sg() may return -1. This will result in a read from\npdx-\u003ePixelUrb[frameInfo][-1]\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "5fb4d2525b6dcffbb8bc26a7dfc7ed17ad323a06", "tree": "1bee1fc6833eceaa1bcb3a4eb743994f4468b9af", "parents": [ "ce9c010c5c39df05ed81a06aba492c45ee0c6f19" ], "author": { "name": "Jeff Mahoney", "email": "jeffm@suse.com", "time": "Fri Aug 07 16:12:03 2009 -0700" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:12:03 2009 -0700" }, "message": "staging: add dependencies on PCI for drivers that require it\n\nThis patch adds PCI dependencies to staging drivers that require it.\n\nSigned-off-by: Jeff Mahoney \u003cjeffm@suse.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "ce9c010c5c39df05ed81a06aba492c45ee0c6f19", "tree": "f35f0cea6f28ec7a7e7f5d58c5ae27d160388e59", "parents": [ "2c63abf9e8a51dec886da482dfd8ae752581a61c" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Tue Aug 04 16:53:36 2009 -0700" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:12:03 2009 -0700" }, "message": "Staging: rtl8192su: fix build error\n\nThis fixes a build error when selecting the rtl8192su driver as a\nmodule. This has been reported by me, and the opensuse kernel developer\nteam, and I finally tracked it down.\n\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n" }, { "commit": "2c63abf9e8a51dec886da482dfd8ae752581a61c", "tree": "05bb3f69ae9cfe205e5f30353237e8089736c3b9", "parents": [ "4d2da07bc876fc5bc455e0721df388a3db7e4ba5" ], "author": { "name": "Mike Galbraith", "email": "efault@gmx.de", "time": "Fri Jul 31 07:14:04 2009 +0200" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:12:02 2009 -0700" }, "message": "Staging: rt2870: Revert d44ca7 Removal of kernel_thread() API\n\nStaging: rt2870: Revert d44ca7 Removal of kernel_thread() API\n\nThe sanity check this patch introduced triggers on shutdown, apparently due to\nthreads having already exited by the time BUG_ON() is reached.\n\nSigned-off-by: Mike Galbraith \u003cefault@gmx.de\u003e\nCc: Peter Teoh \u003chtmldeveloper@gmail.com\u003e\nCc: stable \u003cstable@kernel.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "4d2da07bc876fc5bc455e0721df388a3db7e4ba5", "tree": "6a95188e5931ffd4be626ba1e06f248ff0f4ba25", "parents": [ "36b8659f9316b24c514a7c8290596b2382b91dd2" ], "author": { "name": "Jakob Gruber", "email": "jakob.gruber@kabelnet.at", "time": "Thu Jul 30 20:37:36 2009 +0200" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:12:02 2009 -0700" }, "message": "Staging: rt2870: Add USB ID for Linksys, Planex Communications, Belkin\n\nLinksys WUSB100, Belkin F5D8053 N, Planex Communications unknown model.\n\nSigned-off-by: Jakob Gruber \u003cjakob.gruber@kabelnet.at\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "cf7fdd57f978d40ceb9a0f58a25f5cf9c84d6f33", "tree": "17de519a492c4353dc65111bec683bd4f038a311", "parents": [ "c15e3ca1d822abba78c00b1ffc3e7b382a50396e" ], "author": { "name": "Oliver Neukum", "email": "oliver@neukum.org", "time": "Tue Aug 04 23:52:09 2009 +0200" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:05:14 2009 -0700" }, "message": "USB: fix oops on disconnect in cdc-acm\n\nThis patch fixes an oops caused when during an unplug a device\u0027s table\nof endpoints is zeroed before the driver is notified. A pointer to\nthe endpoint must be cached.\n\nthis fixes a regression caused by commit\n5186ffee2320942c3dc9745f7930e0eb15329ca6\nTherefore it should go into 2.6.31\n\nSigned-off-by: Oliver Neukum \u003coliver@neukum.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "c15e3ca1d822abba78c00b1ffc3e7b382a50396e", "tree": "16d153097046ed53624aad102ddbcbad4e49a534", "parents": [ "50d0678e2026c18e4147f0b16b5853113659b82d" ], "author": { "name": "Rogerio Brito", "email": "rbrito@ime.usp.br", "time": "Thu Aug 06 15:20:19 2009 -0700" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:05:14 2009 -0700" }, "message": "USB: storage: include Prolific Technology USB drive in unusual_devs list\n\nAdd a quirk entry for the Leading Driver UD-11 usb flash drive.\n\nAs Alan Stern told me, the device doesn\u0027t deal correctly with the\nlocking media feature of the device, and this patch incorporates it.\n\nCompiled, tested, working.\n\nSigned-off-by: Rogerio Brito \u003crbrito@ime.usp.br\u003e\nCc: Phil Dibowitz \u003cphil@ipom.com\u003e\nCc: Alan Stern \u003cstern@rowland.harvard.edu\u003e\nCc: Robert Hancock \u003chancockrwd@gmail.com\u003e\nCc: stable \u003cstable@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "50d0678e2026c18e4147f0b16b5853113659b82d", "tree": "0d2039118db833c451c4b0cf57020a50abe7666f", "parents": [ "c47aacc67a3d26dfab9c9b8965975ed2b2010b30" ], "author": { "name": "Dhaval Vasa", "email": "dhaval.vasa@einfochips.com", "time": "Fri Aug 07 17:26:49 2009 +0530" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Fri Aug 07 16:05:13 2009 -0700" }, "message": "USB: ftdi_sio: add product_id for Marvell OpenRD Base, Client\n\nreference:\nhttp://www.open-rd.org\n\nSigned-off-by: Dhaval Vasa \u003cdhaval.vasa@einfochips.com\u003e\nCc: stable \u003cstable@kernel.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" } ], "next": "c47aacc67a3d26dfab9c9b8965975ed2b2010b30" }