)]}'
{
  "log": [
    {
      "commit": "2ab9391dea6e36fed13443c29bf97d3be05f5289",
      "tree": "8bc492fe3df71457caf8009bd081b9be0ec1074a",
      "parents": [
        "f19180056ea09ec6a5d32e741234451a1e6eba4d"
      ],
      "author": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Mar 31 10:28:29 2006 -0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Mar 31 10:28:29 2006 -0800"
      },
      "message": "[IA64] Avoid \"u64 foo : 32;\" for gcc3 vs. gcc4 compatibility\n\ngcc3 thinks that a 32-bit field of a u64 type is itself a u64, so\nshould be printed with \"%ld\".  gcc4 thinks it needs just \"%d\".\nMake both versions happy by avoiding this construct.\n\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "f19180056ea09ec6a5d32e741234451a1e6eba4d",
      "tree": "386a178dd80773e3b62e6989f4faaaddb9602aa8",
      "parents": [
        "d1127e40e8d75cd3855e35424937c73d0bcec558"
      ],
      "author": {
        "name": "Zhang, Yanmin",
        "email": "yanmin_zhang@linux.intel.com",
        "time": "Mon Feb 27 11:37:45 2006 +0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Thu Mar 30 17:14:12 2006 -0800"
      },
      "message": "[IA64] Export cpu cache info by sysfs\n\nThe patch exports 8 attributes of cpu cache info under\n/sys/devices/system/cpu/cpuX/cache/indexX:\n1) level\n2) type\n3) coherency_line_size\n4) ways_of_associativity\n5) size\n6) shared_cpu_map\n7) attributes\n8) number_of_sets: number_of_sets\u003dsize/ways_of_associativity/coherency_line_size.\n\nSigned-off-by: Zhang Yanmin \u003cyanmin.zhang@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "4129a953ad4db379d8e07b0dd2157998653a1325",
      "tree": "84c6d310953044caa420410165adcd0dfb2ac55f",
      "parents": [
        "4d357acadd7a5e60767c748ed7807e11c4387bdf"
      ],
      "author": {
        "name": "Fenghua Yu",
        "email": "fenghua.yu@intel.com",
        "time": "Mon Feb 27 16:16:22 2006 -0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Mar 24 13:15:23 2006 -0800"
      },
      "message": "[IA64] New IA64 core/thread detection patch\n\nIPF SDM 2.2 changes definition of PAL_LOGICAL_TO_PHYSICAL to add\nproc_number\u003d-1 to get core/thread mapping info on the running processer.\n\nBased on this change, we had better to update existing core/thread\ndetection in IA64 kernel correspondingly. The attached patch implements\nthis change. It simplifies detection code and eliminates potential race\ncondition. It also runs a bit faster and has better scalability especially\nwhen cores and threads number grows up in one package.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "f15ac5801fdc1b217c3b8b5dbc63a09371d2ee4d",
      "tree": "b9d4eeb9b5a6ab36fdaebf24263aa4ba5543aec7",
      "parents": [
        "7b9c8ba2d634a0467a8a36018a28624563f34f47"
      ],
      "author": {
        "name": "Xu, Anthony",
        "email": "anthony.xu@intel.com",
        "time": "Mon Jan 09 10:36:35 2006 +0800"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Jan 16 15:44:53 2006 -0800"
      },
      "message": "[IA64] pal cache flush patch\n\nBecause PAL spec has changed since 2002, you can goto\nhttp://developer.intel.com/design/itanium/manuals/iiasdmanual.htm to\ndownload new SDM, all PAL calls should be invoked with psr.ic\u003d1, and\nit\u0027s caller\u0027s responsibility to handle possible tlb miss.\nIa64_pal_cache_flush was written according to old spec, it is obsolete,\nand this patch has ia64_pal_cache_flush conform to new spec.\n\nSigned-off-by Anthony Xu \u003canthony.xu@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "4db8699bcfa8faddb5727b1cb010a4d9b8a42e8c",
      "tree": "eb4cb14927ed9cf4507f875cd69fe35f87b3b3bc",
      "parents": [
        "fd589e0b662c1ea8cfb1e0d20d60a2510979865b"
      ],
      "author": {
        "name": "Venkatesh Pallipadi",
        "email": "venkatesh.pallipadi@intel.com",
        "time": "Fri Jul 29 16:15:00 2005 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Fri Aug 26 15:09:24 2005 -0700"
      },
      "message": "[IA64] Add ACPI based P-state support\n\nPatch to support P-state transitions on ia64. This driver is based on ACPI,\nand uses the ACPI processor driver interface to find out the P-state support\ninformation for the processor. This driver plugs into generic cpufreq\ninfrastructure.\n\nOnce this driver is loaded successfully, ondemand/userspace governor can be\nused to change the CPU frequency dynamically based on load or on request from\nuserspace process.\n\nRefer :\nACPI specification -\n      http://www.acpi.info\nP-state related PAL calls -\n      http://developer.intel.com/design/itanium/downloads/24869909.pdf\n\nSigned-off-by: Venkatesh Pallipadi \u003cvenkatesh.pallipadi@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "e927ecb05e1ce4bbb1e10f57008c94994e2160f5",
      "tree": "bc8256cc074f02d557088696035982fa7ae0b301",
      "parents": [
        "6118ec847e8e35393efc0f88394c2f5dd48c3313"
      ],
      "author": {
        "name": "Suresh Siddha",
        "email": "suresh.b.siddha@intel.com",
        "time": "Mon Apr 25 13:25:06 2005 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Mon Apr 25 13:25:06 2005 -0700"
      },
      "message": "[IA64] multi-core/multi-thread identification\n\nVersion 3 - rediffed to apply on top of Ashok\u0027s hotplug cpu\npatch.  /proc/cpuinfo output in step with x86.\n\nThis is an updated MC/MT identification patch based on the \nprevious discussions on list. \n\nAdd the Multi-core and Multi-threading detection for IPF.\n  - Add new core and threading related fields in /proc/cpuinfo.\n\t\tPhysical id\n\t\tCore id\n\t\tThread id\n\t\tSiblings\n  - setup the cpu_core_map and cpu_sibling_map appropriately\n  - Handles Hot plug CPU\n \nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: Gordon Jin \u003cgordon.jin@intel.com\u003e\nSigned-off-by: Rohit Seth \u003crohit.seth@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2",
      "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d",
      "parents": [],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n"
    }
  ]
}