)]}'
{
  "commit": "1f3b6045f783ee394076ad6dba2d72ecaaecd243",
  "tree": "c20820794846f45db619991d0ddc26832ccf75e8",
  "parents": [
    "adb34022eb7a11126fecef6b5abb4741a17360c6"
  ],
  "author": {
    "name": "Russ Anderson",
    "email": "rja@sgi.com",
    "time": "Wed Oct 31 11:10:38 2007 -0500"
  },
  "committer": {
    "name": "Tony Luck",
    "email": "tony.luck@intel.com",
    "time": "Tue Nov 06 15:40:31 2007 -0800"
  },
  "message": "[IA64] Disable/re-enable CPE interrupts on Altix\n\nWhen the CPE handler encounters too many CPEs (such as a solid single\nbit memory error), it sets up a polling timer and disables the CPE\ninterrupt (to avoid excessive overhead logging the stream of single\nbit errors).  disable_irq_nosync() calls chip-\u003edisable() to provide\na chipset specifiec interface for disabling the interrupt.  This patch\nadds the Altix specific support to disable and re-enable the CPE interrupt.\n\nSigned-off-by: Russ Anderson (rja@sgi.com)\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cc87025e8f54c0d2656584376949a44642432815",
      "old_mode": 33188,
      "old_path": "arch/ia64/kernel/mca.c",
      "new_id": "10b48cd15a878c399503d5bc5da4334906748978",
      "new_mode": 33188,
      "new_path": "arch/ia64/kernel/mca.c"
    },
    {
      "type": "modify",
      "old_id": "0f9b12683bf39bfb44da0adb2f1b21816a6c19c0",
      "old_mode": 33188,
      "old_path": "arch/ia64/sn/kernel/irq.c",
      "new_id": "53351c3cd7b1ef071fb6ff53ccdfc219f135182d",
      "new_mode": 33188,
      "new_path": "arch/ia64/sn/kernel/irq.c"
    }
  ]
}