tree ae4d69033fa3e1e64485433bec8e496fc498ca8f
parent 165aeb82848c81ee1774f8defc74df4341e9184b
author Andi Kleen <ak@suse.de> 1126543764 +0200
committer Linus Torvalds <torvalds@g5.osdl.org> 1126547398 -0700

[PATCH] x86-64: Increase TLB flush array size

The generic TLB flush functions kept upto 506 pages per
CPU to avoid too frequent IPIs.

This value was done for the L1 cache of older x86 CPUs,
but with modern CPUs it does not make much sense anymore.
TLB flushing is slow enough that using the L2 cache is fine.

This patch increases the flush array on x86-64 to cache
5350 pages. That is roughly 20MB with 4K pages. It speeds
up large munmaps in multithreaded processes on SMP considerably.

The cost is roughly 42k of memory per CPU, which is reasonable.

I only increased it on x86-64 for now, but it would probably
make sense to increase it everywhere. Embedded architectures
with SMP may keep it smaller to save some memory per CPU.

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>