[PARISC] PA7200 also supports prefetch for read
It seems PA7200 processors also suppress traps on loads to
%r0. This means we can prefetch for read on these cpus. Of course,
we can't support prefetch for write, since that requires
LOAD DOUBLEWORD which was added with PA2.0
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
diff --git a/include/asm-parisc/prefetch.h b/include/asm-parisc/prefetch.h
index f5a2e7a..5d02172 100644
--- a/include/asm-parisc/prefetch.h
+++ b/include/asm-parisc/prefetch.h
@@ -24,11 +24,14 @@
__asm__("ldw 0(%0), %%r0" : : "r" (addr));
}
+/* LDD is a PA2.0 addition. */
+#ifdef CONFIG_PA20
#define ARCH_HAS_PREFETCHW
extern inline void prefetchw(const void *addr)
{
__asm__("ldd 0(%0), %%r0" : : "r" (addr));
}
+#endif /* CONFIG_PA20 */
#endif /* CONFIG_PREFETCH */
#endif /* __ASSEMBLY__ */