)]}'
{
  "commit": "8799ee9f49f6171fd58f4d64f8c067ca49006a5d",
  "tree": "b746b8800bc99633f31505d151624c8ccd75cd47",
  "parents": [
    "326764a85b7676388db3ebad6488f312631d7661"
  ],
  "author": {
    "name": "Russell King",
    "email": "rmk@dyn-67.arm.linux.org.uk",
    "time": "Thu Jun 29 18:24:21 2006 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Thu Jun 29 18:24:21 2006 +0100"
  },
  "message": "[ARM] Set bit 4 on section mappings correctly depending on CPU\n\nOn some CPUs, bit 4 of section mappings means \"update the\ncache when written to\".  On others, this bit is required to\nbe one, and others it\u0027s required to be zero.  Finally, on\nARMv6 and above, setting it turns on \"no execute\" and prevents\nspeculative prefetches.\n\nWith all these combinations, no one value fits all CPUs, so we\nhave to pick a value depending on the CPU type, and the area\nwe\u0027re mapping.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
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