)]}'
{
  "commit": "a09e89f67ca56d6fa7634bd0738d64fa61bc3c39",
  "tree": "fca9a84947d7faaf72ca5d4e2e2120bf59487ff1",
  "parents": [
    "0a3fabe30e1a3b2037a12b863b8c45fffce38ee9"
  ],
  "author": {
    "name": "Adam Lackorzynski",
    "email": "adam@os.inf.tu-dresden.de",
    "time": "Thu Mar 10 17:41:56 2011 +0100"
  },
  "committer": {
    "name": "Takashi Iwai",
    "email": "tiwai@suse.de",
    "time": "Thu Mar 10 17:44:34 2011 +0100"
  },
  "message": "ALSA: hda: Prevent writing ICH6_PCIREG_TCSEL on AMD systems\n\nazx_init_pci() always writes PCI config register ICH6_PCIREG_TCSEL\nalthough this looks to be only defined on Intel systems and has a\ndifferent meaning on AMD systems. On AMD systems the PCI interrupt pin\ncontrol register is modified instead.\n\nSince the meaning of offset 0x44 in device specific configuration space is\nunknown for devices by other vendors, we only exclude AMD systems to\nretain the current behaviour.\n\nSigned-off-by: Adam Lackorzynski \u003cadam@os.inf.tu-dresden.de\u003e\nSigned-off-by: Takashi Iwai \u003ctiwai@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fcedad9a5feffab614d084f92a3f3588d89a3382",
      "old_mode": 33188,
      "old_path": "sound/pci/hda/hda_intel.c",
      "new_id": "70a9d32f0e967561ee64c83d515c721c2903978c",
      "new_mode": 33188,
      "new_path": "sound/pci/hda/hda_intel.c"
    }
  ]
}