)]}'
{
  "commit": "ba0cef3d149ce4db293c572bf36ed352b11ce7b9",
  "tree": "af811c141b19286f715d75c564f121aeda40f309",
  "parents": [
    "c530ccd9a1864a44a7ff35826681229ce9f2357a"
  ],
  "author": {
    "name": "Stephane Eranian",
    "email": "eranian@google.com",
    "time": "Fri Oct 15 15:15:01 2010 +0200"
  },
  "committer": {
    "name": "Ingo Molnar",
    "email": "mingo@elte.hu",
    "time": "Mon Oct 18 19:58:48 2010 +0200"
  },
  "message": "perf_events: Fix bogus AMD64 generic TLB events\n\nPERF_COUNT_HW_CACHE_DTLB:READ:MISS had a bogus umask value of 0 which\ncounts nothing. Needed to be 0x7 (to count all possibilities).\n\nPERF_COUNT_HW_CACHE_ITLB:READ:MISS had a bogus umask value of 0 which\ncounts nothing. Needed to be 0x3 (to count all possibilities).\n\nSigned-off-by: Stephane Eranian \u003ceranian@google.com\u003e\nSigned-off-by: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Robert Richter \u003crobert.richter@amd.com\u003e\nCc: \u003cstable@kernel.org\u003e # as far back as it applies\nLKML-Reference: \u003c4cb85478.41e9d80a.44e2.3f00@mx.google.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c2897b7b4a3b1c7a6cfe4fe7e70b3d7378432d4c",
      "old_mode": 33188,
      "old_path": "arch/x86/kernel/cpu/perf_event_amd.c",
      "new_id": "46d58448c3aff9039fdf0b909d069d00d80ef75e",
      "new_mode": 33188,
      "new_path": "arch/x86/kernel/cpu/perf_event_amd.c"
    }
  ]
}