)]}'
{
  "commit": "e7a7b329f2001da8fbc3a35735adf32e516b9f93",
  "tree": "cb25fa2b29d6d9d1edf61d6c830c365495c32267",
  "parents": [
    "1a23b4a64a6ede84eae820f35e02a869bdf09b77"
  ],
  "author": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Wed Nov 09 16:26:13 2011 -0600"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Thu Nov 24 02:01:36 2011 -0600"
  },
  "message": "powerpc/85xx: Rework MPC8569MDS device tree\n\nUtilize new split between board \u0026 SoC, and new SoC device trees split\ninto pre \u0026 post utilizing \u0027template\u0027 includes for SoC IP blocks.\n\nOther changes include:\n* Moved to a standard 2 #address-cells \u0026 #size-cells at top-level\n* Moved to specifying interrupt-parent for mpic at root\n* Moved to 4-cell mpic interrupt cells to support MPIC timers\n* Removed CPU properties setup by u-boot to match other .dts\n* Reworked PCIe nodes to allow supportin IRQs for controller (errors)\n  and moved PCI device IRQs down to virtual bridge level\n* Renamed SDHC node from \u0027sdhci\u0027 to \u0027sdhc\u0027\n* Dropping \"fsl,mpc8569-IP...\" from compatibles for standard blocks\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
    {
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      "old_path": "/dev/null",
      "new_id": "eb75a18e61e4fdabd61899e1c7420bd4279020e4",
      "new_mode": 33188,
      "new_path": "arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi"
    },
    {
      "type": "add",
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b07064d1193084fd8cc6b5097d82c240057987df",
      "new_mode": 33188,
      "new_path": "arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi"
    },
    {
      "type": "modify",
      "old_id": "8b72eaff5b0329e56ffb27279076b6ef111724e4",
      "old_mode": 33188,
      "old_path": "arch/powerpc/boot/dts/mpc8569mds.dts",
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      "new_mode": 33188,
      "new_path": "arch/powerpc/boot/dts/mpc8569mds.dts"
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}