)]}'
{
  "commit": "f59ca05871a055a73f8e626f2d868f0da248e22c",
  "tree": "dd077b2cbbf92f9dbda925d8bff9e567f5a56b3f",
  "parents": [
    "3b8f40481513a7b6123def5a02db4cff96ae2198"
  ],
  "author": {
    "name": "Shan Hai",
    "email": "haishan.bai@gmail.com",
    "time": "Thu Sep 01 11:32:03 2011 +0800"
  },
  "committer": {
    "name": "Ingo Molnar",
    "email": "mingo@elte.hu",
    "time": "Tue Sep 13 11:12:22 2011 +0200"
  },
  "message": "locking, lib/atomic64: Annotate atomic64_lock::lock as raw\n\nThe spinlock protected atomic64 operations must be irq safe as they\nare used in hard interrupt context and cannot be preempted on -rt:\n\n NIP [c068b218] rt_spin_lock_slowlock+0x78/0x3a8\n  LR [c068b1e0] rt_spin_lock_slowlock+0x40/0x3a8\n Call Trace:\n  [eb459b90] [c068b1e0] rt_spin_lock_slowlock+0x40/0x3a8 (unreliable)\n  [eb459c20] [c068bdb0] rt_spin_lock+0x40/0x98\n  [eb459c40] [c03d2a14] atomic64_read+0x48/0x84\n  [eb459c60] [c001aaf4] perf_event_interrupt+0xec/0x28c\n  [eb459d10] [c0010138] performance_monitor_exception+0x7c/0x150\n  [eb459d30] [c0014170] ret_from_except_full+0x0/0x4c\n\nSo annotate it.\n\nIn mainline this change documents the low level nature of\nthe lock - otherwise there\u0027s no functional difference. Lockdep\nand Sparse checking will work as usual.\n\nSigned-off-by: Shan Hai \u003chaishan.bai@gmail.com\u003e\nReviewed-by: Yong Zhang \u003cyong.zhang0@gmail.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e12ae0dd08a8d077b1c3160ac1ee90986cc3b38d",
      "old_mode": 33188,
      "old_path": "lib/atomic64.c",
      "new_id": "82b33134e141b469c963ef036b082562a4dfbf95",
      "new_mode": 33188,
      "new_path": "lib/atomic64.c"
    }
  ]
}