| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | menu "DMA support" | 
 | 2 |  | 
 | 3 | config SH_DMA | 
 | 4 | 	bool "DMA controller (DMAC) support" | 
 | 5 | 	help | 
 | 6 | 	  Selecting this option will provide same API as PC's Direct Memory | 
 | 7 | 	  Access Controller(8237A) for SuperH DMAC. | 
 | 8 |  | 
 | 9 | 	  If unsure, say N. | 
 | 10 |  | 
 | 11 | config NR_ONCHIP_DMA_CHANNELS | 
 | 12 | 	depends on SH_DMA | 
 | 13 | 	int "Number of on-chip DMAC channels" | 
 | 14 | 	default "4" | 
 | 15 | 	help | 
 | 16 | 	  This allows you to specify the number of channels that the on-chip | 
 | 17 | 	  DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the | 
 | 18 | 	  SH7750R/SH7751R. | 
 | 19 |  | 
 | 20 | config NR_DMA_CHANNELS_BOOL | 
 | 21 | 	depends on SH_DMA | 
 | 22 | 	bool "Override default number of maximum DMA channels" | 
 | 23 | 	help | 
 | 24 | 	  This allows you to forcibly update the maximum number of supported | 
 | 25 | 	  DMA channels for a given board. If this is unset, this will default | 
 | 26 | 	  to the number of channels that the on-chip DMAC has. | 
 | 27 |  | 
 | 28 | config NR_DMA_CHANNELS | 
 | 29 | 	int "Maximum number of DMA channels" | 
 | 30 | 	depends on SH_DMA && NR_DMA_CHANNELS_BOOL | 
 | 31 | 	default NR_ONCHIP_DMA_CHANNELS | 
 | 32 | 	help | 
 | 33 | 	  This allows you to specify the maximum number of DMA channels to | 
 | 34 | 	  support. Setting this to a higher value allows for cascading DMACs | 
 | 35 | 	  with additional channels. | 
 | 36 |  | 
 | 37 | config DMA_PAGE_OPS | 
 | 38 | 	bool "Use DMAC for page copy/clear" | 
 | 39 | 	depends on SH_DMA && BROKEN | 
 | 40 | 	help | 
 | 41 | 	  Selecting this option will use a dual-address mode configured channel | 
 | 42 | 	  in the SH DMAC for copy_page()/clear_page(). Primarily a performance | 
 | 43 | 	  hack. | 
 | 44 |  | 
 | 45 | config DMA_PAGE_OPS_CHANNEL | 
 | 46 | 	depends on DMA_PAGE_OPS | 
 | 47 | 	int "DMA channel for sh memory-manager page copy/clear" | 
 | 48 | 	default "3" | 
 | 49 | 	help | 
 | 50 | 	  This allows the specification of the dual address dma channel, | 
 | 51 | 	  in case channel 3 is unavailable. On the SH4, channels 1,2, and 3 | 
 | 52 | 	  are dual-address capable. | 
 | 53 |  | 
 | 54 | endmenu | 
 | 55 |  |