| Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 1 | # | 
|  | 2 | # DMA engine configuration | 
|  | 3 | # | 
|  | 4 |  | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 5 | menuconfig DMADEVICES | 
| Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 6 | bool "DMA Engine support" | 
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 7 | depends on !HIGHMEM64G && HAS_DMA | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 8 | help | 
| Haavard Skinnemoen | 6d4f587 | 2007-11-28 16:21:43 -0800 | [diff] [blame] | 9 | DMA engines can do asynchronous data transfers without | 
|  | 10 | involving the host CPU.  Currently, this framework can be | 
|  | 11 | used to offload memory copies in the network stack and | 
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 12 | RAID operations in the MD driver.  This menu only presents | 
|  | 13 | DMA Device drivers supported by the configured arch, it may | 
|  | 14 | be empty in some cases. | 
| Chris Leech | c13c826 | 2006-05-23 17:18:44 -0700 | [diff] [blame] | 15 |  | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 16 | if DMADEVICES | 
| Chris Leech | db21733 | 2006-06-17 21:24:58 -0700 | [diff] [blame] | 17 |  | 
| Chris Leech | 0bbd5f4 | 2006-05-23 17:35:34 -0700 | [diff] [blame] | 18 | comment "DMA Devices" | 
|  | 19 |  | 
|  | 20 | config INTEL_IOATDMA | 
|  | 21 | tristate "Intel I/OAT DMA support" | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 22 | depends on PCI && X86 | 
|  | 23 | select DMA_ENGINE | 
|  | 24 | select DCA | 
|  | 25 | help | 
|  | 26 | Enable support for the Intel(R) I/OAT DMA engine present | 
|  | 27 | in recent Intel Xeon chipsets. | 
|  | 28 |  | 
|  | 29 | Say Y here if you have such a chipset. | 
|  | 30 |  | 
|  | 31 | If unsure, say N. | 
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 32 |  | 
|  | 33 | config INTEL_IOP_ADMA | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 34 | tristate "Intel IOP ADMA support" | 
|  | 35 | depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | 
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 36 | select ASYNC_CORE | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 37 | select DMA_ENGINE | 
|  | 38 | help | 
|  | 39 | Enable support for the Intel(R) IOP Series RAID engines. | 
| Dan Williams | c211092 | 2007-01-02 13:52:26 -0700 | [diff] [blame] | 40 |  | 
| Haavard Skinnemoen | 3bfb1d2 | 2008-07-08 11:59:42 -0700 | [diff] [blame^] | 41 | config DW_DMAC | 
|  | 42 | tristate "Synopsys DesignWare AHB DMA support" | 
|  | 43 | depends on AVR32 | 
|  | 44 | select DMA_ENGINE | 
|  | 45 | default y if CPU_AT32AP7000 | 
|  | 46 | help | 
|  | 47 | Support the Synopsys DesignWare AHB DMA controller.  This | 
|  | 48 | can be integrated in chips such as the Atmel AT32ap7000. | 
|  | 49 |  | 
| Zhang Wei | 173acc7 | 2008-03-01 07:42:48 -0700 | [diff] [blame] | 50 | config FSL_DMA | 
|  | 51 | bool "Freescale MPC85xx/MPC83xx DMA support" | 
|  | 52 | depends on PPC | 
|  | 53 | select DMA_ENGINE | 
|  | 54 | ---help--- | 
|  | 55 | Enable support for the Freescale DMA engine. Now, it support | 
|  | 56 | MPC8560/40, MPC8555, MPC8548 and MPC8641 processors. | 
|  | 57 | The MPC8349, MPC8360 is also supported. | 
|  | 58 |  | 
| Saeed Bishara | ff7b047 | 2008-07-08 11:58:36 -0700 | [diff] [blame] | 59 | config MV_XOR | 
|  | 60 | bool "Marvell XOR engine support" | 
|  | 61 | depends on PLAT_ORION | 
|  | 62 | select ASYNC_CORE | 
|  | 63 | select DMA_ENGINE | 
|  | 64 | ---help--- | 
|  | 65 | Enable support for the Marvell XOR engine. | 
|  | 66 |  | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 67 | config DMA_ENGINE | 
|  | 68 | bool | 
|  | 69 |  | 
|  | 70 | comment "DMA Clients" | 
|  | 71 | depends on DMA_ENGINE | 
|  | 72 |  | 
|  | 73 | config NET_DMA | 
|  | 74 | bool "Network: TCP receive copy offload" | 
|  | 75 | depends on DMA_ENGINE && NET | 
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 76 | default (INTEL_IOATDMA || FSL_DMA) | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 77 | help | 
|  | 78 | This enables the use of DMA engines in the network stack to | 
|  | 79 | offload receive copy-to-user operations, freeing CPU cycles. | 
| Dan Williams | 9c402f4 | 2008-06-27 01:21:11 -0700 | [diff] [blame] | 80 |  | 
|  | 81 | Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise | 
|  | 82 | say N. | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 83 |  | 
| Haavard Skinnemoen | 4a776f0 | 2008-07-08 11:58:45 -0700 | [diff] [blame] | 84 | config DMATEST | 
|  | 85 | tristate "DMA Test client" | 
|  | 86 | depends on DMA_ENGINE | 
|  | 87 | help | 
|  | 88 | Simple DMA test client. Say N unless you're debugging a | 
|  | 89 | DMA Device driver. | 
|  | 90 |  | 
| Shannon Nelson | 2ed6dc3 | 2007-10-16 01:27:42 -0700 | [diff] [blame] | 91 | endif |