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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* sun4m_irq.c
2 * arch/sparc/kernel/sun4m_irq.c:
3 *
4 * djhr: Hacked out of irq.c into a CPU dependent version.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
10 */
11
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/errno.h>
13#include <linux/linkage.h>
14#include <linux/kernel_stat.h>
15#include <linux/signal.h>
16#include <linux/sched.h>
17#include <linux/ptrace.h>
18#include <linux/smp.h>
19#include <linux/interrupt.h>
20#include <linux/slab.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
David S. Miller454eeb22008-08-27 04:05:35 -070023#include <linux/of.h>
24#include <linux/of_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include <asm/ptrace.h>
27#include <asm/processor.h>
28#include <asm/system.h>
29#include <asm/psr.h>
30#include <asm/vaddrs.h>
31#include <asm/timer.h>
32#include <asm/openprom.h>
33#include <asm/oplib.h>
34#include <asm/traps.h>
35#include <asm/pgalloc.h>
36#include <asm/pgtable.h>
37#include <asm/smp.h>
38#include <asm/irq.h>
39#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <asm/cacheflush.h>
41
Al Viro32231a62007-07-21 19:18:57 -070042#include "irq.h"
43
44/* On the sun4m, just like the timers, we have both per-cpu and master
45 * interrupt registers.
46 */
47
48/* These registers are used for sending/receiving irqs from/to
49 * different cpu's.
50 */
51struct sun4m_intreg_percpu {
52 unsigned int tbt; /* Interrupts still pending for this cpu. */
53
54 /* These next two registers are WRITE-ONLY and are only
55 * "on bit" sensitive, "off bits" written have NO affect.
56 */
57 unsigned int clear; /* Clear this cpus irqs here. */
58 unsigned int set; /* Set this cpus irqs here. */
59 unsigned char space[PAGE_SIZE - 12];
60};
61
62/*
63 * djhr
64 * Actually the clear and set fields in this struct are misleading..
65 * according to the SLAVIO manual (and the same applies for the SEC)
66 * the clear field clears bits in the mask which will ENABLE that IRQ
67 * the set field sets bits in the mask to DISABLE the IRQ.
68 *
69 * Also the undirected_xx address in the SLAVIO is defined as
70 * RESERVED and write only..
71 *
72 * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
73 * sun4m machines, for MP the layout makes more sense.
74 */
75struct sun4m_intregs {
76 struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
77 unsigned int tbt; /* IRQ's that are still pending. */
78 unsigned int irqs; /* Master IRQ bits. */
79
80 /* Again, like the above, two these registers are WRITE-ONLY. */
81 unsigned int clear; /* Clear master IRQ's by setting bits here. */
82 unsigned int set; /* Set master IRQ's by setting bits here. */
83
84 /* This register is both READ and WRITE. */
85 unsigned int undirected_target; /* Which cpu gets undirected irqs. */
86};
87
Linus Torvalds1da177e2005-04-16 15:20:36 -070088static unsigned long dummy;
89
90struct sun4m_intregs *sun4m_interrupts;
91unsigned long *irq_rcvreg = &dummy;
92
Al Viro32231a62007-07-21 19:18:57 -070093/* Dave Redman (djhr@tadpole.co.uk)
94 * The sun4m interrupt registers.
95 */
96#define SUN4M_INT_ENABLE 0x80000000
97#define SUN4M_INT_E14 0x00000080
98#define SUN4M_INT_E10 0x00080000
99
100#define SUN4M_HARD_INT(x) (0x000000001 << (x))
101#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
102
103#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
104#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
105#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
106#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
107#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
108#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
109#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
110#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
111#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
112#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
113#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
114#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
115#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
116#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
117
118#define SUN4M_INT_SBUS(x) (1 << (x+7))
119#define SUN4M_INT_VME(x) (1 << (x))
120
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121/* These tables only apply for interrupts greater than 15..
122 *
123 * any intr value below 0x10 is considered to be a soft-int
124 * this may be useful or it may not.. but that's how I've done it.
125 * and it won't clash with what OBP is telling us about devices.
126 *
127 * take an encoded intr value and lookup if it's valid
128 * then get the mask bits that match from irq_mask
129 *
130 * P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
131 */
132static unsigned char irq_xlate[32] = {
133 /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
134 0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
135 0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
136};
137
138static unsigned long irq_mask[] = {
139 0, /* illegal index */
140 SUN4M_INT_SCSI, /* 1 irq 4 */
141 SUN4M_INT_ETHERNET, /* 2 irq 6 */
142 SUN4M_INT_VIDEO, /* 3 irq 8 */
143 SUN4M_INT_REALTIME, /* 4 irq 10 */
144 SUN4M_INT_FLOPPY, /* 5 irq 11 */
145 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), /* 6 irq 12 */
146 SUN4M_INT_MODULE_ERR, /* 7 irq 15 */
147 SUN4M_INT_SBUS(0), /* 8 irq 2 */
148 SUN4M_INT_SBUS(1), /* 9 irq 3 */
149 SUN4M_INT_SBUS(2), /* 10 irq 5 */
150 SUN4M_INT_SBUS(3), /* 11 irq 7 */
151 SUN4M_INT_SBUS(4), /* 12 irq 9 */
152 SUN4M_INT_SBUS(5), /* 13 irq 11 */
153 SUN4M_INT_SBUS(6) /* 14 irq 13 */
154};
155
Adrian Bunkc61c65c2008-06-05 11:40:58 -0700156static unsigned long sun4m_get_irqmask(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157{
158 unsigned long mask;
159
160 if (irq > 0x20) {
161 /* OBIO/SBUS interrupts */
162 irq &= 0x1f;
163 mask = irq_mask[irq_xlate[irq]];
164 if (!mask)
165 printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
166 } else {
167 /* Soft Interrupts will come here.
168 * Currently there is no way to trigger them but I'm sure
169 * something could be cooked up.
170 */
171 irq &= 0xf;
172 mask = SUN4M_SOFT_INT(irq);
173 }
174 return mask;
175}
176
177static void sun4m_disable_irq(unsigned int irq_nr)
178{
179 unsigned long mask, flags;
180 int cpu = smp_processor_id();
181
182 mask = sun4m_get_irqmask(irq_nr);
183 local_irq_save(flags);
184 if (irq_nr > 15)
185 sun4m_interrupts->set = mask;
186 else
187 sun4m_interrupts->cpu_intregs[cpu].set = mask;
188 local_irq_restore(flags);
189}
190
191static void sun4m_enable_irq(unsigned int irq_nr)
192{
193 unsigned long mask, flags;
194 int cpu = smp_processor_id();
195
196 /* Dreadful floppy hack. When we use 0x2b instead of
197 * 0x0b the system blows (it starts to whistle!).
198 * So we continue to use 0x0b. Fixme ASAP. --P3
199 */
200 if (irq_nr != 0x0b) {
201 mask = sun4m_get_irqmask(irq_nr);
202 local_irq_save(flags);
203 if (irq_nr > 15)
204 sun4m_interrupts->clear = mask;
205 else
206 sun4m_interrupts->cpu_intregs[cpu].clear = mask;
207 local_irq_restore(flags);
208 } else {
209 local_irq_save(flags);
210 sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
211 local_irq_restore(flags);
212 }
213}
214
215static unsigned long cpu_pil_to_imask[16] = {
216/*0*/ 0x00000000,
217/*1*/ 0x00000000,
218/*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
219/*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
220/*4*/ SUN4M_INT_SCSI,
221/*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
222/*6*/ SUN4M_INT_ETHERNET,
223/*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
224/*8*/ SUN4M_INT_VIDEO,
225/*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
226/*10*/ SUN4M_INT_REALTIME,
227/*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
228/*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
229/*13*/ SUN4M_INT_AUDIO,
230/*14*/ SUN4M_INT_E14,
231/*15*/ 0x00000000
232};
233
234/* We assume the caller has disabled local interrupts when these are called,
235 * or else very bizarre behavior will result.
236 */
237static void sun4m_disable_pil_irq(unsigned int pil)
238{
239 sun4m_interrupts->set = cpu_pil_to_imask[pil];
240}
241
242static void sun4m_enable_pil_irq(unsigned int pil)
243{
244 sun4m_interrupts->clear = cpu_pil_to_imask[pil];
245}
246
247#ifdef CONFIG_SMP
248static void sun4m_send_ipi(int cpu, int level)
249{
250 unsigned long mask;
251
252 mask = sun4m_get_irqmask(level);
253 sun4m_interrupts->cpu_intregs[cpu].set = mask;
254}
255
256static void sun4m_clear_ipi(int cpu, int level)
257{
258 unsigned long mask;
259
260 mask = sun4m_get_irqmask(level);
261 sun4m_interrupts->cpu_intregs[cpu].clear = mask;
262}
263
264static void sun4m_set_udt(int cpu)
265{
266 sun4m_interrupts->undirected_target = cpu;
267}
268#endif
269
270#define OBIO_INTR 0x20
271#define TIMER_IRQ (OBIO_INTR | 10)
272#define PROFILE_IRQ (OBIO_INTR | 14)
273
Adrian Bunkc61c65c2008-06-05 11:40:58 -0700274static struct sun4m_timer_regs *sun4m_timers;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
276
277static void sun4m_clear_clock_irq(void)
278{
279 volatile unsigned int clear_intr;
280 clear_intr = sun4m_timers->l10_timer_limit;
281}
282
283static void sun4m_clear_profile_irq(int cpu)
284{
285 volatile unsigned int clear;
286
287 clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
288}
289
290static void sun4m_load_profile_irq(int cpu, unsigned int limit)
291{
292 sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
293}
294
David Howells40220c12006-10-09 12:19:47 +0100295static void __init sun4m_init_timers(irq_handler_t counter_fn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296{
297 int reg_count, irq, cpu;
298 struct linux_prom_registers cnt_regs[PROMREG_MAX];
299 int obio_node, cnt_node;
300 struct resource r;
301
302 cnt_node = 0;
303 if((obio_node =
304 prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
305 (obio_node = prom_getchild (obio_node)) == 0 ||
306 (cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
307 prom_printf("Cannot find /obio/counter node\n");
308 prom_halt();
309 }
310 reg_count = prom_getproperty(cnt_node, "reg",
311 (void *) cnt_regs, sizeof(cnt_regs));
312 reg_count = (reg_count/sizeof(struct linux_prom_registers));
313
314 /* Apply the obio ranges to the timer registers. */
315 prom_apply_obio_ranges(cnt_regs, reg_count);
316
317 cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
318 cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
319 cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
320 for(obio_node = 1; obio_node < 4; obio_node++) {
321 cnt_regs[obio_node].phys_addr =
322 cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
323 cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
324 cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
325 }
326
327 memset((char*)&r, 0, sizeof(struct resource));
328 /* Map the per-cpu Counter registers. */
329 r.flags = cnt_regs[0].which_io;
330 r.start = cnt_regs[0].phys_addr;
David S. Miller454eeb22008-08-27 04:05:35 -0700331 sun4m_timers = (struct sun4m_timer_regs *) of_ioremap(&r, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332 PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
333 /* Map the system Counter register. */
334 /* XXX Here we expect consequent calls to yeld adjusent maps. */
335 r.flags = cnt_regs[4].which_io;
336 r.start = cnt_regs[4].phys_addr;
David S. Miller454eeb22008-08-27 04:05:35 -0700337 of_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
339 sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
340 master_l10_counter = &sun4m_timers->l10_cur_count;
341 master_l10_limit = &sun4m_timers->l10_timer_limit;
342
343 irq = request_irq(TIMER_IRQ,
344 counter_fn,
Thomas Gleixner67413202006-07-01 19:29:26 -0700345 (IRQF_DISABLED | SA_STATIC_ALLOC),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346 "timer", NULL);
347 if (irq) {
348 prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
349 prom_halt();
350 }
351
352 if (!cpu_find_by_instance(1, NULL, NULL)) {
353 for(cpu = 0; cpu < 4; cpu++)
354 sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
355 sun4m_interrupts->set = SUN4M_INT_E14;
356 } else {
357 sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
358 }
359#ifdef CONFIG_SMP
360 {
361 unsigned long flags;
362 extern unsigned long lvl14_save[4];
363 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
364
365 /* For SMP we use the level 14 ticker, however the bootup code
Simon Arlottd1a78c32007-05-11 13:51:23 -0700366 * has copied the firmware's level 14 vector into the boot cpu's
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 * trap table, we must fix this now or we get squashed.
368 */
369 local_irq_save(flags);
370 trap_table->inst_one = lvl14_save[0];
371 trap_table->inst_two = lvl14_save[1];
372 trap_table->inst_three = lvl14_save[2];
373 trap_table->inst_four = lvl14_save[3];
374 local_flush_cache_all();
375 local_irq_restore(flags);
376 }
377#endif
378}
379
380void __init sun4m_init_IRQ(void)
381{
382 int ie_node,i;
383 struct linux_prom_registers int_regs[PROMREG_MAX];
384 int num_regs;
385 struct resource r;
386 int mid;
387
388 local_irq_disable();
389 if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
390 (ie_node = prom_getchild (ie_node)) == 0 ||
391 (ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
392 prom_printf("Cannot find /obio/interrupt node\n");
393 prom_halt();
394 }
395 num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
396 sizeof(int_regs));
397 num_regs = (num_regs/sizeof(struct linux_prom_registers));
398
399 /* Apply the obio ranges to these registers. */
400 prom_apply_obio_ranges(int_regs, num_regs);
401
402 int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
403 int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
404 int_regs[4].which_io = int_regs[num_regs-1].which_io;
405 for(ie_node = 1; ie_node < 4; ie_node++) {
406 int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
407 int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
408 int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
409 }
410
411 memset((char *)&r, 0, sizeof(struct resource));
412 /* Map the interrupt registers for all possible cpus. */
413 r.flags = int_regs[0].which_io;
414 r.start = int_regs[0].phys_addr;
David S. Miller454eeb22008-08-27 04:05:35 -0700415 sun4m_interrupts = (struct sun4m_intregs *) of_ioremap(&r, 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");
417
418 /* Map the system interrupt control registers. */
419 r.flags = int_regs[4].which_io;
420 r.start = int_regs[4].phys_addr;
David S. Miller454eeb22008-08-27 04:05:35 -0700421 of_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422
423 sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
424 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
425 sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff;
426
427 if (!cpu_find_by_instance(1, NULL, NULL)) {
428 /* system wide interrupts go to cpu 0, this should always
429 * be safe because it is guaranteed to be fitted or OBP doesn't
430 * come up
431 *
432 * Not sure, but writing here on SLAVIO systems may puke
433 * so I don't do it unless there is more than 1 cpu.
434 */
435 irq_rcvreg = (unsigned long *)
436 &sun4m_interrupts->undirected_target;
437 sun4m_interrupts->undirected_target = 0;
438 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439 BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
440 BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
441 BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
442 BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
443 BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
444 BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
445 BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 sparc_init_timers = sun4m_init_timers;
447#ifdef CONFIG_SMP
448 BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
449 BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
450 BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
451#endif
452 /* Cannot enable interrupts until OBP ticker is disabled. */
453}