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review.evervolv.com / android_kernel_oneplus_sm8150 / b13cfd173f73c3f6f9a307b7b6e64d45fbd756b2 / . / include / asm-mips / ddb5xxx / ddb5476.h
blob: 4c23390d9354e730e186956d6d4e417187aaf033 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * header file specific for ddb5476
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/*
15 * Memory map (physical address)
16 *
17 * Note most of the following address must be properly aligned by the
18 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
19 * PCI_IO_BASE must be aligned along 16MB boundary.
20 */
21#define DDB_SDRAM_BASE 0x00000000
22#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
23
24#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
25#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
26
27#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
28#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
29
30#define DDB_PCI_IO_BASE 0x06000000
31#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
32
33#define DDB_PCI_MEM_BASE 0x08000000
34#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
35
36#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
37#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
38
39#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
40#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
41
42#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
43#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
44
45#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
46#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
47
48
49/* aliases */
50#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
51#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
52
53/* PCI intr ack share PCIW0 with PCI IO */
54#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
55
56/*
57 * Interrupt mapping
58 *
59 * We have three interrupt controllers:
60 *
61 * . CPU itself - 8 sources
62 * . i8259 - 16 sources
63 * . vrc5476 - 16 sources
64 *
65 * They connected as follows:
66 * all vrc5476 interrupts are routed to cpu IP2 (by software setting)
67 * all i2869 are routed to INTC in vrc5476 (by hardware connection)
68 *
69 * All VRC5476 PCI interrupts are level-triggered (no ack needed).
70 * All PCI irq but INTC are active low.
71 */
72
73/*
74 * irq number block assignment
75 */
76
77#define NUM_CPU_IRQ 8
78#define NUM_I8259_IRQ 16
79#define NUM_VRC5476_IRQ 16
80
81#define DDB_IRQ_BASE 0
82
83#define I8259_IRQ_BASE DDB_IRQ_BASE
84#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
85#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
86
87/*
88 * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
89 */
90
91#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
92#define VRC5476_IRQ_CNTD 1 /* cpu no target */
93#define VRC5476_IRQ_MCE 2 /* memory check error */
94#define VRC5476_IRQ_DMA 3 /* DMA */
95#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
96#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
97#define VRC5476_IRQ_GPT 6 /* general purpose timer */
98#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
99#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
100#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
101#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
102#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
103#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
104#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
105#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
106#define VRC5476_IRQ_PCI 15 /* PCI internal error */
107
108/*
109 * i2859 irq assignment
110 */
111#define I8259_IRQ_RESERVED_0 0
112#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
113#define I8259_IRQ_CASCADE 2
114#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
115#define I8259_IRQ_UART_A 4 /* M1543 default */
116#define I8259_IRQ_PARALLEL 5 /* M1543 default */
117#define I8259_IRQ_RESERVED_6 6
118#define I8259_IRQ_RESERVED_7 7
119#define I8259_IRQ_RTC 8 /* who set this? */
120#define I8259_IRQ_USB 9 /* ddb_setup */
121#define I8259_IRQ_PMU 10 /* ddb_setup */
122#define I8259_IRQ_RESERVED_11 11
123#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
124#define I8259_IRQ_RESERVED_13 13
125#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
126#define I8259_IRQ_HDC2 15 /* default */
127
128
129/*
130 * misc
131 */
132#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
133#define CPU_VRC5476_CASCADE 2
134
135#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
136#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
137#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
138
139/*
140 * low-level irq functions
141 */
142#ifndef __ASSEMBLY__
143extern void nile4_map_irq(int nile4_irq, int cpu_irq);
144extern void nile4_map_irq_all(int cpu_irq);
145extern void nile4_enable_irq(int nile4_irq);
146extern void nile4_disable_irq(int nile4_irq);
147extern void nile4_disable_irq_all(void);
148extern u16 nile4_get_irq_stat(int cpu_irq);
149extern void nile4_enable_irq_output(int cpu_irq);
150extern void nile4_disable_irq_output(int cpu_irq);
151extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
152extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
153extern void nile4_clear_irq(int nile4_irq);
154extern void nile4_clear_irq_mask(u32 mask);
155extern u8 nile4_i8259_iack(void);
156extern void nile4_dump_irq_status(void); /* Debug */
157#endif /* !__ASSEMBLY__ */