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review.evervolv.com / android_kernel_oneplus_sm8150 / c5780e976e19faff345fcef4a01db87108b51a44 / . / drivers / scsi / ips.h
blob: f46c382e5599aa022c87631a55f81dcdef17fb6c [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*****************************************************************************/
2/* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 1999 IBM Corporation */
9/* Copyright (C) 2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/*****************************************************************************/
49
50#ifndef _IPS_H_
51 #define _IPS_H_
52
Olaf Hering733482e2005-11-08 21:34:55 -0800[diff] [blame]53#include <linux/version.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]54 #include <asm/uaccess.h>
55 #include <asm/io.h>
56
57 /*
58 * Some handy macros
59 */
60 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) || defined CONFIG_HIGHIO
61 #define IPS_HIGHIO
62 #endif
63
64 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
65 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
66 #define IPS_IS_TROMBONE(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
67 (ha->revision_id >= IPS_REVID_TROMBONE32) && \
68 (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
69 #define IPS_IS_CLARINET(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
70 (ha->revision_id >= IPS_REVID_CLARINETP1) && \
71 (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
72 #define IPS_IS_MORPHEUS(ha) (ha->device_id == IPS_DEVICEID_MORPHEUS)
73 #define IPS_IS_MARCO(ha) (ha->device_id == IPS_DEVICEID_MARCO)
74 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
75 (IPS_IS_TROMBONE(ha) && \
76 (ips_force_i2o))) ? 1 : 0)
77 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
78 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
79 (ips_force_memio))) ? 1 : 0)
80
81 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
82 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
83 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
84 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
85
86 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,4)
87 #define pci_set_dma_mask(dev,mask) ( mask > 0xffffffff ? 1:0 )
88 #define scsi_set_pci_device(sh,dev) (0)
89 #endif
90
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]91 #ifndef IRQ_NONE
92 typedef void irqreturn_t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]93 #define IRQ_NONE
94 #define IRQ_HANDLED
95 #define IRQ_RETVAL(x)
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]96 #endif
97
98 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]99 #define IPS_REGISTER_HOSTS(SHT) scsi_register_module(MODULE_SCSI_HA,SHT)
100 #define IPS_UNREGISTER_HOSTS(SHT) scsi_unregister_module(MODULE_SCSI_HA,SHT)
101 #define IPS_ADD_HOST(shost,device)
102 #define IPS_REMOVE_HOST(shost)
103 #define IPS_SCSI_SET_DEVICE(sh,ha) scsi_set_pci_device(sh, (ha)->pcidev)
104 #define IPS_PRINTK(level, pcidev, format, arg...) \
105 printk(level "%s %s:" format , "ips" , \
106 (pcidev)->slot_name , ## arg)
107 #define scsi_host_alloc(sh,size) scsi_register(sh,size)
108 #define scsi_host_put(sh) scsi_unregister(sh)
109 #else
110 #define IPS_REGISTER_HOSTS(SHT) (!ips_detect(SHT))
111 #define IPS_UNREGISTER_HOSTS(SHT)
112 #define IPS_ADD_HOST(shost,device) do { scsi_add_host(shost,device); scsi_scan_host(shost); } while (0)
113 #define IPS_REMOVE_HOST(shost) scsi_remove_host(shost)
Christoph Hellwig12413192005-06-11 01:05:01 +0200[diff] [blame]114 #define IPS_SCSI_SET_DEVICE(sh,ha) do { } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]115 #define IPS_PRINTK(level, pcidev, format, arg...) \
116 dev_printk(level , &((pcidev)->dev) , format , ## arg)
117 #endif
118
119 #ifndef MDELAY
120 #define MDELAY mdelay
121 #endif
122
123 #ifndef min
124 #define min(x,y) ((x) < (y) ? x : y)
125 #endif
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]126
127 #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */
128 #define __iomem
129 #endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]130
131 #define pci_dma_hi32(a) ((a >> 16) >> 16)
132 #define pci_dma_lo32(a) (a & 0xffffffff)
133
134 #if (BITS_PER_LONG > 32) || (defined CONFIG_HIGHMEM64G && defined IPS_HIGHIO)
135 #define IPS_ENABLE_DMA64 (1)
136 #else
137 #define IPS_ENABLE_DMA64 (0)
138 #endif
139
140 /*
141 * Adapter address map equates
142 */
143 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
144 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
145 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
146 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
147 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
148 #define IPS_REG_SQER 0x28 /* Status Q End Reg */
149 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
150 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
151 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
152 #define IPS_REG_CBSP 0x07 /* CBSP register */
153 #define IPS_REG_FLAP 0x18 /* Flash address port */
154 #define IPS_REG_FLDP 0x1C /* Flash data port */
155 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
156 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
157 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
158 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
159 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
160 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
161 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
162 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
163
164 /*
165 * Adapter register bit equates
166 */
167 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
168 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
169 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
170 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
171 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
172 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
173 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
174 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
175 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
176 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
177 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
178 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
179 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
180 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
181
182 /*
183 * Adapter Command ID Equates
184 */
185 #define IPS_CMD_GET_LD_INFO 0x19
186 #define IPS_CMD_GET_SUBSYS 0x40
187 #define IPS_CMD_READ_CONF 0x38
188 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
189 #define IPS_CMD_READ 0x02
190 #define IPS_CMD_WRITE 0x03
191 #define IPS_CMD_FFDC 0xD7
192 #define IPS_CMD_ENQUIRY 0x05
193 #define IPS_CMD_FLUSH 0x0A
194 #define IPS_CMD_READ_SG 0x82
195 #define IPS_CMD_WRITE_SG 0x83
196 #define IPS_CMD_DCDB 0x04
197 #define IPS_CMD_DCDB_SG 0x84
198 #define IPS_CMD_EXTENDED_DCDB 0x95
199 #define IPS_CMD_EXTENDED_DCDB_SG 0x96
200 #define IPS_CMD_CONFIG_SYNC 0x58
201 #define IPS_CMD_ERROR_TABLE 0x17
202 #define IPS_CMD_DOWNLOAD 0x20
203 #define IPS_CMD_RW_BIOSFW 0x22
204 #define IPS_CMD_GET_VERSION_INFO 0xC6
205 #define IPS_CMD_RESET_CHANNEL 0x1A
206
207 /*
208 * Adapter Equates
209 */
210 #define IPS_CSL 0xFF
211 #define IPS_POCL 0x30
212 #define IPS_NORM_STATE 0x00
213 #define IPS_MAX_ADAPTER_TYPES 3
214 #define IPS_MAX_ADAPTERS 16
215 #define IPS_MAX_IOCTL 1
216 #define IPS_MAX_IOCTL_QUEUE 8
217 #define IPS_MAX_QUEUE 128
218 #define IPS_BLKSIZE 512
219 #define IPS_MAX_SG 17
220 #define IPS_MAX_LD 8
221 #define IPS_MAX_CHANNELS 4
222 #define IPS_MAX_TARGETS 15
223 #define IPS_MAX_CHUNKS 16
224 #define IPS_MAX_CMDS 128
225 #define IPS_MAX_XFER 0x10000
226 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
227 #define IPS_MAX_POST_BYTES 0x02
228 #define IPS_MAX_CONFIG_BYTES 0x02
229 #define IPS_GOOD_POST_STATUS 0x80
230 #define IPS_SEM_TIMEOUT 2000
231 #define IPS_IOCTL_COMMAND 0x0D
232 #define IPS_INTR_ON 0
233 #define IPS_INTR_IORL 1
234 #define IPS_FFDC 99
235 #define IPS_ADAPTER_ID 0xF
236 #define IPS_VENDORID_IBM 0x1014
237 #define IPS_VENDORID_ADAPTEC 0x9005
238 #define IPS_DEVICEID_COPPERHEAD 0x002E
239 #define IPS_DEVICEID_MORPHEUS 0x01BD
240 #define IPS_DEVICEID_MARCO 0x0250
241 #define IPS_SUBDEVICEID_4M 0x01BE
242 #define IPS_SUBDEVICEID_4L 0x01BF
243 #define IPS_SUBDEVICEID_4MX 0x0208
244 #define IPS_SUBDEVICEID_4LX 0x020E
245 #define IPS_SUBDEVICEID_5I2 0x0259
246 #define IPS_SUBDEVICEID_5I1 0x0258
247 #define IPS_SUBDEVICEID_6M 0x0279
248 #define IPS_SUBDEVICEID_6I 0x028C
249 #define IPS_SUBDEVICEID_7k 0x028E
250 #define IPS_SUBDEVICEID_7M 0x028F
251 #define IPS_IOCTL_SIZE 8192
252 #define IPS_STATUS_SIZE 4
253 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
254 #define IPS_IMAGE_SIZE 500 * 1024
255 #define IPS_MEMMAP_SIZE 128
256 #define IPS_ONE_MSEC 1
257 #define IPS_ONE_SEC 1000
258
259 /*
260 * Geometry Settings
261 */
262 #define IPS_COMP_HEADS 128
263 #define IPS_COMP_SECTORS 32
264 #define IPS_NORM_HEADS 254
265 #define IPS_NORM_SECTORS 63
266
267 /*
268 * Adapter Basic Status Codes
269 */
270 #define IPS_BASIC_STATUS_MASK 0xFF
271 #define IPS_GSC_STATUS_MASK 0x0F
272 #define IPS_CMD_SUCCESS 0x00
273 #define IPS_CMD_RECOVERED_ERROR 0x01
274 #define IPS_INVAL_OPCO 0x03
275 #define IPS_INVAL_CMD_BLK 0x04
276 #define IPS_INVAL_PARM_BLK 0x05
277 #define IPS_BUSY 0x08
278 #define IPS_CMD_CMPLT_WERROR 0x0C
279 #define IPS_LD_ERROR 0x0D
280 #define IPS_CMD_TIMEOUT 0x0E
281 #define IPS_PHYS_DRV_ERROR 0x0F
282
283 /*
284 * Adapter Extended Status Equates
285 */
286 #define IPS_ERR_SEL_TO 0xF0
287 #define IPS_ERR_OU_RUN 0xF2
288 #define IPS_ERR_HOST_RESET 0xF7
289 #define IPS_ERR_DEV_RESET 0xF8
290 #define IPS_ERR_RECOVERY 0xFC
291 #define IPS_ERR_CKCOND 0xFF
292
293 /*
294 * Operating System Defines
295 */
296 #define IPS_OS_WINDOWS_NT 0x01
297 #define IPS_OS_NETWARE 0x02
298 #define IPS_OS_OPENSERVER 0x03
299 #define IPS_OS_UNIXWARE 0x04
300 #define IPS_OS_SOLARIS 0x05
301 #define IPS_OS_OS2 0x06
302 #define IPS_OS_LINUX 0x07
303 #define IPS_OS_FREEBSD 0x08
304
305 /*
306 * Adapter Revision ID's
307 */
308 #define IPS_REVID_SERVERAID 0x02
309 #define IPS_REVID_NAVAJO 0x03
310 #define IPS_REVID_SERVERAID2 0x04
311 #define IPS_REVID_CLARINETP1 0x05
312 #define IPS_REVID_CLARINETP2 0x07
313 #define IPS_REVID_CLARINETP3 0x0D
314 #define IPS_REVID_TROMBONE32 0x0F
315 #define IPS_REVID_TROMBONE64 0x10
316
317 /*
318 * NVRAM Page 5 Adapter Defines
319 */
320 #define IPS_ADTYPE_SERVERAID 0x01
321 #define IPS_ADTYPE_SERVERAID2 0x02
322 #define IPS_ADTYPE_NAVAJO 0x03
323 #define IPS_ADTYPE_KIOWA 0x04
324 #define IPS_ADTYPE_SERVERAID3 0x05
325 #define IPS_ADTYPE_SERVERAID3L 0x06
326 #define IPS_ADTYPE_SERVERAID4H 0x07
327 #define IPS_ADTYPE_SERVERAID4M 0x08
328 #define IPS_ADTYPE_SERVERAID4L 0x09
329 #define IPS_ADTYPE_SERVERAID4MX 0x0A
330 #define IPS_ADTYPE_SERVERAID4LX 0x0B
331 #define IPS_ADTYPE_SERVERAID5I2 0x0C
332 #define IPS_ADTYPE_SERVERAID5I1 0x0D
333 #define IPS_ADTYPE_SERVERAID6M 0x0E
334 #define IPS_ADTYPE_SERVERAID6I 0x0F
335 #define IPS_ADTYPE_SERVERAID7t 0x10
336 #define IPS_ADTYPE_SERVERAID7k 0x11
337 #define IPS_ADTYPE_SERVERAID7M 0x12
338
339 /*
340 * Adapter Command/Status Packet Definitions
341 */
342 #define IPS_SUCCESS 0x01 /* Successfully completed */
343 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
344 #define IPS_FAILURE 0x04 /* Completed with Error */
345
346 /*
347 * Logical Drive Equates
348 */
349 #define IPS_LD_OFFLINE 0x02
350 #define IPS_LD_OKAY 0x03
351 #define IPS_LD_FREE 0x00
352 #define IPS_LD_SYS 0x06
353 #define IPS_LD_CRS 0x24
354
355 /*
356 * DCDB Table Equates
357 */
358 #define IPS_NO_DISCONNECT 0x00
359 #define IPS_DISCONNECT_ALLOWED 0x80
360 #define IPS_NO_AUTO_REQSEN 0x40
361 #define IPS_DATA_NONE 0x00
362 #define IPS_DATA_UNK 0x00
363 #define IPS_DATA_IN 0x01
364 #define IPS_DATA_OUT 0x02
365 #define IPS_TRANSFER64K 0x08
366 #define IPS_NOTIMEOUT 0x00
367 #define IPS_TIMEOUT10 0x10
368 #define IPS_TIMEOUT60 0x20
369 #define IPS_TIMEOUT20M 0x30
370
371 /*
372 * SCSI Inquiry Data Flags
373 */
374 #define IPS_SCSI_INQ_TYPE_DASD 0x00
375 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
376 #define IPS_SCSI_INQ_LU_CONNECTED 0x00
377 #define IPS_SCSI_INQ_RD_REV2 0x02
378 #define IPS_SCSI_INQ_REV2 0x02
379 #define IPS_SCSI_INQ_REV3 0x03
380 #define IPS_SCSI_INQ_Address16 0x01
381 #define IPS_SCSI_INQ_Address32 0x02
382 #define IPS_SCSI_INQ_MedChanger 0x08
383 #define IPS_SCSI_INQ_MultiPort 0x10
384 #define IPS_SCSI_INQ_EncServ 0x40
385 #define IPS_SCSI_INQ_SoftReset 0x01
386 #define IPS_SCSI_INQ_CmdQue 0x02
387 #define IPS_SCSI_INQ_Linked 0x08
388 #define IPS_SCSI_INQ_Sync 0x10
389 #define IPS_SCSI_INQ_WBus16 0x20
390 #define IPS_SCSI_INQ_WBus32 0x40
391 #define IPS_SCSI_INQ_RelAdr 0x80
392
393 /*
394 * SCSI Request Sense Data Flags
395 */
396 #define IPS_SCSI_REQSEN_VALID 0x80
397 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
398 #define IPS_SCSI_REQSEN_NO_SENSE 0x00
399
400 /*
401 * SCSI Mode Page Equates
402 */
403 #define IPS_SCSI_MP3_SoftSector 0x01
404 #define IPS_SCSI_MP3_HardSector 0x02
405 #define IPS_SCSI_MP3_Removeable 0x04
406 #define IPS_SCSI_MP3_AllocateSurface 0x08
407
408 /*
409 * HA Flags
410 */
411
412 #define IPS_HA_ENH_SG 0x1
413
414 /*
415 * SCB Flags
416 */
417 #define IPS_SCB_MAP_SG 0x00008
418 #define IPS_SCB_MAP_SINGLE 0X00010
419
420 /*
421 * Passthru stuff
422 */
423 #define IPS_COPPUSRCMD (('C'<<8) | 65)
424 #define IPS_COPPIOCCMD (('C'<<8) | 66)
425 #define IPS_NUMCTRLS (('C'<<8) | 68)
426 #define IPS_CTRLINFO (('C'<<8) | 69)
427
428 /* flashing defines */
429 #define IPS_FW_IMAGE 0x00
430 #define IPS_BIOS_IMAGE 0x01
431 #define IPS_WRITE_FW 0x01
432 #define IPS_WRITE_BIOS 0x02
433 #define IPS_ERASE_BIOS 0x03
434 #define IPS_BIOS_HEADER 0xC0
435
436 /* time oriented stuff */
437 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
438 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
439
440 #define IPS_SECS_MIN 60
441 #define IPS_SECS_HOUR 3600
442 #define IPS_SECS_8HOURS 28800
443 #define IPS_SECS_DAY 86400
444 #define IPS_DAYS_NORMAL_YEAR 365
445 #define IPS_DAYS_LEAP_YEAR 366
446 #define IPS_EPOCH_YEAR 1970
447
448 /*
449 * Scsi_Host Template
450 */
451#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
452 static int ips_proc24_info(char *, char **, off_t, int, int, int);
Christoph Hellwigf64a1812005-10-31 18:32:08 +0100[diff] [blame]453 static void ips_select_queue_depth(struct Scsi_Host *, struct scsi_device *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]454 static int ips_biosparam(Disk *disk, kdev_t dev, int geom[]);
455#else
456 static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
457 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
458 sector_t capacity, int geom[]);
Christoph Hellwigf64a1812005-10-31 18:32:08 +0100[diff] [blame]459 static int ips_slave_configure(struct scsi_device *SDptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]460#endif
461
462/*
463 * Raid Command Formats
464 */
465typedef struct {
466 uint8_t op_code;
467 uint8_t command_id;
468 uint8_t log_drv;
469 uint8_t sg_count;
470 uint32_t lba;
471 uint32_t sg_addr;
472 uint16_t sector_count;
473 uint8_t segment_4G;
474 uint8_t enhanced_sg;
475 uint32_t ccsar;
476 uint32_t cccr;
477} IPS_IO_CMD, *PIPS_IO_CMD;
478
479typedef struct {
480 uint8_t op_code;
481 uint8_t command_id;
482 uint16_t reserved;
483 uint32_t reserved2;
484 uint32_t buffer_addr;
485 uint32_t reserved3;
486 uint32_t ccsar;
487 uint32_t cccr;
488} IPS_LD_CMD, *PIPS_LD_CMD;
489
490typedef struct {
491 uint8_t op_code;
492 uint8_t command_id;
493 uint8_t reserved;
494 uint8_t reserved2;
495 uint32_t reserved3;
496 uint32_t buffer_addr;
497 uint32_t reserved4;
498} IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
499
500typedef struct {
501 uint8_t op_code;
502 uint8_t command_id;
503 uint8_t channel;
504 uint8_t reserved3;
505 uint8_t reserved4;
506 uint8_t reserved5;
507 uint8_t reserved6;
508 uint8_t reserved7;
509 uint8_t reserved8;
510 uint8_t reserved9;
511 uint8_t reserved10;
512 uint8_t reserved11;
513 uint8_t reserved12;
514 uint8_t reserved13;
515 uint8_t reserved14;
516 uint8_t adapter_flag;
517} IPS_RESET_CMD, *PIPS_RESET_CMD;
518
519typedef struct {
520 uint8_t op_code;
521 uint8_t command_id;
522 uint16_t reserved;
523 uint32_t reserved2;
524 uint32_t dcdb_address;
525 uint16_t reserved3;
526 uint8_t segment_4G;
527 uint8_t enhanced_sg;
528 uint32_t ccsar;
529 uint32_t cccr;
530} IPS_DCDB_CMD, *PIPS_DCDB_CMD;
531
532typedef struct {
533 uint8_t op_code;
534 uint8_t command_id;
535 uint8_t channel;
536 uint8_t source_target;
537 uint32_t reserved;
538 uint32_t reserved2;
539 uint32_t reserved3;
540 uint32_t ccsar;
541 uint32_t cccr;
542} IPS_CS_CMD, *PIPS_CS_CMD;
543
544typedef struct {
545 uint8_t op_code;
546 uint8_t command_id;
547 uint8_t log_drv;
548 uint8_t control;
549 uint32_t reserved;
550 uint32_t reserved2;
551 uint32_t reserved3;
552 uint32_t ccsar;
553 uint32_t cccr;
554} IPS_US_CMD, *PIPS_US_CMD;
555
556typedef struct {
557 uint8_t op_code;
558 uint8_t command_id;
559 uint8_t reserved;
560 uint8_t state;
561 uint32_t reserved2;
562 uint32_t reserved3;
563 uint32_t reserved4;
564 uint32_t ccsar;
565 uint32_t cccr;
566} IPS_FC_CMD, *PIPS_FC_CMD;
567
568typedef struct {
569 uint8_t op_code;
570 uint8_t command_id;
571 uint8_t reserved;
572 uint8_t desc;
573 uint32_t reserved2;
574 uint32_t buffer_addr;
575 uint32_t reserved3;
576 uint32_t ccsar;
577 uint32_t cccr;
578} IPS_STATUS_CMD, *PIPS_STATUS_CMD;
579
580typedef struct {
581 uint8_t op_code;
582 uint8_t command_id;
583 uint8_t page;
584 uint8_t write;
585 uint32_t reserved;
586 uint32_t buffer_addr;
587 uint32_t reserved2;
588 uint32_t ccsar;
589 uint32_t cccr;
590} IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
591
592typedef struct
593{
594 uint8_t op_code;
595 uint8_t command_id;
596 uint16_t reserved;
597 uint32_t count;
598 uint32_t buffer_addr;
599 uint32_t reserved2;
600} IPS_VERSION_INFO, *PIPS_VERSION_INFO;
601
602typedef struct {
603 uint8_t op_code;
604 uint8_t command_id;
605 uint8_t reset_count;
606 uint8_t reset_type;
607 uint8_t second;
608 uint8_t minute;
609 uint8_t hour;
610 uint8_t day;
611 uint8_t reserved1[4];
612 uint8_t month;
613 uint8_t yearH;
614 uint8_t yearL;
615 uint8_t reserved2;
616} IPS_FFDC_CMD, *PIPS_FFDC_CMD;
617
618typedef struct {
619 uint8_t op_code;
620 uint8_t command_id;
621 uint8_t type;
622 uint8_t direction;
623 uint32_t count;
624 uint32_t buffer_addr;
625 uint8_t total_packets;
626 uint8_t packet_num;
627 uint16_t reserved;
628} IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
629
630typedef struct {
631 uint8_t op_code;
632 uint8_t command_id;
633 uint8_t type;
634 uint8_t direction;
635 uint32_t count;
636 uint32_t buffer_addr;
637 uint32_t offset;
638} IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
639
640typedef union {
641 IPS_IO_CMD basic_io;
642 IPS_LD_CMD logical_info;
643 IPS_IOCTL_CMD ioctl_info;
644 IPS_DCDB_CMD dcdb;
645 IPS_CS_CMD config_sync;
646 IPS_US_CMD unlock_stripe;
647 IPS_FC_CMD flush_cache;
648 IPS_STATUS_CMD status;
649 IPS_NVRAM_CMD nvram;
650 IPS_FFDC_CMD ffdc;
651 IPS_FLASHFW_CMD flashfw;
652 IPS_FLASHBIOS_CMD flashbios;
653 IPS_VERSION_INFO version_info;
654 IPS_RESET_CMD reset;
655} IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
656
657typedef struct {
658 uint8_t logical_id;
659 uint8_t reserved;
660 uint8_t raid_level;
661 uint8_t state;
662 uint32_t sector_count;
663} IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
664
665typedef struct {
666 uint8_t no_of_log_drive;
667 uint8_t reserved[3];
668 IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
669} IPS_LD_INFO, *PIPS_LD_INFO;
670
671typedef struct {
672 uint8_t device_address;
673 uint8_t cmd_attribute;
674 uint16_t transfer_length;
675 uint32_t buffer_pointer;
676 uint8_t cdb_length;
677 uint8_t sense_length;
678 uint8_t sg_count;
679 uint8_t reserved;
680 uint8_t scsi_cdb[12];
681 uint8_t sense_info[64];
682 uint8_t scsi_status;
683 uint8_t reserved2[3];
684} IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
685
686typedef struct {
687 uint8_t device_address;
688 uint8_t cmd_attribute;
689 uint8_t cdb_length;
690 uint8_t reserved_for_LUN;
691 uint32_t transfer_length;
692 uint32_t buffer_pointer;
693 uint16_t sg_count;
694 uint8_t sense_length;
695 uint8_t scsi_status;
696 uint32_t reserved;
697 uint8_t scsi_cdb[16];
698 uint8_t sense_info[56];
699} IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
700
701typedef union {
702 struct {
703 volatile uint8_t reserved;
704 volatile uint8_t command_id;
705 volatile uint8_t basic_status;
706 volatile uint8_t extended_status;
707 } fields;
708
709 volatile uint32_t value;
710} IPS_STATUS, *PIPS_STATUS;
711
712typedef struct {
713 IPS_STATUS status[IPS_MAX_CMDS + 1];
714 volatile PIPS_STATUS p_status_start;
715 volatile PIPS_STATUS p_status_end;
716 volatile PIPS_STATUS p_status_tail;
717 volatile uint32_t hw_status_start;
718 volatile uint32_t hw_status_tail;
719} IPS_ADAPTER, *PIPS_ADAPTER;
720
721typedef struct {
722 uint8_t ucLogDriveCount;
723 uint8_t ucMiscFlag;
724 uint8_t ucSLTFlag;
725 uint8_t ucBSTFlag;
726 uint8_t ucPwrChgCnt;
727 uint8_t ucWrongAdrCnt;
728 uint8_t ucUnidentCnt;
729 uint8_t ucNVramDevChgCnt;
730 uint8_t CodeBlkVersion[8];
731 uint8_t BootBlkVersion[8];
732 uint32_t ulDriveSize[IPS_MAX_LD];
733 uint8_t ucConcurrentCmdCount;
734 uint8_t ucMaxPhysicalDevices;
735 uint16_t usFlashRepgmCount;
736 uint8_t ucDefunctDiskCount;
737 uint8_t ucRebuildFlag;
738 uint8_t ucOfflineLogDrvCount;
739 uint8_t ucCriticalDrvCount;
740 uint16_t usConfigUpdateCount;
741 uint8_t ucBlkFlag;
742 uint8_t reserved;
743 uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
744} IPS_ENQ, *PIPS_ENQ;
745
746typedef struct {
747 uint8_t ucInitiator;
748 uint8_t ucParameters;
749 uint8_t ucMiscFlag;
750 uint8_t ucState;
751 uint32_t ulBlockCount;
752 uint8_t ucDeviceId[28];
753} IPS_DEVSTATE, *PIPS_DEVSTATE;
754
755typedef struct {
756 uint8_t ucChn;
757 uint8_t ucTgt;
758 uint16_t ucReserved;
759 uint32_t ulStartSect;
760 uint32_t ulNoOfSects;
761} IPS_CHUNK, *PIPS_CHUNK;
762
763typedef struct {
764 uint16_t ucUserField;
765 uint8_t ucState;
766 uint8_t ucRaidCacheParam;
767 uint8_t ucNoOfChunkUnits;
768 uint8_t ucStripeSize;
769 uint8_t ucParams;
770 uint8_t ucReserved;
771 uint32_t ulLogDrvSize;
772 IPS_CHUNK chunk[IPS_MAX_CHUNKS];
773} IPS_LD, *PIPS_LD;
774
775typedef struct {
776 uint8_t board_disc[8];
777 uint8_t processor[8];
778 uint8_t ucNoChanType;
779 uint8_t ucNoHostIntType;
780 uint8_t ucCompression;
781 uint8_t ucNvramType;
782 uint32_t ulNvramSize;
783} IPS_HARDWARE, *PIPS_HARDWARE;
784
785typedef struct {
786 uint8_t ucLogDriveCount;
787 uint8_t ucDateD;
788 uint8_t ucDateM;
789 uint8_t ucDateY;
790 uint8_t init_id[4];
791 uint8_t host_id[12];
792 uint8_t time_sign[8];
793 uint32_t UserOpt;
794 uint16_t user_field;
795 uint8_t ucRebuildRate;
796 uint8_t ucReserve;
797 IPS_HARDWARE hardware_disc;
798 IPS_LD logical_drive[IPS_MAX_LD];
799 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
800 uint8_t reserved[512];
801} IPS_CONF, *PIPS_CONF;
802
803typedef struct {
804 uint32_t signature;
805 uint8_t reserved1;
806 uint8_t adapter_slot;
807 uint16_t adapter_type;
808 uint8_t ctrl_bios[8];
809 uint8_t versioning; /* 1 = Versioning Supported, else 0 */
810 uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */
811 uint8_t reserved2;
812 uint8_t operating_system;
813 uint8_t driver_high[4];
814 uint8_t driver_low[4];
815 uint8_t BiosCompatibilityID[8];
816 uint8_t ReservedForOS2[8];
817 uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */
818 uint8_t bios_low[4];
819 uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */
820 uint8_t Filler[60];
821} IPS_NVRAM_P5, *PIPS_NVRAM_P5;
822
823/*--------------------------------------------------------------------------*/
824/* Data returned from a GetVersion Command */
825/*--------------------------------------------------------------------------*/
826
827 /* SubSystem Parameter[4] */
828#define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
829
830typedef struct
831{
832 uint32_t revision;
833 uint8_t bootBlkVersion[32];
834 uint8_t bootBlkAttributes[4];
835 uint8_t codeBlkVersion[32];
836 uint8_t biosVersion[32];
837 uint8_t biosAttributes[4];
838 uint8_t compatibilityId[32];
839 uint8_t reserved[4];
840} IPS_VERSION_DATA;
841
842
843typedef struct _IPS_SUBSYS {
844 uint32_t param[128];
845} IPS_SUBSYS, *PIPS_SUBSYS;
846
847/**
848 ** SCSI Structures
849 **/
850
851/*
852 * Inquiry Data Format
853 */
854typedef struct {
855 uint8_t DeviceType;
856 uint8_t DeviceTypeQualifier;
857 uint8_t Version;
858 uint8_t ResponseDataFormat;
859 uint8_t AdditionalLength;
860 uint8_t Reserved;
861 uint8_t Flags[2];
862 uint8_t VendorId[8];
863 uint8_t ProductId[16];
864 uint8_t ProductRevisionLevel[4];
865 uint8_t Reserved2; /* Provides NULL terminator to name */
866} IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
867
868/*
869 * Read Capacity Data Format
870 */
871typedef struct {
872 uint32_t lba;
873 uint32_t len;
874} IPS_SCSI_CAPACITY;
875
876/*
877 * Request Sense Data Format
878 */
879typedef struct {
880 uint8_t ResponseCode;
881 uint8_t SegmentNumber;
882 uint8_t Flags;
883 uint8_t Information[4];
884 uint8_t AdditionalLength;
885 uint8_t CommandSpecific[4];
886 uint8_t AdditionalSenseCode;
887 uint8_t AdditionalSenseCodeQual;
888 uint8_t FRUCode;
889 uint8_t SenseKeySpecific[3];
890} IPS_SCSI_REQSEN;
891
892/*
893 * Sense Data Format - Page 3
894 */
895typedef struct {
896 uint8_t PageCode;
897 uint8_t PageLength;
898 uint16_t TracksPerZone;
899 uint16_t AltSectorsPerZone;
900 uint16_t AltTracksPerZone;
901 uint16_t AltTracksPerVolume;
902 uint16_t SectorsPerTrack;
903 uint16_t BytesPerSector;
904 uint16_t Interleave;
905 uint16_t TrackSkew;
906 uint16_t CylinderSkew;
907 uint8_t flags;
908 uint8_t reserved[3];
909} IPS_SCSI_MODE_PAGE3;
910
911/*
912 * Sense Data Format - Page 4
913 */
914typedef struct {
915 uint8_t PageCode;
916 uint8_t PageLength;
917 uint16_t CylindersHigh;
918 uint8_t CylindersLow;
919 uint8_t Heads;
920 uint16_t WritePrecompHigh;
921 uint8_t WritePrecompLow;
922 uint16_t ReducedWriteCurrentHigh;
923 uint8_t ReducedWriteCurrentLow;
924 uint16_t StepRate;
925 uint16_t LandingZoneHigh;
926 uint8_t LandingZoneLow;
927 uint8_t flags;
928 uint8_t RotationalOffset;
929 uint8_t Reserved;
930 uint16_t MediumRotationRate;
931 uint8_t Reserved2[2];
932} IPS_SCSI_MODE_PAGE4;
933
934/*
935 * Sense Data Format - Page 8
936 */
937typedef struct {
938 uint8_t PageCode;
939 uint8_t PageLength;
940 uint8_t flags;
941 uint8_t RetentPrio;
942 uint16_t DisPrefetchLen;
943 uint16_t MinPrefetchLen;
944 uint16_t MaxPrefetchLen;
945 uint16_t MaxPrefetchCeiling;
946} IPS_SCSI_MODE_PAGE8;
947
948/*
949 * Sense Data Format - Block Descriptor (DASD)
950 */
951typedef struct {
952 uint32_t NumberOfBlocks;
953 uint8_t DensityCode;
954 uint16_t BlockLengthHigh;
955 uint8_t BlockLengthLow;
956} IPS_SCSI_MODE_PAGE_BLKDESC;
957
958/*
959 * Sense Data Format - Mode Page Header
960 */
961typedef struct {
962 uint8_t DataLength;
963 uint8_t MediumType;
964 uint8_t Reserved;
965 uint8_t BlockDescLength;
966} IPS_SCSI_MODE_PAGE_HEADER;
967
968typedef struct {
969 IPS_SCSI_MODE_PAGE_HEADER hdr;
970 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
971
972 union {
973 IPS_SCSI_MODE_PAGE3 pg3;
974 IPS_SCSI_MODE_PAGE4 pg4;
975 IPS_SCSI_MODE_PAGE8 pg8;
976 } pdata;
977} IPS_SCSI_MODE_PAGE_DATA;
978
979/*
980 * Scatter Gather list format
981 */
982typedef struct ips_sglist {
983 uint32_t address;
984 uint32_t length;
985} IPS_STD_SG_LIST;
986
987typedef struct ips_enh_sglist {
988 uint32_t address_lo;
989 uint32_t address_hi;
990 uint32_t length;
991 uint32_t reserved;
992} IPS_ENH_SG_LIST;
993
994typedef union {
995 void *list;
996 IPS_STD_SG_LIST *std_list;
997 IPS_ENH_SG_LIST *enh_list;
998} IPS_SG_LIST;
999
1000typedef struct _IPS_INFOSTR {
1001 char *buffer;
1002 int length;
1003 int offset;
1004 int pos;
1005 int localpos;
1006} IPS_INFOSTR;
1007
1008typedef struct {
1009 char *option_name;
1010 int *option_flag;
1011 int option_value;
1012} IPS_OPTION;
1013
1014/*
1015 * Status Info
1016 */
1017typedef struct ips_stat {
1018 uint32_t residue_len;
1019 void *scb_addr;
1020 uint8_t padding[12 - sizeof(void *)];
1021} ips_stat_t;
1022
1023/*
1024 * SCB Queue Format
1025 */
1026typedef struct ips_scb_queue {
1027 struct ips_scb *head;
1028 struct ips_scb *tail;
1029 int count;
1030} ips_scb_queue_t;
1031
1032/*
1033 * Wait queue_format
1034 */
1035typedef struct ips_wait_queue {
1036 Scsi_Cmnd *head;
1037 Scsi_Cmnd *tail;
1038 int count;
1039} ips_wait_queue_t;
1040
1041typedef struct ips_copp_wait_item {
1042 Scsi_Cmnd *scsi_cmd;
1043 struct ips_copp_wait_item *next;
1044} ips_copp_wait_item_t;
1045
1046typedef struct ips_copp_queue {
1047 struct ips_copp_wait_item *head;
1048 struct ips_copp_wait_item *tail;
1049 int count;
1050} ips_copp_queue_t;
1051
1052/* forward decl for host structure */
1053struct ips_ha;
1054
1055typedef struct {
1056 int (*reset)(struct ips_ha *);
1057 int (*issue)(struct ips_ha *, struct ips_scb *);
1058 int (*isinit)(struct ips_ha *);
1059 int (*isintr)(struct ips_ha *);
1060 int (*init)(struct ips_ha *);
1061 int (*erasebios)(struct ips_ha *);
1062 int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
1063 int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
1064 void (*statinit)(struct ips_ha *);
1065 int (*intr)(struct ips_ha *);
1066 void (*enableint)(struct ips_ha *);
1067 uint32_t (*statupd)(struct ips_ha *);
1068} ips_hw_func_t;
1069
1070typedef struct ips_ha {
1071 uint8_t ha_id[IPS_MAX_CHANNELS+1];
1072 uint32_t dcdb_active[IPS_MAX_CHANNELS];
1073 uint32_t io_addr; /* Base I/O address */
1074 uint8_t irq; /* IRQ for adapter */
1075 uint8_t ntargets; /* Number of targets */
1076 uint8_t nbus; /* Number of buses */
1077 uint8_t nlun; /* Number of Luns */
1078 uint16_t ad_type; /* Adapter type */
1079 uint16_t host_num; /* Adapter number */
1080 uint32_t max_xfer; /* Maximum Xfer size */
1081 uint32_t max_cmds; /* Max concurrent commands */
1082 uint32_t num_ioctl; /* Number of Ioctls */
1083 ips_stat_t sp; /* Status packer pointer */
1084 struct ips_scb *scbs; /* Array of all CCBS */
1085 struct ips_scb *scb_freelist; /* SCB free list */
1086 ips_wait_queue_t scb_waitlist; /* Pending SCB list */
1087 ips_copp_queue_t copp_waitlist; /* Pending PT list */
1088 ips_scb_queue_t scb_activelist; /* Active SCB list */
1089 IPS_IO_CMD *dummy; /* dummy command */
1090 IPS_ADAPTER *adapt; /* Adapter status area */
1091 IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */
1092 dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
1093 IPS_ENQ *enq; /* Adapter Enquiry data */
1094 IPS_CONF *conf; /* Adapter config data */
1095 IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */
1096 IPS_SUBSYS *subsys; /* Subsystem parameters */
1097 char *ioctl_data; /* IOCTL data area */
1098 uint32_t ioctl_datasize; /* IOCTL data size */
1099 uint32_t cmd_in_progress; /* Current command in progress*/
1100 int flags; /* */
1101 uint8_t waitflag; /* are we waiting for cmd */
1102 uint8_t active;
1103 int ioctl_reset; /* IOCTL Requested Reset Flag */
1104 uint16_t reset_count; /* number of resets */
1105 time_t last_ffdc; /* last time we sent ffdc info*/
1106 uint8_t revision_id; /* Revision level */
1107 uint16_t device_id; /* PCI device ID */
1108 uint8_t slot_num; /* PCI Slot Number */
1109 uint16_t subdevice_id; /* Subsystem device ID */
1110 int ioctl_len; /* size of ioctl buffer */
1111 dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/
1112 uint8_t bios_version[8]; /* BIOS Revision */
1113 uint32_t mem_addr; /* Memory mapped address */
1114 uint32_t io_len; /* Size of IO Address */
1115 uint32_t mem_len; /* Size of memory address */
1116 char __iomem *mem_ptr; /* Memory mapped Ptr */
1117 char __iomem *ioremap_ptr;/* ioremapped memory pointer */
1118 ips_hw_func_t func; /* hw function pointers */
1119 struct pci_dev *pcidev; /* PCI device handle */
1120 char *flash_data; /* Save Area for flash data */
1121 int flash_len; /* length of flash buffer */
1122 u32 flash_datasize; /* Save Area for flash data size */
1123 dma_addr_t flash_busaddr; /* dma address of flash buffer*/
1124 dma_addr_t enq_busaddr; /* dma address of enq struct */
1125 uint8_t requires_esl; /* Requires an EraseStripeLock */
1126} ips_ha_t;
1127
1128typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1129
1130/*
1131 * SCB Format
1132 */
1133typedef struct ips_scb {
1134 IPS_HOST_COMMAND cmd;
1135 IPS_DCDB_TABLE dcdb;
1136 uint8_t target_id;
1137 uint8_t bus;
1138 uint8_t lun;
1139 uint8_t cdb[12];
1140 uint32_t scb_busaddr;
1141 uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility
1142 uint32_t timeout;
1143 uint8_t basic_status;
1144 uint8_t extended_status;
1145 uint8_t breakup;
1146 uint8_t sg_break;
1147 uint32_t data_len;
1148 uint32_t sg_len;
1149 uint32_t flags;
1150 uint32_t op_code;
1151 IPS_SG_LIST sg_list;
1152 Scsi_Cmnd *scsi_cmd;
1153 struct ips_scb *q_next;
1154 ips_scb_callback callback;
1155 uint32_t sg_busaddr;
1156 int sg_count;
1157 dma_addr_t data_busaddr;
1158} ips_scb_t;
1159
1160typedef struct ips_scb_pt {
1161 IPS_HOST_COMMAND cmd;
1162 IPS_DCDB_TABLE dcdb;
1163 uint8_t target_id;
1164 uint8_t bus;
1165 uint8_t lun;
1166 uint8_t cdb[12];
1167 uint32_t scb_busaddr;
1168 uint32_t data_busaddr;
1169 uint32_t timeout;
1170 uint8_t basic_status;
1171 uint8_t extended_status;
1172 uint16_t breakup;
1173 uint32_t data_len;
1174 uint32_t sg_len;
1175 uint32_t flags;
1176 uint32_t op_code;
1177 IPS_SG_LIST *sg_list;
1178 Scsi_Cmnd *scsi_cmd;
1179 struct ips_scb *q_next;
1180 ips_scb_callback callback;
1181} ips_scb_pt_t;
1182
1183/*
1184 * Passthru Command Format
1185 */
1186typedef struct {
1187 uint8_t CoppID[4];
1188 uint32_t CoppCmd;
1189 uint32_t PtBuffer;
1190 uint8_t *CmdBuffer;
1191 uint32_t CmdBSize;
1192 ips_scb_pt_t CoppCP;
1193 uint32_t TimeOut;
1194 uint8_t BasicStatus;
1195 uint8_t ExtendedStatus;
1196 uint8_t AdapterType;
1197 uint8_t reserved;
1198} ips_passthru_t;
1199
1200#endif
1201
1202/* The Version Information below gets created by SED during the build process. */
1203/* Do not modify the next line; it's what SED is looking for to do the insert. */
1204/* Version Info */
1205/*************************************************************************
1206*
1207* VERSION.H -- version numbers and copyright notices in various formats
1208*
1209*************************************************************************/
1210
1211#define IPS_VER_MAJOR 7
1212#define IPS_VER_MAJOR_STRING "7"
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]1213#define IPS_VER_MINOR 12
1214#define IPS_VER_MINOR_STRING "12"
1215#define IPS_VER_BUILD 02
1216#define IPS_VER_BUILD_STRING "02"
1217#define IPS_VER_STRING "7.12.02"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1218#define IPS_RELEASE_ID 0x00020000
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]1219#define IPS_BUILD_IDENT 761
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1220#define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1221#define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1222#define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1223#define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1224
1225/* Version numbers for various adapters */
1226#define IPS_VER_SERVERAID1 "2.25.01"
1227#define IPS_VER_SERVERAID2 "2.88.13"
1228#define IPS_VER_NAVAJO "2.88.13"
1229#define IPS_VER_SERVERAID3 "6.10.24"
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]1230#define IPS_VER_SERVERAID4H "7.12.02"
1231#define IPS_VER_SERVERAID4MLx "7.12.02"
1232#define IPS_VER_SARASOTA "7.12.02"
1233#define IPS_VER_MARCO "7.12.02"
1234#define IPS_VER_SEBRING "7.12.02"
1235#define IPS_VER_KEYWEST "7.12.02"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1236
1237/* Compatability IDs for various adapters */
1238#define IPS_COMPAT_UNKNOWN ""
1239#define IPS_COMPAT_CURRENT "KW710"
1240#define IPS_COMPAT_SERVERAID1 "2.25.01"
1241#define IPS_COMPAT_SERVERAID2 "2.88.13"
1242#define IPS_COMPAT_NAVAJO "2.88.13"
1243#define IPS_COMPAT_KIOWA "2.88.13"
1244#define IPS_COMPAT_SERVERAID3H "SB610"
1245#define IPS_COMPAT_SERVERAID3L "SB610"
1246#define IPS_COMPAT_SERVERAID4H "KW710"
1247#define IPS_COMPAT_SERVERAID4M "KW710"
1248#define IPS_COMPAT_SERVERAID4L "KW710"
1249#define IPS_COMPAT_SERVERAID4Mx "KW710"
1250#define IPS_COMPAT_SERVERAID4Lx "KW710"
1251#define IPS_COMPAT_SARASOTA "KW710"
1252#define IPS_COMPAT_MARCO "KW710"
1253#define IPS_COMPAT_SEBRING "KW710"
1254#define IPS_COMPAT_TAMPA "KW710"
1255#define IPS_COMPAT_KEYWEST "KW710"
1256#define IPS_COMPAT_BIOS "KW710"
1257
1258#define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1259#define IPS_COMPAT_ID_LENGTH 8
1260
1261#define IPS_DEFINE_COMPAT_TABLE(tablename) \
1262 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1263 IPS_COMPAT_UNKNOWN, \
1264 IPS_COMPAT_SERVERAID1, \
1265 IPS_COMPAT_SERVERAID2, \
1266 IPS_COMPAT_NAVAJO, \
1267 IPS_COMPAT_KIOWA, \
1268 IPS_COMPAT_SERVERAID3H, \
1269 IPS_COMPAT_SERVERAID3L, \
1270 IPS_COMPAT_SERVERAID4H, \
1271 IPS_COMPAT_SERVERAID4M, \
1272 IPS_COMPAT_SERVERAID4L, \
1273 IPS_COMPAT_SERVERAID4Mx, \
1274 IPS_COMPAT_SERVERAID4Lx, \
1275 IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
1276 IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
1277 IPS_COMPAT_MARCO, \
1278 IPS_COMPAT_SEBRING, \
1279 IPS_COMPAT_TAMPA, \
1280 IPS_COMPAT_KEYWEST \
1281 }
1282
1283
1284/*
1285 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1286 * Emacs will notice this stuff at the end of the file and automatically
1287 * adjust the settings for this buffer only. This must remain at the end
1288 * of the file.
1289 * ---------------------------------------------------------------------------
1290 * Local variables:
1291 * c-indent-level: 2
1292 * c-brace-imaginary-offset: 0
1293 * c-brace-offset: -2
1294 * c-argdecl-indent: 2
1295 * c-label-offset: -2
1296 * c-continued-statement-offset: 2
1297 * c-continued-brace-offset: 0
1298 * indent-tabs-mode: nil
1299 * tab-width: 8
1300 * End:
1301 */